IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE

A GSM Receiver Front-End in 65nm Digital CMOS Process

See Taur Lee and Solti Peng
Texas Instruments Inc., 12500 TI Boulevard, Dallas TX75243

In the intense competition on a fully integrated QuadBand GSM/GPRS transceiver using purely digital CMOS
process [1], die area has been the most important factor to
reduce the cost of the product. The fully integrated
transceiver should maintain the same or better
performances than standalone ICs. Deep submicron
CMOS process has been the key to pack more transistors
and also to reduce the cost. An estimated of 35-40% die
shrink is expected from a 90nm to 65nm node.
In this work, a highly compact low-voltage low-current
GSM 850MHz receiver front-end has been implemented
using a standard 65nm digital CMOS process. The
receiver is based on a direct conversion technique as
depicted in Figure 1. It consists of an LNA, an IQ passive
mixer with pre-gain stages and a divde-by-4. The
differential LNA outputs are connected to the IQ mixing
circuits which convert the RF input signal into quadrature
baseband signals. The low-pass filter is a simple RC filter
that limits the baseband bandwidth and also helps to
reduce strong blockers power for the linearity of the
analog-to-digital converters that will be the subsequent
blocks in the receiver chain. To achieve the goal of 3545% die size shrink, the LNA used resistors as loads and
realized an inductor-less LNA by implementing the
degeneration inductors using bondwires. Circuit
techniques have been used extensively in the I/Q mixers
to achieve good performances with limited die area.
A detailed discussion of the LNA and I/Q mixer
designs follows. The paper is concluded with
measurement results and conclusions.

0-7803-9023-7/05/$20.00 2005 IEEE.

The proposed highly compact resistor load LNA is

shown in Figure 2. The RF inputs are ac-coupled and
going into transistors M1 and M2 with cascode transistors
M3 and M4. Inductors L1 and L2 are used as
degeneration inductor and also for input matching. The
conventional monolithic inductive load [2] has been
replaced with resistive load RL. The advantages of using
resistive load versus inductive load are as follows. With
inductive load, tuning mechanism is required to maintain
the LNA gain due to the inductance variation over process
and temperature and this increases the die area and
complicates the design. Furthermore, with the pressure of
die area, the capacitor bank is usually implemented using
MOS capacitor. Under large blocker power, this capacitor
can be very nonlinear and also the device will have
reliability issues.
Receiver IC
LPFI

Receiver Front-end

RFIN

LNA

OUTBB,I

I. INTRODUCTION

II. LNA DESIGN

4xfLO
LPFQ

OUTBB,Q

ABSTRACT A highly compact 18.6mA, 1.5V GSM

850MHz receiver front-end implemented in a standard 65nm
digital CMOS process is presented. It achieves 33dB of gain
with noise figure of 1.7dB, in-band IIP3 of -9.9dBm and IIP2
greater than 31 dBm. The P1dB is -26.5dBm and the P1dB
with -25dBm blocker at 3MHz offset is -23.1dBm. It occupies
an area of just 0.43 mm2.
Index Terms GSM, LNA, Mixer, I/Q demodulator, 1dB
compression point (P1dB), second-order input intercept
point (IIP2), third-order input intercept point (IIP3),
conversion gain, noise figure (NF).

Figure 1. Direct conversion receiver front-end.

In the current design, the LNA has a resistive load

implemented using NWELL resistor. This allows a very
compact LNA being designed. In addition, the
degeneration inductors which are implemented using a
monolithic inductor in this test chip can be easily replaced
by bondwires which is the goal of this design to realize an
inductor-less LNA. The disadvantage of using the
resistive load is the degradation on 1-dB gain
compression point (P1dB) if it is output limited. Another
disadvantage of using resistive load is the large resistance
value variation over process and temperature. This large
variation of resistance value leads to large variation of dc

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349

VDD

M10

RL

M12
M11

RL
VO-

VO+
Rfb

Rfb
M6
VREF

M7

M8

M3

M4

M1

M2

M13
M5
OP AMP
RFM9

RF+

L2

L1

VSS

Figure 2. LNA schematic.

output voltage. It has been demonstrated [3] that keeping

constant dc voltage at the output has the advantage of
maintaining more consistent second-order and third-order
intercept point (IIP2 and IIP3). In order to maintain the dc
voltage at the LNA output over process and temperature
variation, a common mode feedback circuit which adjusts
the dc bias current through the LNA is designed. The
common mode voltage is sensed through resistors Rfb and
compare with VREF using an operational amplifier. The
operational amplifier controls transistor M13 which act as
a voltage control current source and through current
mirror to complete the negative feedback loop. From first
order approximation, the LNA gain can be expressed as

Gain

1
u RL ,
2Zo Ls

where Zo is the operating frequency, Ls is the

degeneration inductor and RL is the load resistance. The
simulated gain variation over process and temperature is
less than 2dB. Any gain variation over process and
temperature can be digitally calibrated by connecting
more or less resistors in parallel to the load resistors.
This LNA occupies an area of just 210x110Pm2. It
includes a 2KV ESD and bonding pads. The operational
amplifier and the ESD are packed underneath the pads
using only metal 1. Metal 2 has been used as a ground
shield. The simulated NF including all the parasitic is
about 1dB with a gain of 26dB.

350

III. MIXER DESIGN

The mixer design is based on the passive topology
owing to the advantages of high linearity and low noise.
Due to its passive nature, the mixer does not possess gain.
In order to obtain the overall gain from a passive mixer a
gain stage is added prior to the passive mixer to boost up
the overall mixer gain as well as to improve the mixer
noise figure.
A common-source amplifier is used as the gain stage in
this design. This amplifier takes the output from the LNA
directly through a dc blocking capacitor. It has a cascode
structure with a resistor load. Cascode structure gives
better isolation between input and output. The resistor
load provides a more constant load during output swing,
thus better linearity.
The basic structure of this mixer is shown in Figure 3.
An ac couple capacitor is placed between the gain stage
and the mixer switch. There are two purposes for this
capacitor. One is the ability to select optimal biasing
voltage for the gain stage output and switch
independently. The other is to eliminate the mismatch
effect in the gain stage if differential topology is used.
The overall mixer gain can be easily derived from this
basic structure as follows.
Av |

g m RL ,

where gm is the transconductance of the input device and a

perfect switch is assumed (the 2/S factor).

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Common-Source Amplifier
VDD
RL

VDD  VREF
RL

LO

Passive Mixer

VREF Generator

Amplifier Replica

Vsw

VDD
IF

Iinj

VREF
CL

Vcas

Vcas
Ibias

Vgs

I bias
RF

V  VREF
I inj  DD
RL

VREF
OP AMP

Figure 3. Mixer basic structure

Vgs
To bias the input
device of the gain
stage

VSS

The output capacitor (CL) along with the commonsource amplifier load resistor sets the mixer bandwidth.
The bandwidth needs to be set around 300kHz for GSM
application in order to filter out some of the 400kHz
blocker signal. Due to this small bandwidth, large
resistance and/or capacitance values are required. Large
capacitance value means large chip real estate. Large
resistance value means large gain and large voltage drop
across it, which could hurt linearity performance and
P1dB. To counteract this effect, current has to be reduced.
Reduced current may hurt noise performance. So there is
a tradeoff between the chip size, gain, linearity and noise
performance.
To overcome the tradeoff, we used a current injection
scheme in which we still can maintain the amount of
current flowing through the input transistor (Ibias) to
achieve the required noise performance and at the same
time to have the right amount of voltage drop across the
load resistor. This current injection scheme is also shown
in Figure 3. The output dc voltage (VREF) is maintained
through a similar feedback circuit to the one used in LNA
as shown in Figure 4. This feedback circuit uses a replica
of the amplifier (a scale-down version) instead of sensing
the common mode voltage directly from the amplifier
output. The current injection scheme is also included in
the feedback circuit. Normally linearity and P1dB
requirements determine the output dc voltage (VREF),
while noise performance dictates the device biasing
current (Ibias). The current difference is compensated
through the injected current (Iinj).
This mixer is designed as a full I/Q demodulator in a
differential topology. In order to reduce the IF output
capacitor physical size, we stacked MIM (metal-metal)
capacitor on top MOS capacitor. The MIM capacitor is
connected differentially while MOS capacitor is
connected single-ended. By doing this we can save about

Figure 4. Biasing circuit for mixer gain stage.

36% of chip area compared to using the MOS capacitor

alone.
MOS capacitor is quite nonlinear at low bias voltage. In
order to avoid the nonlinear region, high bias voltage is
required (high Vsw). Therefore a PMOS switch is used
instead of NMOS switch, even though the PMOS has
higher on-resistance than its counterpart NMOS. However
an advantage of using PMOS is that PMOS has its own
well and the coupling through substrate could be less
compared to NMOS device.
A divide-by-4 is also included in this I/Q demodulator.
It takes 4 times of the RF frequency and generates
differential quadrature signals used as the LO input to the
I/Q demodulator. To take advantage of the speed of deep
submicron CMOS process we use a switch type divider
[3]. The outputs from the divider are rail-to-rail signals
and can be used to directly drive the mixer switches. It
helps to obtain better conversion gain and noise figure.
This I/Q demodulator, including divide-by-4 and LO
buffer, occupies an area of about 0.41mm2. 94% of the
area is actually occupied by the IF capacitor. The
simulated NF is about 12dB (single-side band) with a
voltage gain of 8dB.
IV. EXPERIMENT RESULTS

This receiver front end is fabricated using a 65nm

advanced digital CMOS process. A die photo of the whole
front end is shown in Figure 5. The total area of the LNA
and mixer occupied about 0.43 mm2. 90% of the area is
occupied by the IF capacitor. The die is packaged in a
chip scale ball grid array package and tested on a FR4
board. A RF balun is used on the board to provide
differential input to the LNA. The mixer takes a singleended signal with 4 times LO frequency. A single-ended

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351

to differential converter is included on the die to generate

the differential input signals for the divider just for testing
purpose.

Mixer

frequencies are chosen for the test. Thus, 40kHz is the

third-order IM product and 30kHz is the second-order IM
product. The results of P1dB, IIP2 and IIP3 are plotted in
Figure 6.
A complete performance of this receiver front-end is
listed in Table 2. Clearly the results show adequate
performance for GSM application using the 65nm CMOS
process with low supply voltage.

LN

IF Capacitor

Figure 5. Die photo.

1.5V supply is used for the whole front end (LNA,

mixer and divider). The chip is mainly tested at 880MHz.
We have measured the noise figure (NF), P1dB, IIP2 and
IIP3 of the overall LNA/mixer chain.
The noise figure at various spot frequencies (1kHz,
10kHz, 50kHz and 100kHz) is measured. A summary of
the noise performance is listed in Table 1.

Noise Figure (NF)

1.7 dB

NF with -25dBm blocker @ 3MHz offset

5.2 dB

S11

-16 dB

IIP2 (In-band)

31.5 dBm

IIP3 (In-band)

-9.9 dBm

P1dB

-26.5 dBm

P1dB under blocker

-23.1 dBm

Gain

33 dB

Total current consumption @ 1.5V

18.6 mA

LNA

8.0 mA

I/Q Demodulator

6.6 mA

Divider

4.0 mA

Table 2. Overall performance of the receiver front-end.

@1kHz

@10kHz

@50kHz

@100kHz

IV. CONCLUSION

Noise

2.87

Figure

1.85

1.72

1.56

(dB)

Table 1. Noise figure at 880MHz.

For two-tone intercept point tests we select two tones

which generate the IF products well within the mixer
bandwidth as well as their third-order and second-order
intermodulation (IM) byproducts. 70kHz and 100kHz IF

We have demonstrated a GSM receiver front-end in

65nm advanced digital CMOS process. The overall results
show very adequate performance for GSM application.
This leads to a possible solution of very high integration,
small die size and low cost for GSM in very deep
submicron CMOS digital process. Activity to a final
quad-band GSM solution in this 65nm digital CMOS
process is currently underway.

Output Power (dBm)

REFERENCES
80
60
40
20

IIP2=31.5dB

[1] Ozan E. Erdogan, et al., A Single-Chip Quad-Band

GSM/GPRS Transceiver in 0.18Pm Standard CMOS, in
ISSCC Dig. Tech. Papers, 2005, pp. 318319.
[2] Leroux, et al., A 0.8dB NF ESD-protected 9mW CMOS
LNA, in ISSCC Dig. Tech. Papers, 2001, pp. 410411.
[3] Solti Peng, et al., A Wide-band Mixer for
WCDMA/CDMA2000 in 90nm Digital CMOS Process,
IEEE RFIC Symposium, 2005, pp. 179-182.

IIP3=-9.9dBm
Pout

0
- 20
- 40

IM3

- 60
- 80
- 100

IM2
- 55

- 35

- 15

25

45

Input Power (dBm)

Figure 6. P1dB, IIP2 and IIP3 plot.

352

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