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Module 2 : Intel 8051 Microcontroller


Lecture 13 : 8051 Instruction Set

8051 Instructions
8051 has about 111 instructions. These can be grouped into the following categories
1. Arithmetic Instructions
2. Logical Instructions
3. Data Transfer instructions
4. Boolean Variable Instructions
5. Program Branching Instructions
The following nomenclatures for register, data, address and variables are used while write instructions.
A: Accumulator
B: B register
C: Carry bit
Rn: Register R0 R7 of the currently selected register bank
Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00 7FH) or it could be in
the special function register (80 FFH).
@Ri: 8bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode.
#data8: Immediate 8-bit data available in the instruction.
#data16: Immediate 16-bit data available in the instruction.
Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP & ACALL. Jump range is 2
kbyte (one page).
Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one byte) used for short jump (SJMP) and all conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
Arithmetic Instructions
Mnemonics
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
DA A
DIV AB

DEC A
DEC Rn
DEC direct
DEC @Ri
INC A
INC Rn
INC direct
INC @Ri

Description
A
A + Rn
A
A + (direct)
A
A + @Ri
A
A + data
A
A + Rn + C
A
A + (direct) + C
A
A + @Ri + C
A
A + data + C
Decimal adjust accumulator
Divide A by B
A
quotient
B
remainder
A
A -1
Rn
Rn - 1
(direct)
(direct) - 1
@Ri
@Ri - 1
A
A+1
Rn
Rn + 1
(direct)
(direct) + 1
@Ri
@Ri +1

Bytes
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Instruction Cycles
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INC DPTR
MUL AB

SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data

DPTR
DPTR +1
Multiply A by B
A
low byte (A*B)
B
high byte (A* B)
A
A - Rn - C
A
A (direct) - C
A
A - @Ri - C
A
A - data - C

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Logical Instructions
Mnemonics
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
CLR A
CPL A
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
RL A
RLC A
RR A
RRC A
SWAP A
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data

Description
A AND Rn
A
A AND (direct)
A
A AND @Ri
A
A AND data
(direct)
(direct) AND A
(direct)
(direct) AND data
A
00H
A
A
A
A OR Rn
A
A OR (direct)
A
A OR @Ri
A
A OR data
(direct)
(direct) OR A
(direct)
(direct) OR data
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
Rotate accumulator right through carry
Swap nibbles within Acumulator
A
A EXOR Rn
A
A EXOR (direct)
A
A EXOR @Ri
A
A EXOR data
(direct)
(direct) EXOR A
(direct)
(direct) EXOR data
A

Bytes
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Instruction Cycles
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Data Transfer Instructions


Mnemonics
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct1, direct2
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVC A, @Ri
MOVX A, @DPTR
MOVX @Ri, A

Description
A
Rn
A
(direct)
A
@Ri
A
data
Rn
A
Rn
(direct)
Rn
data
(direct)
A
(direct)
Rn
(direct1)
(direct2)
(direct)
@Ri
(direct)
#data
@Ri
A
@Ri
(direct)
@Ri
data
DPTR
data16
A
Code byte pointed by A + DPTR
A
Code byte pointed by A + PC
A
Code byte pointed by Ri 8-bit address)
A
External data pointed by DPTR
@Ri
A (External data 8bit address)

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MOVX @DPTR, A
PUSH direct
POP direct
XCH Rn
XCH direct
XCH @Ri
XCHD A, @Ri

@DPTR

A(External data 16bit address)


(SP)
(direct)
(direct)
(SP)
Exchange A with Rn
Exchange A with direct byte
Exchange A with indirect RAM
Exchange least significant nibble of A with that of
indirect RAM

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Boolean Variable Instructions


Mnemonics

Description

Instruction Cycles

CLR C

C-bit

CLR bit

bit

SET C

SET bit

bit

CPL C
CPL bit

Bytes

C
bit

ANL C, /bit

C.

ANL C, bit

C. bit

ORL C, /bit

C+

ORL C, bit

C + bit

MOV C, bit

bit

MOV bit, C

bit

Program Branching Instructions


Mnemonics
ACALL addr11
AJMP addr11
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
JMP @A+DPTR
JZ rel
JNZ rel
LCALL addr16
LJMP addr 16
NOP
RET
RETI
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
NOP

Description
(SP) ; addr 11
PC
Addr11
PC
Compare with A, jump (PC + rel) if not equal
Compare with A, jump (PC + rel) if not equal
Compare with Rn, jump (PC + rel) if not equal
Compare with @Ri A, jump (PC + rel) if not equal
Decrement Rn, jump if not zero
Decrement (direct), jump if not zero
Jump (PC + rel) if C bit = 1
Jump (PC + rel) if C bit = 0
Jump (PC + rel) if bit = 1
Jump (PC + rel) if bit = 0
Jump (PC + rel) if bit = 1
A+DPTR
PC
If A=0, jump to PC + rel
If A 0 , jump to PC + rel
PC + 3
(SP), addr16
PC
Addr16
PC
No operation
(SP)
PC
(SP)
PC, Enable Interrupt
PC + 2 + rel
PC
A+DPTR
PC
If A = 0. jump PC+ rel
If A 0, jump PC + rel
No operation
PC + 2

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