CMOS SEQUENTIAL CIRCUITS

Sequential circuits or regenerative are circuits in which the output is determined by

the current inputs as well as the previously applied input variables. Figure shows a sequential
circuit consisting of a combinational circuit and a memory block in the feedback loop. In
most cases, the regenerative behaviour of sequential circuits is due to either a direct or
indirect feedback connection between the output and the input.
The critical components of sequential systems are the basic regenerative circuits,
which can be classified into three main groups: bistable circuits, monostable circuits, and
astable circuits.Bistable circuits have, as their name implies, two stable states or operation
modes,each of which can be attained under certain input and output conditions. Among these
three main groups of regenerative circuit types, the bistable circuits are by far the most
widely used 'and the most important class. All basic latch and flip-flop circuits, registers, and
memory elements used in digital systems fall into this category.
Principle of bistable circuits

CIRCUIT SCHEMATIC

TRANSISTOR LEVEL IMPLEMENTATION

Voltage transfer chara of bistatble elemnet

A bistable circuit a circuit having two stable states that represent 0 and 1. Another
common name for a bistable circuit is flip-flop. The cross-coupling of two inverters results in
a bistable circuit, that is, a circuit with two stable states, each corresponding to a logic state.
The circuit serves as a memory, storing either a 1 or a 0.
SR FLIPFLOP
NOR BASED SR FLIP FLOP
The circuit consists of two CMOS NOR2 gates. One of the input terminals of
eachNOR gate is used to cross-couple to the output of the other NOR gate,(hence, the circuit
can perform a simple memory function of holding its state.,)while the second input enables
triggering of the circuit. S and R external triggering inputs are for allowing a change of state
from one stable operating mode to the other.
Gate level schematic and block diagram

Truth table

Circuit operation
The SR flipflop has two complementary outputs, Q and Q. By definition, the flipflop is
said to be in its set state when Q is equal to logic " 1 " and Q is equal to logic "0."
Conversely, the latch is in its reset state when the output Q is equal to logic "0" and Q is equal
to "1."
The operation of the CMOS SR flip circuit shown in Fig. can be examined in more
detail by considering the operating modes of the four nMOS transistors, MI, M2, M3, and
M4. If the set input (S) is equal to logic high(VOH) and the reset input (R) is equal to logic
low(VOL), both of the parallel-connected transistors Ml and M2 will be on. Consequently, the
voltage on node Q will assume a logic-low level of V OL = 0. At the same time, both M3 and
M4 are turned off, which results in a logic-high voltage (V OH) at node Q. If the reset input (R)
is equal to VOH and the set input (S) is equal to V OL, the situation will be reversed (Ml and
M2 turned off Qis at logic high and M3 and M4 turned on-Q at logic low). When both of the
input voltages are equal to logic low ,VOL o there are two possibilities. Depending on the
previous state of the SR latch, either M2 or M3 will be on, while both of the trigger
transistors MI and M4 are off. This will generate a logic-low level of V OL = O at one of the
output nodes, while the complementary output node is at VOH.
Hence to summarize
If both input signals ( S and R)are equal to logic "0," the SR flipflop will operate
exactly like the simple cross-coupled bistable element, it will preserve (hold) either
one of its two stable operating points (states) as determined by the previous inputs.
If the set input (S) is equal to logic "1" and the reset input is equal to logic "0," then
the output node Q will be forced to logic " 1 " while the output node Q is forced to
logic "0." This means that the SR flipflop will be set, regardless of its previous state.

 If S is equal to "0" and R is equal to " ," then the output node Q will be forced to "0"
while Q is forced to "1." Thus, with this input combination, the flipflop is reset,
regardless of its previously held state.
If both of the inputs S and R are equal to logic 1" ,both output nodes will be forced to
logic "0," which conflicts with the complementarity of Q and Q. Therefore, this input
combination is not permitted during normal operation and is considered to be a not
allowed condition.
The static operation modes and voltage levels of the NOR-based CMOS SR flipflop circuit
are summarized in the following table.

NAND2 SR Latch or flipflop

The gate-level schematic and the corresponding block diagram representation of the NANDbased SR flipflop circuit are shown in Fig.. The small circles at the S and R input terminals
indicate that the circuit responds to active low input signals. NAND-based SR flipflop circuit
reveals that in order to hold (preserve) a state, both of the external trigger inputs must be
equal to logic " 1." The operating point or the state of the circuit can be changed only by
pulling the set input to logic zero or by pulling the reset input to zero. We can observe that if
S is equal to "0" and R is equal to " 1," the output Q attains a logic " 1 " value and the
complementary output Q becomes logic "0." Thus, in order to setthe NAND SR flipflop, a
logic "0" must be applied to the set (S) input. Similarly, in order to reset the latch, a logic "0"
must be applied to the reset (R) input. The conclusion is that the NAND-based SR flipflop

responds to active low input signals, as opposed to the NOR-based SR latch, which
responds to active high inputs. Note that if both input signals are equal to logic "0," both
output nodes assume a logic-high level, which is not allowed because it violates the
complementarity of the two outputs.

Clocked SR Latch
To facilitate synchronous operation, the circuit response can be controlled simply by adding a
gating clock signal to the circuit, so that the outputs will respond to the input levels only
during the active period of a clock pulse.

The gate-level schematic of a clocked NOR-based SR latch is shown in Fig. It can be seen
that if the clock (CK) is equal to logic "0," the input signals have no influence upon the
circuit response. The outputs of the two AND gates will remain at logic "0," which forces the
SR latch to hold its current state regardless of the S and R input signals. When the clock input
goes to logic " 1," the logic levels applied to the S and R inputs are permitted to reach the SR
latch, and possibly change its state. Note that as in the nonclocked SR latch, the input

combination S = R = "1" is not allowed in the clocked SR latch. With both inputs S and R at
logic " 1," the occurrence of a clock pulse causes both outputs to go momentarily to zero.
When the clock pulse is removed, i.e., when it becomes "0," the state of the latch is
indeterminate. It can eventually settle into either state, depending on slight delay differences
between the output signals. The circuit is strictly level-sensitive during active clock
phases, i.e., any changes occurring. in the S and R input voltages when the CK level is
equal to " 1 " will be reflected onto the circuit outputs. Consequently, even a narrow spike
or glitch occurring during an active clock phase can set or reset the latch, if the loop delay is
shorter than the pulse width.

Figure shows a CMOS implementation of the clocked NOR-based SR latch circuit, using two
simple AOI gates. Notice that the AOI-based implementation of the circuit results in a very
small transistor count.

The NAND-based SR latch can also be implemented with gating clock input, as shown in
Fig. It must be noted, however, that both input signals S and R as well as the clock signal CK
are active low in this case. This means that changes in the input signal levels will be ignored
when the clock is equal to logic " 1," and that inputs will influence the outputs only when the
clock is active, i.e., CK = "0."
For the circuit implementation of this clocked NAND-based SR latch, we can use a simple
OAI structure, which is essentially analogous to the AOI-based realization of the clocked
NOR SR latch circuit.
NAND BASED SR LATCH WITH ACTIVE HIGH INPUTS

A different implementation of the clocked NAND-based SR latch is shown in Fig. . Here,

both input signals and the CK signal are active high, i.e., the latch output Q will be set when
CK = " 1," S = " 1," and R = "O." Similarly, the latch will be reset when CK = "1," = "O,"
and R = "1." The latch preserves its state as long as the clock signal is inactive, i.e., when CK
= "O". The drawback of this implementation is that the transistor count is higher than
the active low version.
Clocked JK Latch
The JK latch is commonly called a JK flip-flop. SR latch circuits suffer from the common
problem of having a not-allowed input combination, i.e., their state becomes indeterminate
when both inputs S and R are activated at the same time. This problem can be overcome by
adding two feedback lines from the outputs to the inputs, as shown in Fig.. The resulting
circuit is called a JK latch.

Figure shows an all-NAND implementation of the JK latch with active high inputs, and the
corresponding block diagram representation.
The J and K inputs in this circuit correspond to the set and reset inputs of the basic SR latch.
When the clock is active, the latch can be set with the input combination (J = '1," K = "0"),
and it can be reset with the input combination (J = "0," K = "1"). If both inputs are equal to

logic "0," the latch preserves its current state. If, on the other hand, both inputs are equal to "
1 " during the active clock phase, the latch simply switches its state due to feedback. In other
words, the JK latch does not have a not-allowed input combination. As in the other clocked
latch circuits, the JK latch will hold its current state when the clock is inactive (CK = "0").
The operation of the clocked JK latch is summarize-d in the truth Table.

NOR BASED IMPLEMENTATION OF JK LATCH

Figure shows an alternative, NOR-based implementation of the clocked JK latch, and CMOS
realization of this circuit. Note that the AOI-based circuit structure results in a relatively low
transistor count, and consequently, a more compact circuit compared to the all-NAND
realization
While there is no not-allowed input combination for the JK latch, there is still a potential
problem. If both inputs are equal to logic " 1 " during the active phase of the clock pulse, the
output of the circuit will oscillate (toggle) continuously until either the clock becomes
inactive (goes to zero), or one of the input signals goes to zero. To prevent this undesirable
timing problem, the clock pulse width must be made smaller than the input-to-output
propagation delay .
Master-Slave Flip-Flop
Mater slave flipflop consists of two latch stages in a cascaded configuration. Key operation
principle is that the two cascaded stages are activated with opposite clock phases. This
configuration is called the master-slave flip-flop

The input latch in Fig. , called the "master," is activated when the clock pulse is high. During
this phase, the inputs J and K allow data to be entered into the flip-flop, and the first-stage
outputs are set according to the primary inputs. When the clock pulse goes to zero, the master
latch becomes inactive and the second-stage latch, called the "slave," becomes active. The
output levels of the flip-flop circuit are determined during this second phase, based on the
master-stage outputs set in the previous phase.

Since the master and the slave stages are effectively decoupled from each other with the
opposite clocking scheme, the circuit is never transparent, i.e., a change occurring in the
primary inputs is never reflected directly to the outputs. This very important property clearly
separates the master-slave flip-flop from the latch circuits
Because the master and the slave stages are decoupled from each other, the circuit allows for
toggling when J = K = "1," but it eliminates the possibility of uncontrolled oscillations since
only one stage is active at any given time.

A NOR-based alternative realization for the master-slave flip-flop circuit is shown in Fig.
The master-slave flip-flop circuit examined here has the potential problem of "one's
catching." When the clock pulse is high, a narrow spike or glitch in one of the inputs, for
instance a glitch in the J line (or K line), may set (or reset) the master latch and thus cause an
unwanted state transition, which will then be propagated into the slave stage during the
following phase. This problem can be eliminated to a large extent by building an edgetriggered master-slave flip-flop.
D LATCH

The gate-level representation of the D-latch is simply obtained by modifying the clocked
NOR-based SR latch circuit. Here, the circuit has a single input D, which is directly
connected to the S input of the latch. The input variable D is also inverted and connected to
the R input of the latch. It can be seen from the gate-level schematic that the output Q
assumes the value of the input D when the clock is active, i.e., for CK = "1." When the clock
signal goes to zero, the output will simply preserve its state. Thus, the CK input acts as an
enable signal which allows data to be accepted into the D-latch.
The D-latch finds many applications in digital circuit design, primarily for temporary
storage of data or as a delay element.
Consider the circuit diagram given in Fig., which shows a basic two-inverter loop and two
CMOS transmission gate (TG) switches.

The TG at the input is activated by the CK signal, whereas the TG in the inverter loop is
activated by the inverse of the CK signal, CK. Thus, the input signal is accepted (latched) into
the circuit when the clock is high, and this information is preserved as the state of the inverter
loop when the clock is low.
The operation of the CMOS D-latch circuit can be better visualized by replacing the CMOS
transmission gates with simple switches, as shown in Fig.

A timing diagram shows the time intervals during which the input and the output signals
should be valid (unshaded).

The valid D input must be stable for a short time before (setup time, tsetup) and after (hold
time, thold) the negative clock transition, during which the input switch opens and the loop
switch closes. Once the inverter loop is completed by closing the loop switch, the output will
preserve its valid level. In the D-latch design, the requirements for setup time and hold time
should be met carefully. Any violation of such specifications can cause metastability
problems.
Figure shows a different version of the CMOS D-latch.

The circuit contains two tristate inverters, driven by the clock signal and its inverse. The basic
operation principle of the circuit is the same as that shown in first figure. The first tri-state
inverter acts as the input switch, accepting the input signal when the clock is high. At this
time, the second tristate inverter is at its high-impedance state, and the output Q is following
the input signal. When the clock goes low, the input buffer becomes inactive, and the second
tristate inverter completes the two-inverter loop, which preserves its state until the next clock
pulse.
MASTER SLAVE NE GATIVE EDGE TRIGGERED D FLIP FLOP

Consider the two-stage master-slave flip-flop circuit shown in Fig.,which is constructed by

simply cascading two, D-latch circuits. The first stage (master) isidriven by the clock signal,
while the second stage (slave) is driven by the inverted clock signal. Thus, the master stage is
positive level-sensitive, while the slave stage is negative level-sensitive.

When the clock is, high, the master stage follows the D input while the slave stage holds the
previous value. When the clock changes from logic "1" to logic "," the master latch ceases to
sample the input and stores the D value at the time of the clock transition. At the same time,
the slave latch becomes transparent, passing the stored master value Q m to the output of the
slave stage, Q.. The input cannot affect the output because the master stage is disconnected
from the D input. When the clock changes again from logic 0" to 1," the slave latch locks in
the master latch output and the master stage starts sampling the input again. Thus, this circuit
is a negative edge-triggered D flip-flop by virtue of the fact that it samples the input at the
falling edge of the clock pulse.
CMOS LOGIC SYSTEMS

Psueodo nMOS
Dynamic CMOS
CMOS domino
Clocked CMOS
n-p CMOS
Zipper CMOS

Pseudo nMOS

PseudonMOS NAND3 structure

PseudonMOS logic structure consists of nMOS pull down n/w and a PMOS pullup transistor
with its gate grounded.Depletion load pull upt transistor of standard nMOS logic ckts
replaced with a pMOS transistor with its gate connected to ground so that it is always ON
forms a pseudo nMOS logic structure.This a ratioed circuit since Gain ratio of n-driver

transistors to p-transistor load (beta driver /beta load ), is important to ensure adequate noise
margin.
Disadvantages of pseudo-nMOS gate compared to a complementary CMOS gate
Nonzero static power dissipation, since the always-on pmos load device conducts a
steady-state current when the output voltage is lower than VDD. Also,
Value of VOL and the noise margins are now determined by the ratio of the pmos load
transconductance(p) to the pull-down or driver transconductance(n)
Advantage
The clear advantage of pseudo-NMOS is the reduced number of transistors
(N+1 )versus 2N for complementary CMOS).
[Reason for low value of VOL ,and reduced noise margin
(Noise margin,NML=VIL-VOL,VOL=0 for FULL CMOS but for pseudo nMOs .WHEN Vout is
low -VOL, ie Vin =VDD,nmos pulldown n/w is ON providing a path from output node to
ground,where as PMOS pull up is always ON connecting VDD to o/p node.Hence VOL will
not be zero.(this is not the case with CMOS since if pulldown n/w is ON pull will be
off ).hence noise margin also will be low compared to complementary CMOS.
Inorder to have a low value for VOL ratioing is necessary.
The value of VOL is obtained by equating the currents through the driver(NMOS) and load
(PMOS)devices for Vin = VDD. At this operation point, it is reasonable to assume that the
NMOS device resides in linear mode (since the output should ideally be close to 0V), while
the PMOS load is saturated.
Drain current in saturation

IdP= p (VGSP-VTP) VDSAT-V2DSAT

2

Drain current in linear region

IdN= n(VGSN-VTN)Vout-V2out
2

Vout=VOL
VG=VDD
VGSP=0 - VDD= - VDD
VGSN= VDD
IdN = - IdP
n(VDD-VTN)VOL-V2OL= - p (-VDD-VTP) VDSAT-V2DSAT
2
2
VTN= |VTP|, NEGLECTING HIHER POWERS
VOL= - p (-VDD-VTP) VDSAT
n(VDD-VTN)

= p VDSAT
n
VOL = p Cox(W/L)P VDSAT
n Cox(W/L)n
Hence to get low value of VOL PMOS device should be sized much smaller than that
of NMOS device.]

Dynamic CMOS

Actual logic is implemented in faster nMOS logic and a p -transistor is used for nontime critical precharging of output line so that output capacitance is charged to VDD. The
circuit operation is based on first precharging the output node capacitance and subsequently,
evaluating the output level according to the applied inputs.
Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor
Mp.During that time, the evaluate NMOS transistor Me is off, so that the pull-down path is
disabled.
Evaluation

For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned
on. The output is conditionally discharged based on the input values and the pull-down
topology. If the inputs are such that the PDN(Pull Down Network) conducts, then a low
resistance path exists between Out and GND and the output is discharged to GND. If the
PDN is turned off, the precharged value remains stored on the output capacitance CL

Advantage
Dynamic CMOS circuit technique allows us to significantly reduce the number of
transistors used to implement any logic function.
Limitations
Charge sharing may be a problem unless the inputs are constrained not to change
during the period of clock
Single phase dynamic logic structures cannot be cascaded since owing to circuit
delays incorrect inputs to next stage may be present when evaluation begins and
wrong output results.
One remedy is to employ a four phase clock in which actual signals are
derived clocks 12 23 34 41 as shown in fig b. The basic circuit in fig a is
modified by the inclusion of a transmission gate as in fig c the function of which is to
samle the output during evaluate period and to hold the output state while the next
stage logic evaluates. For this strategy to work next stage must operate with
overlapping but later clock signals. Since there are four different derived clock signals
there are four different clocking configurations. Inorder to avoid erroneous evaluation
gate must be connected in allowable next sequences set out in table below

Clocked CMOS(C2MOS )LOGIC

The logic is implemented in both n- and p transistors in form of a pull up p block and
a complementary n block pull down structure .However logic in this case is evaluated only
during on period of clock.A clocked inverter(tristate inverter) forms part of this family.
Limitation
Owing to extra transistors in series slow rise times and fall times can be expected.
CMOS Domino logic

An extension to dynamic CMOs LOGIC ,a dynamic CMOS logi stage followed by a

static inverter constitute CMOS domino logic.This static inverting buffer allows for
cascading of logic structures using only a single phase clock without erroneous outputs.
Features
Such logic structures can have smaller area than conventional CMOS logic
Requires less no:of transistors to implement logic function compared to conventional
CMOS
Parasitic capacitances are smaller so that higher operating speeds are possible.
Operation is free of glitches since each gate can make only one 1 to 0 transition
Only non inverting structures are possible because of presence of inverting buffer
Limitations
Charge distribution is a problem in domino CMOS
Eg AB+GH+(E+F)(C+D)

n-p CMOS(NORA)LOGIC

This is a variation of basic dynamic logic arrangement in which actual logic blocks are
alternatively n and p in a cascaded structure.The pre charge and evaluate transistors are fed
from clock and alternately and functions of top and bottom transistors are alternate
between precharge and evaluate. The precharge-and-evaluate timing of nMOS logic stages is
accomplished by the clock signal , whereas the pMOS logic stages are controlled by the
inverted clock signal, . The operation of the NORA CMOS circuit is as follows: When the
clock signal is low, the output nodes of nMOS logic blocks are precharged to VDD through
the pMOS precharge transistors, whereas the output nodes of pMOS logic blocks are pre-

discharged to 0 V through the nMOS discharge transistors, driven by

.When the clock

signal makes a low-to-high transition (note that the inverted clock signal makes a high-to-low
transition simultaneously), all cascaded nMOS and pMOS logic stages evaluate one after
the other.
ADVANTAGE of NORA CMOS logic
Static CMOS inverter is not required at the output of every dynamic logic stage.
Instead, direct coupling of logic blocks is feasible by alternating nMOS and pMOS
logic blocks. NORA logic is also compatible with domino CMOS logic.
The second important advantage of NORA CMOS logic is that it allows pipelined
system architecture.
Limitation
Suffer from charge sharing and leakage.
Zipper CMOS

Zipper CMOS is identical with NORA(np CMOS)with the exception of the clock signals.
The Zipper CMOS clock scheme requires the generation of slightly different clock signals for
the precharge (discharge) transistors and for the pull-down (pull-up) transistors. In particular,
the clock signals which drive the pMOS precharge and nMOS discharge transistors allow
these transistors to remain in weak conduction or near cut-off during the evaluation phase,
thus compensating for the charge leakage and charge-sharing problems.
Scaling
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to
as scaling. It is expected that the operational characteristics of the MOS transistor will change
with the reduction of its dimensions. Also, some physical limitations eventually restrict the
extent of scaling that is practically achievable. There are two basic types of size-reduction
strategies: full scaling (also called constant-field scaling) and constantvoltage scaling. Scaling
of MOS transistors is concerned with systematic reduction of overall dimensions of the
devices as allowed by the available technology, while preserving the geometric ratios found

in the larger devices. The proportional scaling of all devices in a circuit would certainly result
in a reduction of the total silicon area occupied by the circuit, thereby increasing the overall
functional density of the chip. To describe device scaling, we introduce a constant scaling
factor S > 1. All horizontal and vertical dimensions of the large-size transistor are then
divided by this scaling factor to obtain the scaled device. The extent of scaling that is
achievable is obviously determined by the fabrication technology and more specifically, by
the minimum feature size.
Scaling models and scaling factors
Constannt field (E) scaling (full scaling)- This scaling option attempts to preserve
the magnitude of internal electric fields in the MOSFET, while the dimensions are
scaled down by a scaling factor . To achieve this goal, all potentials must be scaled
down proportionally, by the same scaling factor.
Constannt Voltage (V) scaling- In constant-voltage scaling, all dimensions of
MOSFET are reduced by a scaling factor. The power supply voltage and the terminal
voltages, on the other hand, remain unchanged.
Combined voltage and field scaling.

L =Length of channel
W =Width of chananel
D =Thickness of channel
X =junction depth

To accomodtae these three models thwo scaling factors are used.1/ AND 1/. 1/ is chosen
a scaling factor for supply voltage VDD and gate oxide thickness D. 1/- for all other linear
dimensions.For the constant field moldel = and for constant voltage moldel =1 is applied.
Effects of scaling-Scaling factors for device scaling
(OBTAIN EXPRESSION (DERIVE) FOR EACH DEVICE PARAMETER GIVEN IN
TEXT PUCKNELL-just summary is shown here.U have to derive each)

To summarize, constant field scaling reduces both the drain current and the drain-to-source
voltage by a factor of ; hence, the power dissipation of the transistor will be reduced by the
factor 2.This significant reduction of the power dissipation is one of the most attractive
features of full scaling. constant-voltage scaling may be preferred over full (constant-field)
scaling in many practical cases because of the external voltage-level constraints. It must
be recognized, however, that constant-voltage scaling increases the drain current density and
the power density .This large increase in current and power densities may eventually cause
serious reliability problems for the scaled transistor, such as electromigration, hot-carrier
degradation, oxide breakdown, and electrical over-stress.
Small geometry effects-Short-Channel Effects

A MOS transistor is called a short-channel device if its channel length is on the same order of
magnitude as the depletion region thicknesses of the source and drainjunctions. Alternatively,
a MOSFET can be defined as a short-channel device if the effective channel length L effis
approximately equal to the source and drain junction depth xj.
Velocity satutation
The lateral electric field EY along the channel increases, as the effective channel length is
decreased. While the electron drift velocity Vd in the channel is proportional to the electric
field for lower field values, this drift velocity tends to saturate at high channel electric fields.
Carrier velocity saturation actually reduces the saturation-mode current.
Mobility degaradation
In short-channel MOS transistors, the carrier velocity in the channel is also a function of the
normal (vertical) electric-field component Ex. Since the vertical field influences the
scattering of carriers (collisions suffered by the carriers) in the surface region, the surface
mobility is reduced.This is mobility degradation.
Modification of threshold votage
Subthreshold conduction in small-geometry MOS transistors- The channel current that
flows under these conditions (VGS < Vtn) is called the subthreshold current.
Punch-through
The channel length is on the same order of magnitude as source and drain depletion region
thicknesses. For large drain-bias voltages, the depletion region surrounding the drain can
extend farther toward the source, and the two depletion regions can eventually merge. This
condition is termed punch-through the current rises sharply once punch-through occurs.
Oxide breakdown
Another limitation on the scaling of thickness of oxide tox is the possibility of oxide
breakdown. If the oxide electric field perpendicular to the surface is larger than a certain
breakdown field, the silicon-dioxide layer may sustain permanent damage during operation,
leading to device failure.
Hot carrier injection
This decrease in critical device dimensions to submicron ranges, accompanied by increasing
substrate doping densities, results in a significant increase of the horizontal and vertical
electric fields in the channel region. Electrons and holes gaining high kinetic energies in the
electric field (hot carriers) may, however, be injected into the gate oxide, and cause

permanent changes in the oxide interface charge distribution, degrading the current-voltage
characteristics of the MOSFET
BiCMOS
Combines Bipolar and CMOS transistors in a single integrated circuit. By retaining benefits of bipolar
and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance. The
superiority of the BiCMOS gate lies in the high current drive capability of the bipolar output
transistors, the zero static power dissipation, and the high input impedance provided by the MOSFET
configuration.
(STUDY fabrication of BICMOS STRUCTURE FROM TEXT -BOTKAR)
COMPARISON B/W CMOS AND BIPOLAR TECHNOLOGIES
CMOS
Low static power dissipation
High i/p impedance
High noise margin
High packing density
High delay sensitivity to load
Low output drive current
Low gm(transconductance)
Bidirectional capability
Nearly ideal switching device
Advantages of BiCMOS

BIPOLAR
High static power dissipation
Low i/p impedance
Low noise margin(low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
Large gm(transconductance)
unidirectional
Non ideal switching device

BiCMOS devices offer high load current sinking and sourcing is required. The high current
gain of the NPN transistor greatly improves the output drive capability of a conventional
CMOS device.
Improved speed over purely-CMOS technology
Lower power dissipation than purely-bipolar technology (simplifying packaging and board
requirements)
Latchup immunity
Flexible I/Os (i.e., TTL, CMOS or ECL compatible) BiCMOS technology is well suited for
I/O intensive applications. ECL, TTL and CMOS input and output levels can easily be
generated
DISADVANTAGE
Costlier due to added Processing Complexity.Additional masking steps than in CMOS to
fabricate bipolar structure along with CMOS
COMPARISON B/W CMOS BIPOLAR AND BiCMOS TECHNOLOGIES
CMOS
Low static power dissipation

BIPOLAR
High static power dissipation

Low speed(Slow switching)

Low o/p current drive
High i/p impedance
High noise margin(high o/p

High speed
High o/p current drive
Low i/p impedance
Low noise margin

BiCMOS
Low static power dissipation
than Bipolar
Faster than CMOS
High o/p current drive
High i/p impedance
High noise margin compared to

voltage swing)
Fabrication process simpler
compared to BiCMOS
BiCMOS Logic gates

Simpler fabrication

bipolar
Fabrication process is complex

Designed with MOS circuits to implement the logic and bipolar transistors to drive output loads.
Charactreristics of BiCMOS logic gates(write for inverter,nand and nor)

The o/p logic levels will be god nd will be close to rail voltages
High i/p impedance
Low o/p impedance
High current drive capability,occupies relatives smaller area
High noise margin

BiCMOS invereter

BiCMOS inverter circuit consists of two bipolartransistors T1 and T2 with one nMOS T3 and one
pMOS transistor T4,both being enhancemnet mode devices.
OPERATION OF CIRCUIT
With Vin=0 volts(GND),T3 is off so that T1 will be non conductiong.but T4 is on and
supplies current to base of T2 which will conduct and act as current source to charge load C L
towards +5 VOLTS(VDD). The O/P of inverter rise +5 volts less base to emitter voltage
VBEof T2.
With Vin=+5 volts(VDD),T4 is off so that T2 will be non conductiong.but T3 is on and
supplies current to base of T1 which will conduct and act as current sink to disccharge load
CL towards 0 VOLTS(GND). The O/P of inverter will fall to 0 volts plus saturation voltage
VCEsat from collector to emitter of T1.
T1 AND T2 will present low impedances when turned on into saturation and load C L will be
charged or discharged rapidly.

 The o/p logic levels will be god nd will be close to rail voltages
Inverter has High i/p impedance
Inverter has Low o/p impedance
Inverter has High current drive capability,occupies relatives smaller area
Inverter has High noise margin
LIMITATIONS OF BASIC INVERETER CONFIGURATION
Owing to presence of DC path from VDD to GND through T3 and T1 ,this is not a ood
arrangement to implement since there will be a significant static current flow whenever
Vin=logic1.
Thre is no diharge path for current from base of either bipolar transistor when it is being
turned off.This will slow down action of circuit.
An improved BiCMOS inverter WITH NO STATIC CURRENT FLOW

DC path through T3 and T1 is eliminated but o/p voltage swing is now reduced since output cannot
fall below base to emitter voltage of T1.(this o/p volt is in effect base voltage of T1 in this
arrangement.T1 wil turn off if o/p volt fall below VBE OF T1.)

Consider the simple BiCMOS inverter circuit shown in figure which consists of two MOS transistors
and two' npn-type bipolar transistors which drive a large output capacitance Cload. The operation
concept of this circuit can be very briefly summarized as follows.
The complementary pMOS and nMOS transistors MP and MN supply base currents to the bipolar
transistors and thus act as "trigger" devices for the bipolar output stage. The bipolar transistor Q 1 can
effectively pull up the output voltage in the presence of a large output capacitance, whereas Q2 pulls
down the output voltage, similar to the well-known totem pole configuration. Depending on the logic
level of the input voltage, either MN or MP can be turned on in steady state, therefore assuring a fully
complementary pushpull operation mode for the two bipolar transistors. In this very simplistic
configuration, two resistors are used to remove the base charge of the bipolar transistors when they
are in cut-off mode. In this circuit resistors provide better improved o/p swing of voltage .
To reduce the turn-off times of the bipolar transistors during switching, two minimum-size nMOS
transistors (MB 1 and MB2) are usually added to provide the necessary base discharge path, instead of
the two resistors(resistors are space consuming). The resulting six-transistor inverter circuit, shown in
Fig.,below is the most widely used conventional BiCMOS inverter configuration.

Conventional BiCMOS inverter.

BiCMOS NOR2

Figure shows the circuit diagram of a BiCMOS NOR2 gate. Here, the base of the bipolar pull-up
transistor Q1 is being driven by two series-connected Pmos transistors. Therefore, the pull-up device
can be turned on only if both of the inputs are logic-low. The base of the bipolar pull-down transistor
Q2 is driven by two parallel-connected nMOS transistors. Therefore, the pull-down device can be
turned on if either one or both of the inputs are logic-high. Also, the base charge of the pull-up device
is removed by two minimum-size nMOS transistors connected in parallel between the base node and
the ground. Notice that only one nMOS transistor, MB2, is being used for removing the base charge
of Q2, when both inputs are logic-low.

BiCMOS NAND2

Figure shows the circuit diagram of a BiCMOS NAND2 gate. In this case, the base of the bipolar
pull-up transistor Q I is being driven by two parallel-connected Pmos transistors. Hence, the pull-up
device is turned on when either one or both of the inputs are logic-low. The bipolar pull-down
transistor Q2, on the other hand, is driven by two series-connected nMOS transistors between the
output node and the base. Therefore, the pull-down device can be turned on only if both of the inputs
are logic-high. For the removal of the base charges of Q1 during turn-off, two series-connected nMOS
transistors are used, whereas only one nMOS transistor is utilized for removing the base charge of Q2.