Open

Column
Liming Xiu

Some Open Issues Associated with the New Type of Component:

Digital-To-Frequency Converter

n the article The Concept of Time-Average-Frequency

and Mathematical Analysis of Flying-Adder Frequency
Synthesis Architecture, a new type of component
Digital-to-Frequency Converter (DFC) is introduced [1].
The DFC is built upon two corner stones: a circuit technique called Flying-Adder frequency synthesis architecture and a rigorously formed concept of Time-AverageFrequency (please refer to Figure 2 of [1]). The first corner stone (Flying-Adder architecture) is the hardware,
which is the implementation circuitry [2][8]. It is a
mature technique with almost ten years history of commercial usage [9]. The second corner stone, Time-Average-Frequency concept, is only formally introduced
recently [1]. Using the Time-Average-Frequency concept,
the theoretical foundation for Digital-to-Frequency Converter is established in [1].
There are two important determinants behind the creation of this new component of Digital-to-Frequency Converter: a) long period of time of studying and designing
with existing PLL techniques, such as integer-N PLL
[10][13] and fractional-N PLL [14][17]. b) the new challenges raised by the various emerging applications. Especially, the new requirements presented by these new
applications are the true driving force behind this innovation, as illustrated by some of the examples in [9].
Although the DFC and the time-average-frequency have
already been used in many commercial products, there
are still several associated mathematical problems which
remain unsolved. These problems are important. If
solved, it will have profound impact on future electronic
system design. These problems are difficult. Their resolutions are beyond the authors capability. Therefore, using
this open column, the author is actively seeking help from
capable researchers on these open problems.
In this article, the circuit-related content has been
reduced to a minimum. The main focus lies in the mathematical understanding. Anyone who has a background in
electrical engineering shall be able to understand the
problems and make a contribution if interested.

Digital Object Identifier 10.1109/MCAS.2008.928422

90

The Background
This open column paper is closely tied to the reference [1], which appears in the same issue of CAS Magazine as this one. The goal of this paper is to provide
further detailed description on the issues raised in
that accompanying paper. As described in Section II.E
of [1], the Flying-Adder frequency synthesizers operation depends heavily on the fractional number used
in that system. When a fractional number is used in
the frequency control word of a Flying-Adder synthesizer, the synthesizers output is in the fashion of
time-average-frequency. In other words, in the output
clock waveform, there is a prolonged cycle every
once in a while. These prolonged cycles are caused by
the fractional carry-in overflows. Table 1 of [1] lists
the resulting patterns from some commonly used fractions. For convenience, this table is presented in here
(Table 1) as well. The left column is the fraction number, while the right column is the corresponding pattern of the cycles. Letter A represents the normal

Table 1.
The combination patterns for some fractions.
Fraction r
0.1

Combination Pattern
AAAAAAAAAB

0.2

AAAAB

0.3

AABAABAAAB

0.4

ABAAB

0.5

AB

0.6

ABABB

0.7

ABBABBABBB

0.8

ABBBB

0.9

ABBBBBBBBB

0.25

AAAB

0.75

ABBB

0.33333333
0.66666667

AAB
ABB

0.125

AAAAAAAB

0.875

ABBBBBBB

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cycle, letter B is the prolonged

cycles caused by the accumulaNormal Cycle Longer Cycle Due to Fractional Carry-In
tion of the fraction. The pattern
repeats forever.
In the simplest case of fraction r taking the form of
T A TA
TA TA TB TA TA
TA TA TB
r = 1/(N + 1), there is one proN
+1
Cycles
longed cycle and N normal
Tm =2 / m
cycles for every N + 1 cycles.
And the clock waveform repeats
Figure 1. The clock waveform when r = 1/(N + 1).
itself for every such N + 1
cycles. This phenomenon is
shown in Figure 1. In the figure,
T A is the period of a normal
S (t )
cycle; T B is the period of a prolonged cycle. As a group, these
N + 1 cycles repeat themselves
One Cycle
at period of Tm .
2
N Cycles of 1
For easier mathematical
t
0
tb
2L
treatment without losing the
Tm
spirit of main focus, a sinusoidal
wave will be used for analysis.
Figure 2. Sinusoidal wave is used for mathematical processing.
Figure 2 shows the 1st harmonic,
S(t), of the clock waveform of
Figure 1.
To further assist the mathematical analysis, signal cycles. r is used to represent the frequency, or possibility,
S(t) can be decomposed into S 1 (t) and S 2 (t) by superim- that type B occurs.
When r takes its simplest form of r = 1/(N + 1),
position, as depicted in Figure 3. This decomposition
could be helpful when Fourier analysis is carried out on there are N type-A cycles T A and one type-B cycle T B
for every N + 1 cycles. This simplest case has been
these signals.
graphically illustrated by Figures 1, 2 and 3. From the
figures, it is understandable that the waveform is a periWhere Is the Most Energy?
A clock signal is used to drive the electronic system. Its odic signal with a period of Tm . Accordingly, the fundaenergy distribution has great impact on the quality of the mental frequency of its spectrum should be
end system. Ideally, for a clock pulse (square wave) of m = 2/Tm . By applying Fourier analysis on the sinufrequency f, all its cycles have the length-in-time of soidal signal of Figure 2 (or Figure 3), we can obtain the
T = 1/f. Consequently, its energy is concentrated at f and Fourier series coefficients in analytic form (please refer
its harmonics, as illustrated in Figure 4. For a clock pulse to Section III.D of [1]).
Using the resulting analytic form, for any given 1 , 2
of close to 50% duty cycle, the magnitudes of the evenand r, we can numerically and graphically prove that
term harmonics are reduced.
The clock waveform of the Flying-Adder synthesizer is the main stem is at (N + 1) m . This also agrees with
different. It is composed of two types of cycles:
T A = I  and T B = ( I + 1) , where I is an integer
and is a constant used to represent a small time duraS1(t )
tion. Obviously, the energy distribution of this type of
clock will be significantly different than for the case of
N Cycles of 1
S2(t )
Figure 4.
One
Cycle
The occurrence of type B cycle T B is dependent on the
2
fractional number r used in the frequency control word,
t
tb
Tm
0
as evident from the examples in Table 1. Therefore, for a
2L
Flying-Adder clock waveform, its energy distribution is
affected by three parameters: T A , T B and r. T A = 2/1
Figure 3. S(t) = S1 (t) + S2 (t) by superimposition.
and T B = 2/2 represent the sizes of the two types of
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91

Magnitude (db)

Frequency

2f

3f

4f

5f

6f

(Hz)

Figure 4. The energy distribution of ideal clock pulse.

intuition. Further, the simulation result by using the Discrete Fourier Transform indicates the same conclusion
(Section IV.C of [1]).
In summary, it seems to us that:
When r = 1/(N + 1), the main stem of signal S(t)s
spectrum lies in the location of (N+1) m .
statement #1
Thus, problem #1 is: can an analytical proof be provided to statement #1?
In general, a fractional number can be classified as
one of the two types: rational and irrational. For the
case of rational, r can be expressed as r = a/b where
both a and b are whole numbers. r = 1/(N + 1) of problem #1 is a special case of rational where a = 1. When
r = a/b is used as the base for accumulation, the carryin overflows occur in such a pattern: for every b operations (accumulation), there are a carry-in overflows. In
other words, for every b cycles, there are a type-B
cycles and b-a type- A cycles. For example, when
r = 3/7, the pattern is AB AB AAB. Figure 5 graphically
shows the scenario.

This is a more generic statement which covers

statement #1. The solution of problem #1, which supposedly is easier to obtain, could potentially provide some
insight to the resolution of this one.
This statement has also been confirmed by the numerical approach we used in Section III of [1] and the simulation result in Section IV.D of [1]. We believe it is true, but
the proof is out of reach at the current time.
Naturally, the next question is:
Problem #3: when r is irrational, how to carry out the
frequency spectrum analysis analytically?
Unlike the cases in problem #1 and #2, the signal S(t)
is not periodic any more when r is irrational. Hence, the
frequency spectrum should be continuous. The simulation result in Section IV.E of [1] shows this characteristic
of continuousness in a certain degree. However, the true
picture of the spectrum can not be accurately obtained
since an irrational number can not be presented by finite
digitals used in a computer. The understanding on this
problem needs to come from analysis.
For all the three aforementioned problems, we only
need to consider the case of r 0.5 since type- A and
type-B cycles are symmetric in mathematical analysis, as
evident from Table 1. Also, if needed, I > 3 can be
assumed when searching the solutions for these problems. Smaller I is never used in a real circuit since it will
increase the implementation difficulty.
The resolutions of these three problems are all related
to one key issue of time-average-frequency: where is the
most clock energy located? This has profound impact on
the usage of the clock signal.

Convert the Spurious Energy to Noise

Fractional numbers are used in DFC to generate frequencies. In a real circuit, the fractions are used as the
When r = a/b, the main stem of signal S(t)s spectrum base for accumulation. From time to time, the acculies in the location of b m
mulation result will overflow. When overflows happen,
statement #2
the corresponding cycles will be prolonged by one .
Problem #2 is: can an analytical proof be provided to Mathematically, the overflows occur regularly. Or,
statement #2?
they are periodic events which result in spurious signals in the frequency spectrum
as illustrated by examples in
Section IV of [1]. For certain
Longer Cycle Due to Fractional Carry-In
Normal Cycle
applications, the spurious signals have negative impact on
system performance, and are
thus undesired. Theoretically, if
b Cycles (Including a Longer Cycles)
the periodic characteristic
Tm =2 / m
could be broken by one way or
another, the spurious signals
Figure 5. The clock waveform when r = a/b.
would be converted into noise.

92

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Figure 6 shows one method

to break the periodic characterTo Break the
Result
istic embedded in the overflow
Periodic Characteristic Result
generation. On the left is the
original scheme used to generCLK
CLK
ate the accumulation result for
circuit operation. FREQ is a real
number (frequency control
FREQ = I + r
UCLK
word). I is its integer part and r
is the fractional part. In this
FREQ = I + r
Modulation
scheme, the accumulation of the
fraction r produces periodic
carry-in overflow to the result.
Figure 6. One method to break the periodic characteristic.
On the right hand side is a proposed method of breaking this
periodic characteristic. A small modulation nate or reduce the spurious signals which are not associsignal/value can be added, at a certain update rate, to ated with the original clock source, such as those caused
the FREQ to change the carry-in generation pattern. by circuit layout mismatch or caused by the interference
The modulation signal generator could be a random signals presented in the circuit board.
number generator, a triangular/sawtooth waveform
generator or a delta-sigma modulator. In Section V of
Spread the Clock Energy
[1], the effects of using a random number generator As CMOS process continuously advances and integration
and a triangular/sawtooth generator have been demon- level reaches higher and higher level, the clock frequency
strated. However, the mathematical understanding has increases and the clock structure becomes more comnot been reached.
plex. Consequently, the task of overcoming the Electromagnetic Interference (EMI) problem in electronic system
Problem #4: can this random number approach be design becomes more challenging. Clock circuitry is the
mathematically modeled and analyzed?
effective source of radiating electromagnetic energy since
clock frequency is usually concentrated on a narrow band
In this problem, there are two adjustable parameters: and its energy is purely centralized. To conquer this probthe magnitude of the random number and the update lem spread spectrum technique can be employed to
rate. Both parameters affect the carry-in generation pat- spread the highly concentrated energy to a boarder band
tern, or the occurrence of type-B cycles.
such that electromagnetic radiation can be reduced, as
depicted in Figure 7.
Problem #5: can a mathematical model be created to
Time-Average-Frequency is ideally suitable for this
describe the triangular/sawtooth waveform modulation?
application since the different types of cycles naturally
spread the clock energy. Using the similar approach preIn this issue, there are three adjustable parameters: sented in Figure 6, carefully designed modulation signals
the magnitude of the waveform (please refer to Figures 27 can be applied on frequency control word FREQ to
and 29 of the accompanying paper), the magnitude of
each step and the update rate. Their impacts on the spectrum need to be understood.
Magnitude

Magnitude

Problem #6: can delta-sigma modulation be used to

alter the spectrum for beneficial effect?
This approach has been tried in our simulation without much success. A mathematical understanding is
desired.
The issue of converting spurious signal into noise is of
great interest to many applications. The scheme
proposed in Figure 6 is a very low-cost, but effective,
implementation. Moreover, it can also be used to elimiTHIRD QUARTER 2008

FCC Limit
Spread Spectrum
Clock Generation

Frequency

Frequency

Figure 7. Spread the clock energy by Spread Spectrum.

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93

manipulate the clock spectrum. This issue has been

discussed intensively in Section VI of the accompanying
paper. The modulation signals used for real application
are either triangular or sawtooth waveforms.
Problem #7: can a mathematical model be created to
describe the triangular/sawtooth waveform modulation
for spreading the energy?
This problem is similar to problem #5. Three parameters are available for adjustment: the magnitude of the
waveform, the magnitude of each step and the update
rate. In problem #5, the goal is to convert the spurious
signals to noise; while in here, the goal is to spread its
center energy to a boarder band. The mathematical challenge still lies in the question of how to relate the type- A
and type-B events to the final clock output spectrum.
Figures 35, 36 and 38 of the accompanying paper
show some real spectrums by using the Flying-Adder
spread spectrum technique. As shown, this technique is
very effective. However, quantitatively, the relationship
between the magnitude of the frequency spread and the
three knobs (the magnitude of the waveform, the magnitude of each step and the update rate) is not well understood. In practice, large amount of trial-and-errors are
carried out. The mathematical understanding can surely
shine some light on this kind of shoot-in-the-dark
work.
Conclusion
In this paper, seven unsolved mathematical problems
have been presented which all relate to a new type of
electronic component: Digital-to-Frequency Converter.
These problems are parts of the theoretical foundation
of this new component. Even though theoretical in
nature, these problems will have profound impact on
future real electronic system design. These problems
present themselves as an excellent example of demonstrating the significance of mathematical analysis in circuit design applications. They show the importance of
fundamental research on directing the real world work.
The author truly hopes that interested and capable
researchers take this challenge and provide help. The
joy of conquering the unknowns could be the reward of
well worth.
References
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analysis of flying-adder frequency synthesis architecture, IEEE Circuit
and System Magazine, Sep., 2008.
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phase synthesis, IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 835846,
June 2000.
[3] L. Xiu and Z. You, A Flying-Adder architecture of frequency and phase
synthesis with scalability, IEEE Trans. on VLSI, pp. 637649, Oct., 2002.

94

[4] L. Xiu and Z. You, A new frequency synthesis method based on

Flying-Adder architecture, IEEE Trans. on Circuit & System II, pp. 130134,
March, 2003.
[5] L. Xiu, W. Li, J. Meiners, and R. Padakanti, A novel all digital phase
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Liming Xiu is an IC design lead in Texas

Instruments Inc. He has been working for
Texas Instruments since his graduation
from Texas A&M University in 1995. During his TI career, he has done significant
amount of work/research in PLL-related
areas. He is the principal inventor of
Flying-Adder frequency synthesis architecture which has
been used in many commercial products. He has published many IEEE journal papers and conference papers
and holds twelve granted and pending US patents. He is
also an expert on VLSI SoC integration with battle-proven
integration experience on several very large chips in
advanced CMOS nodes. In this area, he has one book
published in Nov. 2007 by IEEE-Wiley, VLSI Circuit Design
Methodology Demystified: A Conceptual Taxonomy. Liming
Xiu is a Senior Member of Technical Staff of Texas Instruments. He was general chair of IEEE CASS Dallas Chapter
2006 and 2007. Currently, he is activity chair of IEEE Dallas Section.

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