MICROCONTROLLER (AT89s52)

8051 microcontroller has 128 bytes of RAM, 4K bytes of on-chip

ROM, two timers, one serial port, and four ports (each 8-bits wide) all
on a single chip. The 8051 is an 8-bit processor i.e. the CPU can
work on only 8 bits of data at a time. The fixed amount of on-chip
ROM, RAM, and number of I/O ports in microcontroller makes them
ideal for many applications in which cost and space are critical.

The AT89C51 is a low-power, high-performance CMOS 8-bit

microcomputer with 4K bytes of Flash programmable and erasable
read only memory (PEROM). The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional
nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89S52 is a powerful
microcomputer, which provides a highly flexible and cost-effective
solution to many embedded control applications.

FEATURES:

• Compatible with MCS-51™ Products

• 4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low-power Idle and Power-down Modes

BLOCK DIAGRAM:
External
Interrupts
ETC.

Counter Inputs
On-chip
ROM for Timer 0
Interrupt
program On-chip
control
code RAM Timer 1

CPU

Osc

Bus Serial
4 I/O Ports
control port

P0 P1 P2 P3 TXD RXD

ADDRESS/DATA

PIN CONFIGURATIONS:
 P1.0 Vcc
1 40
P1.1 P0.0 (AD0)
2 39
P1.2 P0.1 (AD1)
3 38
P1.3 P0.2 (AD2)
4 37
P1.4 P0.3 (AD3)
5 36
P1.5 P0.4 (AD4)
6 35
P1.6 P0.5 (AD5)
7 34
P1.7 8 33 P0.6 (AD6)

RST 9 32 P0.7 (AD7)

(RXD) P3.0 10 31 EA/VPP

(TXD) P3.1 11 30 ALE/PROG

(INT0) P3.2 12 29 PSEN

(INT1) P3.3 13 28 P2.7 (A15)

(T0) P3.4 14 27
P2.6 (A14)
(T1) P3.5 15 26
P2.5 (A13)
PIN DESCRIPTION:
16 25
(WR) P3.6 P2.4 (A12)
17 24
(RD) P3.7 P2.3 (A11)

XTAL2 18 23 P2.2 (A10)

XTAL1 19 22 P2.1 (A9)

20 21
GND P2.0 (A8)

VCC - Supply voltage.

GND - Ground.
Port 0 - Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s are written
to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 may also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data
memory. In this mode P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming, and
outputs the code bytes during program verification. External pull-ups
are required during program verification.

Port 1 - Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 1 output buffers can sink/source four TTL inputs. When 1s
are written to Port 1 pins they are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IIL) because of the internal pull-
ups. Port 1 also receives the low-order address bytes during Flash
programming and verification.

Port 2 - Port 2 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @ DPTR). In
this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses
(MOVX @ RI), Port 2 emits the contents of the P2 Special Function
Register.

Port 2 also receives the high-order address bits and some control
signals during Flash programming and verification.
Port 3 - Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs. When 1s
are written to Port 3 pins they are pulled high by the internal pullups
and can be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (IIL) because of the pullups. Port
3 also serves the functions of various special features of the
AT89C51 as listed below:

RST - Reset input. A high on this pin for two machine cycles while the
oscillator is running resets the device.

ALE/PROG - Address Latch Enable output pulse for latching the low
byte of the address during accesses to external memory. This pin is
also the program pulse input (PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the

oscillator frequency, and may be used for external timing or clocking
purposes. Note, however, that one ALE pulse is skipped during each
access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR

location 8EH. With the bit set, ALE is active only during a MOVX or
MOVC instruction. Otherwise, the pin is weakly pulled high. Setting
the ALE-disable bit has no effect if the microcontroller is in external
execution mode.

PORT PIN ALTERNATE FUNCTIONS

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
PSEN – Program Store Enable is the read strobe to external program
memory. When the AT89C51 is executing code from external
program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to
external data memory.

EA/VPP - External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external program
memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP)
during Flash programming, for parts that require 12-volt VPP.

XTAL1 - Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2 - Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS:

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier, which can be configured for use as an on-chip
oscillator. Either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source, XTAL2 should be
left unconnected while XTAL1 is driven.
Figure 1. Oscillator Connections
XTAL1
C1

XTAL2
C2

GND

Note: C1, C2 = 30 pF +/- 10 pF for Crystals

= 40 pF +/- 10 pF for Ceramic Resonators

There are no requirements on the duty cycle of the external clock

signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and
low time specifications must be observed.

THE 8051 REGISTERS:

The most widely used registers of the 8051 are A (accumulator), B,
R0, R1, R2, R3, R4, R5, R6, R7, DPTR (data pointer), and PC
(program counter). All of the above registers are 8-bits, except DPTR
and the program counter. The 8 bots of a register are shown below
from the MSB (most significant bit) D7 to the LSB (least significant
bit) D0.

D7 D6 D5 D4 D3 D2 D1 D0

PROGRAM COUNTER:

The program counter points to the address of the next instruction to

be executed. As the CPU fetches the opcode from the program ROM,
the program counter is incremented to point to the next instruction.
The PC is 16 bits wide i.e. it can access program addresses 0000 to
FFFFH, a total of 64K bytes of code.

PSW (PROGRAM STATUS WORD) REGISTER

The PSW contains status bits that reflect the current state of the CPU
and is also called flag register. The PSW contains the Carry bit, the
Auxiliary Carry bit, the two register bank select bits, the overflow flag
bit, a parity bit, and two user definable status flags.

CY AC F0 RS1 RS0 OV --- P

CY PSW.7 Carry flag.

AC PSW.6 Auxiliary carry flag.
--- PSW.5 Available to the user for general purpose.
RS1 PSW.4 Register Bank selector bit 1.
RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
--- PSW.1 User definable bit.
P PSW.0 Parity flag.
RS1 RS0 Register Bank Address
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH

CY, THE CARRY FLAG

This flag is set whenever there is a carry out from the D7 bit. This flag
bit is affected after an 8-bit addition or subtraction. It can also be set
to 1 or 0 directly by an instruction such as “SETB C” and “CLR C”
where “SETB C” stands for “set bit carry” and “CLR C” for “clear
carry”.

AC, THE AUXILIARY CARRY FLAG

If there is a carry from D3 to D4 during an ADD or SUB operation, this

bit is set; otherwise, it is cleared. This flag is used by instructions that
perform BCD (binary coded decimal) arithmetic.

P, THE PARITY FLAG

The parity flag reflects the number of 1s in the A (accumulator)

register only. If the A register contains an odd number of 1s, then
P=1. Therefore, P=0 if A has an even number of 1s.

OV, THE OVERFLOW FLAG

This flag is set whenever the result of a signed number operation is
too large, causing the high-order bit to overflow into the sign bit.

RAM MEMORY SPACE ALLOCATION IN THE 8051

There are 128 bytes of RAM in the 8051, which are assigned
addresses 00 to 7FH. These 128 bytes are divided into three different
groups:

1. A total of 32 bytes from locations 00 to 1H hex are set aside for

register banks and the stack.

2. A total of 16 bytes from locations 20H to 2FH are set aside for
bit-addressable read/write memory.

3. A total of 80 bytes from locations 30H to 7FH are used for read
and write storage, or what is normally called a scratch pad.
These
80 locations of RAM are widely used for the purpose of storing
data and parameters by 8051 programmers.

7F
Scratch pad RAM
30

2F
Bit-Addressable RAM
20
1F
Register Bank 3
18
17
Register Bank 2
10
0F
Register Bank 1 (stack)
08
07
Register Bank 0
 00

REGISTER BANKS IN THE 8051

The 32 bytes of RAM which is set aside for the register banks and
stack is divided into 4 banks of registers in which each bank has 8
registers, R0 – R7. RAM locations from 0 to 7 are set aside for bank 0
of R0 – R7

where R0 is RAM location 0, R1 is RAM location 1, R2 is location 2,

and so on, until memory location 7 which belongs to R7 of bank 0.
The second bank of registers R0 – R7 starts at RAM location 08 and
goes to location 0FH. The third bank of R0 – R7 starts at memory
location 10H and goes to location 17H; and finally RAM locations 18H
to 1FH are set aside for the fourth bank of R0 – R7.
The following tables shows how the 32 bytes are allocated into 4
banks:

Bank 0 Bank 1 Bank 2 Bank 3

R7 7 R7 7 R7 7 R7 7
R6 6 R6 6 R6 6 R6 6
R5 5 R5 5 R5 5 R5 5
R4 4 R4 4 R4 4 R4 4
R3 3 R3 3 R3 3 R3 3
R2 2 R2 2 R2 2 R2 2
R1 1 R1 1 R1 1 R1 1
R0 0 R0 0 R0 0 R0 0
STACK IN THE 8051
The stack is a section of RAM used by the CPU to store information
temporarily. This information could be data or an address. The CPU
needs this storage area since there are only a limited number of
registers. The register used to access the stack is called the SP
(stack pointer) register. The stack pointer in the 8051 is only 8 bits
wide i.e. it can take values of 00 to FFH. When the 8051 is powered
up, the SP register contains value 07 which implies that RAM location
08 is the first location being used for the stack by the 8051.

The storing of a CPU register in the stack is called a PUSH, and

loading the contents of the stack back into a CPU register is called a
POP. In other words, a register is pushed onto the stack to save it
and popped off the stack to retrieve it.

PUSHING ONTO THE STACK:

In the 8051 the stack pointer (SP) is pointing to the last used location
of the stack. As data is pushed onto the stack, the stack pointer (SP)
is incremented by one and the contents of the register are saved on
the stack. To push the registers onto the stack, RAM addresses are
used.

POPPING FROM THE STACK:

Popping the contents of the stack back into a given register is the
opposite process of pushing. With every pop, the top byte of the stack
is copied to the register specified by the instruction and the stack
pointer is decremented once.

ADDRESSING MODES:
The addressing modes in the microcontroller instruction set are as
follows:

1. DIRECT ADDRESSING

In direct addressing, the operand is specified by an 8-bit address field

in the instruction. Only internal RAM and SFRs cab be directly
accessed.

2. INDIRECT ADDRESSING

In indirect addressing, the instruction specifies a register that

specifies a register that contains the address of the operand. Both
internal and external RAM can be indirectly accessed.
The address register for 8-bit addresses can be either the stack
pointer or R0 or R1 of the selected register bank. The address
register for 16-bit addresses can be only the 16-bit data pointer
register, DPTR.

3. REGISTER INSTRUCTIONS

The register banks, which contain registers R0 through R7, can be

accessed by instructions whose opcodes carry a 3-bit register
specification. Instructions that access the registers this way make
efficient use of code, since this mode eliminates an address byte.
When the instruction is executed, one of the eight registers in the
selected bank is accessed. One of four banks is selected at execution
time by the two bank select bits in the PSW.

4. REGISTER-SPECIFIC INSTRUCTIONS

Some instructions are specific to a certain register. For example,

some instructions always operate on the Accumulator, so no address
byte is needed to point to it. In these cases, the opcode itself points to
the correct register.
5. IMMEDIATE CONSTANTS

The value of a constant can follow the opcode in program memory.

For example,

MOV A, #100

Loads the Accumulator with the decimal number 100. The same
number could be specified in hex digits as 64H.

6. INDEXED ADDRESSING

Program memory can only be accessed via indexed addressing. This

addressing mode is intended for reading look-up labels in program
memory. A 16-bit base register (either DPTR or the Program
Counter) points to the base of the table, and the accumulator is set
up with the table entry number. The address of the table entry in
program memory is formed by adding the accumulator data to the
base pointer.