EE 705 : 2ND LAB ASSIGNMENT SUBMITTED BY BINOD KUMAR(143079023)

The ieee.numeric_bit library is used for implementing functions in both the device-under-test(dut)
file and the testbench file.
The dut is in the a2.vhd file.
The testbench is the a2_test.vhd file.
Important steps are as below:
1.Bit_vector typecasting is used to convert unsigned integers into bit_vector arrays.
2.To_integer function is used to convert the number in bit_vector format into integer format for
performing the shifting operations.
3.Unsigned type Casting is used for peforming addition and substraction operations as per the
standard ieee.numeric_bit library.
4.To_unsigned function is used for converting the integer numbes into unsigned numbers which are
then used for performing Bit_vector typecasting.
It is clear that 3 For loops ensure that all 256x256x4 test Cases are tested even though some of the
test Cases essentially give the same result.
Mathematical Operators used are-+,-.
In-Built functions used are-sll(shift left logical) and srl(shift right logical).
Compilation & Run Logs are on Page No.-4.Even Though VHDL files are attached, they are here
reproduced for reference:
VHDL CODES
1.Dut file
library ieee;
use ieee.numeric_bit.all;
Entity a2 is
port (x: in bit_vector(7 downto 0):="00000000";
y: in bit_vector(7 downto 0):="00000000";
z: out bit_vector(7 downto 0);
op_code: in bit_vector(1 downto 0):="00");
end entity;
architecture arch of a2 is
begin
process (x,y,op_code)
-- taking dummy variables and dummy arrays for fecilitating operations
variable bin:unsigned(7 downto 0);
variable n:bit_vector(7 downto 0):="00000000";
variable b: integer :=0;
begin
--converting operand(Y) into integer for shifting operation
b := TO_INTEGER(UNSIGNED(y));
case op_code is
when "00" =>

bin :=(UNSIGNED(x))+(UNSIGNED(y));
n := bit_vector(bin);
z <= n;
when "01" =>
bin :=(UNSIGNED(x))-(UNSIGNED(y));
n := bit_vector(bin);
z <= n;
when "10" =>
n:=x srl b;
z <= n;
when "11" =>
n:= x sll b;
z <= n;
when others => z <= "00000000";
end case;
end process;
end arch;

2.Testbench
library ieee;
use ieee.numeric_bit.all;
entity a2_test is
end entity;
architecture Behave of a2_test is
signal x,y,z: bit_vector(7 downto 0);
signal op_code: bit_vector(1 downto 0);
component a2
port (x,y: in bit_vector(7 downto 0);
z: out bit_vector(7 downto 0);
op_code: in bit_vector(1 downto 0));
end component;
begin
process is

variable bin:unsigned(7 downto 0);

variable b: integer:=0;
variable n:bit_vector(7 downto 0):="00000000";
begin
--looping for first operand(X) and waiting for the assignment to happen
for k in 0 to 255 loop
x<=bit_vector(TO_UNSIGNED(k,x'Length));
wait for 5 ns;
--looping for second operand(Y) and waiting for the assignment to happen
for j in 0 to 255 loop
y<=bit_vector(TO_UNSIGNED(j,y'Length));
wait for 5 ns;
--converting operand(Y) into integer for shifting operation and waiting for the assignment to happen
b := TO_INTEGER(UNSIGNED(y));
wait for 5 ns;
--looping for the op_code and waiting for the assignment to happen
for i in 0 to 3 loop
op_code<=bit_vector(TO_UNSIGNED(i,op_code'Length));
wait for 5 ns;
case op_code is
when "00" =>
bin :=(UNSIGNED(x))+(UNSIGNED(y));
n := bit_vector(bin);
wait for 5 ns ;
assert (z = n)
report "sum error." severity error;
when "01" =>
bin :=(UNSIGNED(x))-(UNSIGNED(y));
n := bit_vector(bin);
wait for 5 ns ;
assert (z = n)
report "subtraction error." severity error;
when "10" =>
n:=x srl b;
wait for 5 ns;
assert (z = n)
report "right shift error." severity error;
when "11" =>
n:=x sll b;
wait for 5 ns;

assert (z = n)
report "left shift error." severity error;
when others => assert (z = "00000000")
report "other error." severity error;
end case;
end loop;
end loop;
end loop;
assert false report "test completed." severity note;
wait;
end process;
dut: a2
port map(x => x,
y => y,
z => z,
op_code => op_code);
end architecture Behave;

COMPILATION & RUN LOGS:

The ghdl compilation and run logs are as given below: