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Rd = 1k
Rd = 5k
Input-output characteristics with various RD
Rd = 2k
Rd = 10k
Inference:
With the increase in the resistance Rd, the transition width (of input voltage) between output high and
output low decreases and the output low voltage at input high voltage also decreases. Thus, increasing
Rd improves the noise margin of the inverter.
The larger the slope of the linear region at the transition, the larger will be the gain of the amplifier
used with this inverter sub circuit, but the maximum output voltage swing will decrease.
Reason: Since in the transition region the transistor is in linear region,
W
2 )
= (( ) 0.5
=
2L
W
2L
Thus, as RD increases, the magnitude of the derivative increases. Thus the transition becomes more
sharp as the drop is faster in the linear region.
VDS = 0.3V
VDS = 0.7V
VDS = 0.9V
VDS = 1.1V
Thus, 0.40 =
1+0.3
1+0.9
= 0.25
VDS (V)
, mAV-2
gm ( mAV-1 ) at VGS=0.7V
rds = (1+VDS )(IDS)-1 at VGS=0.7V
0.3
1.5165
1.4
21.5 k
0.7
1.5165
1.6
22.0 k
0.9
1.5165
1.641
21.3 k
1.1
1.5165
1.674
21.4 k
-1
Thus, we can assume that gm = 1.64 mAV , rds = 21k at the operating point (VGS=0.7V, VDS=0.9V).
Now, consider the plot of ID vs. VGS at VD = 0.9V
= 2L (( )2 )(1 + )
_______
in saturation region.
From the curve slope, , for larger values of VDS, i.e. in saturation region,
Thus, = 1.6421 1
The (vd / id) vs. frequency for applied small signal drain voltage (0.01V peak ac) at VG = 0.7V, VD =
0.9V
Thus, = 22.15
4. The circuit will be :
So, = ( || )
Thus, = ( || )
Specifications:
VOUT = 0.9V, gain = 5,
VG = 0.7V
Now, since as all other parameters (voltages, ) are same as calculated in previous parts.
Large signal calculations,
Current through RD = Current through NMOS.
0.9
(( )2 )(1 + ) = 1.5165
=
0.01 (1 + 0.222 0.9)
2
2
0.9
= 9.0975 103
This gives,
1
= 98.93
0.2271 103
= 5.59
0.9
Thus, || = 0.848
If all the above conditions are satisfied,
we get || = ( || ) = 5.5 > 5 as specified.
So, if
= .
5.
The output and input signals w.r.t time are as follows:
6.
The differential input and output for 200mV peak sinusoid input is
Now, for the given differential amplifier circuit, the Vb should be such that the current through the
voltage source equals the one with 0.3V at the source.
Thus, from previous part of the same question, IDS = 0.227 mA.
Now, from the ID-VGS curve of the nmos transistor at VD = 0.3V we get VG = 0.745 V for the same
current.
Thus the corresponding input-output curve is
AC analysis :
Input = 50 mV peak
Output = 234 mV peak
Gain = 4.68
Thank you.