Digital'IC Design ETIN20': Outline&

L U N D UN I V E R S I T Y
Outline&
Digital'IC*Design*ETIN20'
Lecture'3*'Devices'con:nued'
Joachim'Rodrigues,'LUND'UNIVERSITY'
'
Recap&
Models&
Velocity&satura2on&
Exercise&
Sub8threshold&current&
Parasi2cs&
Capacitance&&
Resistance&
Fundamentals&
DC&margins&
& Lund University / Dept. of Electrical and Information Technology / September 4, 2014
- 2
Recap:&How&does&it&work?&
VGS must be
lager than a
threshold VT
Opens a
channel
VGS
Recap:&How&does&it&Work?&
A simple model:
k
I D = (VGS VT ) 2
2
k:=gainfactor
VDS
VGS > 0
When&VGS%is&increased&above&VT%
More&nega2ve&than&posi2ve&charges&are&
aHracted&close&to&the&gate&(turns&into&n8
type&material)&
n+
n+
p-
A&channel&is&formed&(Strong&inversion)&
ID
VGS > VT
VDS&drives&a&current&ID%
Gate
Source
Depletion region
Drain
p-substrate
Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 3
n+
n+
n-channel
p-
Depletion
Region
Depletion
Region
Recap:&Linear&Region&(Resis2ve&Opera2on)&
VDS%is&increased&slightly%
ID(VDS)%has&a&resis2ve&behavior%
Horizontal&E8eld&from&drain&to&source&
ID&has&a&linear&rela2on&to&VGS%
A&current&ID&is&established'
VGS > VT
VGS > VT
ID
VDS<VGS-VT
ID
n+
n+
n+
p-
p-
Depletion
Region
ID&is&propor2onal&to&the&horizontal&E8eld&
!&i.e.&to&the&charge&velocity&caused&by&the&drain&voltage&VDS%
VGS forms a
vertical E-field
n+
n+
Recap:&Satura2on&Region&
VDS%=%VGS%%%VT&&&&&&&&
ID&is&propor2onal&to&the&ver2cal&E8eld&
!&i.e.&to&the&#&of&charges&aHracted&by&the&gate&voltage&VGS%
n+
n-channel
n-channel
VDS<VGS-VT
ID
Strong&inversion&reached&precisely&(i.e.&VGD%=%VT)&&&
No&channel&close&to&the&drain&(pinch8o)&
ID%has&a&quadra2c&rela2on&to%VGS%&
ID%has&a&small&dependence&to%VDS%&
VGS > VT
ID
n+
VDS establish a
horizontal E-field pLund University / Dept. of Electrical and Information Technology / September 4, 2014 - 7
VDS=VGS-VT
n+
VDS /2"
p-
Depletion
Region
Recap&
Equations widely used models for manual
calculations
kn W
(VGS - VT ) 2 (1 + VDS ) saturation
2 L
V 2
W
< VGS - VT ; I D = kn ((VGS - VT )VDS - DS )(1 + VDS ) linear
L
2
VDS VGS - VT ; I D =
VDS
kn = nCox
Chapter&3&
The&Devices&Cont.&
Often added to
avoid discontinuity
VT = VT 0 + ( -2 F + VSB - -2 F )
Model&for&Manual&Analysis&
A&rst&order&model&for&the&velocity&saturated&
region:&
I DSAT
VDSAT 2
W
= n Cox ((VGS VT )VDSAT
)
L
2
A&Unied&Model&for&Manual&Analysis&
Vmin 2
W
ID = k
((VGS VT )Vmin
)(1 + VDS )
L
2
'
n
Vmin = min(VGS VT , VDS , VDSAT )
We will transform this model into its unified equivalent
Example&&Unied&Model&
A&Unied&Model&for&Manual&Analysis&
VDS 2
' W
I D = kn ((VGS VT )VDS
)(1 + VDS ) Resistive
L
2
= 0.06; kn'
Vmin = min(1.5 0.43, 1.5, 0.63)
V 2
W
((VGS VT )VDSAT DSAT )(1 + VDS ) Velocity saturated
L
2
W
Vmin 2
I D = k ((VGS VT )Vmin
)(1 + VDS )
L
2
0.632
I D = 172.5 106 ((1.5 0.43)0.63
)(1 + 0.06 1.5) = 89.4 A
2
'
n
Simple&Model&
Three&Regions&
VDSAT%
Model&for&manual&
calcula2ons&
0&.&63&&V&
&
x&10&
0&.&15&
84
2&
Simulated&
V&GS& =& 2&V&
I&D&&(mA)&
Velocity&
saturated&
Linear&
0&.&1&
I&D&&(A)&
1.5&
V&GS& =&1.5&V&
I D = 88 A
0&.&5&
1&
V&GS& =&1&V&
0.5&
0&
0&
Saturated&
region&
Vmin = min(VGS VT , VDS , VDSAT )
2.5&
Wmin
0.375
= 115106
= 172.5 A / V 2
Lmin
0.25
VGS and VDS

Find&Vmin& 15 min exercise: calculate ID for different
Velocity&
kn' W
ID =
(VGS VT ) 2 (1 + VDS ) Saturated
2 L
I D = kn'
VT = 0.43V ; VDS = 1.5V ,1V ; VGS = 1.5V ,1V ; VDSAT = 0.63V ;
0&
0.5&
1&
1.5&
2&
2.5&
V&DS&&(V)Technology
&
Lund University / Dept. of Electrical and Information
/ September 4, 2014 - 16
Saturated&
0&
V&DS&&(V)&
1&
2&
Transistor&Model&for&Manual&Analysis&
A&PMOS&Transistor&
Velocity&satura2on&is&less&pronounced&for&PMOS&due&to&lower&
mobility&
0&
Table&on&Back&Cover&
ID&(mA)&
VGS&=&81.0V&
80.02&
VGS&=&81.5V&
Assume&all&
numbers&
nega2ve!&
80.04&
80.06&
80.08&
VGS&=&82.0V&
Wmin = 0.375 m
Lmin = 0.25 m
VGS&=&82.5V&
80.1&
82.5&
82&
81.5&
81&
VDS&(V)&
80.5&
0&
The&Transistor&as&a&Switch&
Simplied&model&averages&the&
currents&on&the&endpoints&of&the&
transi2on&region&(pg&105)&
Velocity
Saturated
x&105&
Req depends on VDS
6&
Velocity
Saturated
5&
&
Problem: RON is time varying,

dependent on the operation
mode
7&
Req
%%
Req
ID (A)
R eq &(Ohm)
VDS (V)
VDD/2
VDD
4&
3&
2&
1&
0& 0.5&
&
1.5&
%% &
V DD &(V)
&
&
2.5
VDD (V)
1.5
2.5
NMOS (k)
35
19
15
13
PMOS (k)
115
55
38
31
Sub&Threshold&Current&&
&
Req%resistance&for&a&square&transistor&(W/L&=&1)&
in&0.25&um&
SECOND'ORDER'EFFECTS'
(Table&on&Back&Cover)&
Sub8Threshold&Region&
The&Trend&is&to&reduce&VT%
Logarithmic
ln(I
ln(IDD
))
The&sub&threshold&drain&
current&has&an&
exponen2al&rela2on&to&
the&gate&voltage&
(compare&to&bipolar).&&
Exponential increase of the

static power!
VT
High Ioff
Low
&
10m
ln (I D)
100u
1u
Sub threshold region
I off = I 0 e
10n
VT
Low Ioff
High
VT
VGS [V]
100p
VT
1p
VGS (V )
0
0.5
1.0
1.5
2.0
2.5
VGS VT
mvT
VT&in&Short&Channel&MOS&
VT&in&a&Short&Channel&MOS&
VDS = 0
n+
n+
p-
n+
n+
The&Drain/Source&
Deple2on&helps&the&
channel&to&strong&
inversion.&
n+
The depletion region

increases around the
drain when VDS increases
n+
p-
The effect can not be

neglected in a short
channel device
In&a&short&channel&the&
threshold&voltage&tends&
to&be&lower.&
VDS = VDD V tends to be lower

T
n+
n+
p-
p-
VT&in&Short&Channel&MOS&
Example8&Measurements&
VT
Channel stretching is
effective for leakage
reduction
VDS
Penalty: Speed
10
0.25
A&reference&circuit&was&
measured&in&the&sub8VT&
domain&VDD&<&500mV&
Energy/Operation [pJ]
0.3
0.35
[V]
0.4
10
0.25
0.45
0.3
DD
10
10
10
0.35
[V]
0.4
0.45
DD
10
Over&400&kHz&at&400mV&
0.25
0.3
0.35
[V]
DD
10
Total Energy
Dynamic Energy
Leakage Energy
Long devices have a

higher VT and
consequently lower
leakage
10
Frequency [Hz]
VT
Short
Channel
10
0.4
0.45
10
10
10
Frequency [Hz]
10
Lund University
/ September 4, 2014 - 29
Fig. 4. Measured
performance/inDept.
termsof
ofElectrical
energy and and
speedInformation
versus VDD Technology
at 23 C.
3Sep-14
29
Capacitance&
Two&Types&of&Capacitance&
Junc2on&Capacitance&
Diode&areas&
Contribu2on&from&two&parts&8&area&and&side&wall&&
Capacitance&
Gate&Capacitance&
chapter3.fm Page 112 Friday, January 18, 2002 9:00 AM
SECOND ORDER EFFECTS
8&Gate&to&Bulk&
8&Gate&to&Source/Drain&
112
THE DEVICES
Chapter 3
-16
10
VGS
x 10
Gate Capacitance (F)

(a)
Figure 3.31 Simulating the gate capacitance of an MOS
transistor; (a) circuit configuration used for the analysis, (b)
resulting capacitance plot for minimum-size NMOS transistor
in 0.25 m technology.
MOS&Capacitances&
6
5
4
3
2
-2
-1.5
-1
-0.5
GS
0.5
1.5
(V)
(b)
region and its surroundings. The detailed picture, shown in Figure 3.32, shows that the
junction consists of two components:
Gate&Capacitance&
Channel-stop implant
NA+
Source
Gate
Drain
CGS
CGD
n+
n+
CG
CSB
Cut off
Side wall
tox
Bottom
xj
n+
Side wall
n+
n+
n+
Channel
LS
CDB
Substrate NA
Figure 3.32
Detailed view of source junction.
Bulk&Cap.&
&
Junc2on&Cap.&
The side-wall
junction, formed by the source region with doping N and the p channel-stop implant with doping level N . The doping level of the stopper is usually
larger& than that of the substrate, resulting in a larger capacitance per unit area. The
side-wall junction is typically graded, and its grading coefficient varies from 0.33 to
0.5. Its
capacitance value equals C = C' x (W + 2 L ). Notice that no side-wall
Overlap&Cap.&
The bottom-plate junction, which is formed by the source region (with doping ND)
and the substrate with doping NA. The total depletion region capacitance for this
component equals Cbottom = CjWLS, with Cj the junction capacitance per unit area as
given by Eq. (3.9). As the bottom-plate junction is typically of the abrupt type, the
grading coefficient m approaches 0.5.
+
A
sw
Xd
Linear
Source
ND
jsw j
capacitance is counted for the fourth side of the source region, as this represents the
conductive channel.4
Since xj, the junction depth, is a technology parameter, it is normally combined with
C'jsw into a capacitance per unit perimeter Cjsw = C'jswxj. An expression for the total
junction capacitance can then be derived,
The&Capacitance&changes&with&
the&opera2on&mode&
Nonlinear'behavior&&
Saturation
n+
n+
Toactual
actualvalue
valueofofthe
thetotal
totalgate-channel
gate-channelcapacitance
capacitanceand
andits
itsdistribution
distributionover
overthe
the
To
threecomponents
componentsisisbest
bestunderstood
understoodwith
withthe
theaid
aidofofaanumber
numberofofcharts.
charts.The
Thefirst
firstplot
plot(Fig(Figthree
ure3.30a)
3.30a)captures
capturesthe
theevolution
evolutionofofthe
thecapacitance
capacitanceasasaafunction
functionofofVVGSGSfor
forVVDSDS==0.0.For
For
ure
thetransistor
transistorisisoff,
off,no
nochannel
channelisispresent
presentand
andthe
thetotal
totalcapacitance,
capacitance,equal
equaltoto
VVGSGS==0,0,the
L U N D U N I V E R S I TWLC
Y
appearsbetween
betweengate
gateand
andbody.
body.When
Whenincreasing
increasingVVGSGS, ,aadepletion
depletionregion
regionforms
forms
WLCoxox, ,appears
underthe
thegate.
gate.This
Thisseemingly
seeminglycauses
causesthe
thethickness
thicknessofofthe
thegate
gatedielectric
dielectrictotoincrease,
increase,
under
whichmeans
meansaareduction
reductioninincapacitance.
capacitance.Once
Oncethe
thetransistor
transistorturns
turnson
on(V
(VGSGS==VVT),
channel
which
T),aachannel
formedand
andCCGCB
dropstoto0.0.With
WithVVDSDS==0,0,the
thedevice
deviceoperates
operatesininthe
theresistive
resistivemode
modeand
and
isisformed
GCBdrops
thecapacitance
capacitancedivides
dividesequally
equallybetween
betweensource
sourceand
anddrain,
drain,ororCCGCS
WLCoxox/2.
/2.The
The
the
GCS==CC
GCD==WLC
GCD
largefluctuation
fluctuationofofthe
thechannel
channelcapacitance
capacitancearound
aroundVVGSGS=V
=VTTisisworth
worth remembering.
remembering. AA
large
designerlooking
lookingfor
foraawell-behaved
well-behavedlinear
linearcapacitance
capacitanceshould
shouldavoid
avoid operation
operation inin this
this
designer
region.
region.
Dynamic&Capacitance&
VDS=0&
WLC
WLC
oxox
Bottom
CC
GCS
GCS
2WLCoxox
2WLC
33
00
/(V
)
VV
/(V
-V-V
GS
DSDS
GS
T)T
&
at
e
CC
GCD
GCD
11
(b)CC
functionofofthe
thedegree
degreeofofsaturation
saturation
(b)
GCasasa afunction
GC
Figure3.30
3.30 Distribution
Distributionofofthe
thegate-channel
gate-channelcapacitance
capacitanceasasa afunction
functionofofVV and
andVV (from
(from[Dally98]).
[Dally98]).
Figure
Gate8Drain&
Gate8Body&Capacitance&
Oncethe
thetransistor
transistorisison,
on,the
theCapacitance&
distributionofofits
itsgate
gatecapacitance
capacitancedepends
dependsupon
uponthe
the
Once
distribution
becomes&0&with&a&
degreeofofsaturation,
saturation,measured
measuredby
bythe
theVVDSDS/(V
/(VGSGS-V
-VT)T)ratio.
ratio.As
Asillustrated
illustratedininFigure
Figure3.30b,
3.30b,
degree
becomes&0&with&
conduc2ng&channel&
satura2on&&
GSGS
DSDS
38Sep814&
34&
Side
Wall
Junc2on&Capacitance
1
Cbottom = C j Area =
Cdi%=%Cbo;om%+%Csw%
Cbo;om%=%Cj%&Area&&&&&&&&&&&Cj&
Dont'count'the'wall'
towards'the'channel'
CC
GC
GC
WLC
WLC
oxox
22
VV
GSGS
VV
TT
(a)CC
functionofofVV
(with V =0)
=0)
(a)
GCasasa afunction
GC
GSGS(with VDSDS
&
CC
GCS==CC
GCD
GCS
GCD
CDi%=%CBot%+%CSW%
Drain/Source Diffusion
Ch To
an w a
ne rds
l
CC
GC
GC
CC
GCB
GCB
VDS>&0V&
WLC
WLC
oxox
Total&
Capacitance&&
WLC
WLC
oxox
22
(1
in&F/m2&
Csw%=%Cjsw%&Perimeter&&&&&Cjsw&in&F/m&
&
Dont&count&the&wall&towards&the&channel&into&the&perimeter&
VBD / BS
1
2
C j 0 Area
Abrupt junction
Csw = C jsw Perimeter =

(1
Abrupt vs graded
junction is discussed
in the book (Diode)
VBD / BS
1
3
C jsw0 Perimeter
Graded junction
Cj/Cjsw&is&dependent&on&the&bulk&voltage&
Cj0&&and&0&are&process&parameters&&&
Gate&Capacitance&
Overlap&Capacitance&
Source
CGD = Cox W Xd
CG%=%Cox%%W%%Le%
Gate
Drain
Xd
&
Leff
CGS
CGS = Cox W Xd
CGD
CGB
Source
Gate
Xd
%
CG&depends&on&the&region&
&
Cox in F/m2
Cox&in&F/m2&
CGS = Co W
CGS
Co in F/m
CGB
Co or Xd are overlap
process parameters
Channel&Capacitance&
MOS&Capacitance&Example&
To Bulk
To Source
To Drain
Total Gate Cap.
CGCB
CGCS
CGCD
CG
Cutoff
COX W L
COX W L + 2 C0W
Resistive
(1/2) COX W L (1/2) COX W L
Saturation
(2/3) COX W L
COX W L + 2 C0W
(2/3) COX W L + 2 C0W
Cut&o:&No&channel&&CGC%=%CGCB%
Overlap&
Capacitance&
Resis2ve:&Channel&&Divide&CGC&in&two&parts&
(pg&107)&
Gate&Capacitance&8&0.35&micron&process&
&
Cox&=&4.6&fF/m2&
W&=&0.6m;&&Le&=&0.3&m;&&&
&
CG&=&Cox%W%Le&=&4.60.60.310812&=&&
CG&=&0.83&fF&
Satura2on:&&2/3&of&Channel&to&source&
Drain
Leff
Or
CGD = Co W
(Table 3-4)
Gate&is&overlapping&
Drain/source&
region&
CGD
4
Linearized&Junc2on&Capacitance&
Nonlinear'behavior:&Replace&non8linear&capacitance&by&a&
large8signal&equivalent&linear&capacitance.&
Distributes&equal&charge&over&the&voltage&swing&of&interest&
C (fF)
Abrupt
Cj =
Graded
1
C j0
Vhigh: upper voltage

Vlow : lower voltage
V
(1 D ) m
0
VD (V)
0
-5
-4
-3
m=
-2
-1
Ceq =
0.6
K eq =
1
1
for abrupt and m = for graded junction
2
3
Q j
VD
See page 83
Q j (Vhigh ) Q j (Vlow )
Vhigh Vlow
= K eq C j 0
0m [(0 Vhigh )1m (0 Vlow )1m ]

(Vhigh Vlow )(1 m)
Noise&on&Supply&Rails&
MOS&Decoupling&Capacitor&
&A&big&problem&on&large&
synchronously&clocked&chips&
Filters noise on
the supply lines
VDD
VDD
RWire
VDD
ISwitch
&On&chip&decoupling&
capacitors&helps&&
&&&&(&1/10&of&the&switched&C)&
The&world&is&not&digital.&We&need&to&
know&the&limita2ons&
Filler&Cells&in&a&Typical&0.13&um&Tech.&
Leaf Leaf
Cell Cell
Leaf
Cell
Leaf Cell
Leaf Leaf
Cell Cell
Leaf
Cell
Leaf
Cell
Leaf
Cell
Leaf Cell
Leaf
Cell
Leaf
Cell
Resistance&
VDD
Decoupling&&capacitance&
wherever&space&is&empty&%
SECOND ORDER EFFECTS
MOS&Simula2on&Models&
Parasi2c&Resistances&
SPICE&Level&1&(Shichman8Hodges)&
Long&channels&and&manual&calcula2ons&
Resistance&in&
diusion&and&
contact&
RS
RD
SPICE&Level&2&
Physical&model.&Not&accurate&for&sub&micron&tech.&
SPICE&Level&3&
Empirical&model&based&on&curve&matching&
BSIM'(Berkeley'Short*channel'IGFET'Model)'
Accurate'for'short'channel'devices'
EKV'model'for'latest'available'technologies'
Typical&Values&(0.35m)&
Parameter
NMOS
uA/V2
..
PMOS
uA/V2
k'
VT
Leff
Weff
175
0.50 V
0.30 um
0.55 um
0.58 V1/2
0.05
- 60
- 0.60 V
0.38 um
0.55 um
- 0.45 V1/2
- 0.15
tox
Cox
Cj0
Cjsw0
7.5 nm
4.6 fF/um2
0.93 fF/um2
0.28 fF/um
7.5 nm
4.6 fF/um2
1.42 fF/um2
0.38 fF/um
Discrete (BF 170)
50 mA/V2
2V
Seminar:&Drain&current,&opera2on,&mode,&parasi2cs&

Digital'IC Design ETIN20': Outline&

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L U N D UN I V E R S I T Y

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 4

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 5

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 6

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 8

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 10

Vmin = min(VGS VT , VDS , VDSAT )

We will transform this model into its unified equivalent

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 11

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 12

Vmin = min(1.5 0.43, 1.5, 0.63)

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 15

V&GS& =& 2&V&

Vmin = min(VGS VT , VDS , VDSAT )

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 13

VGS and VDS

VT = 0.43V ; VDS = 1.5V ,1V ; VGS = 1.5V ,1V ; VDSAT = 0.63V ;

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 17

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 18

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 19

Req depends on VDS

Problem: RON is time varying,

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 20

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 21

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 23

Exponential increase of the

Sub threshold region

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 24

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 25

The depletion region

The effect can not be

VDS = VDD V tends to be lower

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 26

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 27

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 28

Long devices have a

chapter3.fm Page 112 Friday, January 18, 2002 9:00 AM

SECOND ORDER EFFECTS

Gate Capacitance (F)

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 30

Lund University / Dept. of Electrical and Information Technology / September 4, 2014 - 31

Detailed view of source junction.

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Csw = C jsw Perimeter =

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Total Gate Cap.

(1/2) COX W L (1/2) COX W L

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Vhigh: upper voltage

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0m [(0 Vhigh )1m (0 Vlow )1m ]

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SECOND ORDER EFFECTS

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Discrete (BF 170)