HDL Lab Manual VTU

HDL LAB
Hardware Description
Language
Lab Manual
Prepared by: Sudha L.K

Department of Electronics &
Instrumentation
Bangalore Institute of Technology
Department of Electronics & Instrumentation, BIT
L.K.S
HDL Lab Manual
L.K.S
Cycle of Experiments for HDL Lab

l Cycle
I. Write a VHDL/VERILOG code to simulate all logic gates.
2. Write a VHDL/VERILOG code to synthesize 2:4 Decoder.
3. Write a VHDL/VERILOG code to simulate 8:1 Multiplexer.
4. Write a VHDL/VERILOG code to simulate 1:4 Demultiplexer.
5. Write a VHDL/VERILOG code to simulate 8:3 Encoder with/without
priority.
6. Write a VHDL/VERILOG code to synthesize 4 bit Comparator.
ll Cycle
I. Write a VHDL/VERILOG code to simulate and synthesize the function of Full
Adder using the following modeling styles and demonstrate the operation.
a) Data Flow. b) Behavioral. c) Structural.
2. Write a VHDL/VERILOG code to simulate SRFF and demonstrate the
operation.
3. Write a VHDL/VERILOG code to simulate JKFF.
4. Write a VIIDL/VERILOG code to synthesize T flip-flop.
5. Write a VHDL/VERILOG code to synthesize D flip-flop.
Ill Cycle
1. Write a VHDL/VERILOG code to synthesize 4 bit binary to gray code
converter.
2. Write a VHDL/VERILOG model for 4-bit ALU to simulate the following
functions
i) A + B
v) A AND B
ii) A-B
vi)A or B
iii) A Complement
vii) A NAND B
iv) A * B
viii) A XOR B.
3. Write a VHDL/VERILOG to synthesize BCD counter with
synchronous/asynchronous reset.
4. Write a VHDL/VERILOG code to synthesize 4 bit binary counter with
synchronous/ asynchronous reset.
5. Write a VHDL/VERILOG code to simulate a counter which counts the
sequence ______.
IV Cycle (Interfacing Experiments)

1. Write a VHDL code to display the Elevator operation.
2. Write a VHDL code to display the Hex keypad operation.
3. Write a VHDL code to interface DAC and generate a Triangular/Ramp
Wave
4. Write a VHDL code to control the speed of DC motor and
demonstrate the operation.
HDL Lab Manual

L.K.S
5. Write a VHDL code to change the Direction of Stepper motor.
6. Write a VHDL code to demonstrate the Relay operation.
HDL Lab Manual
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HDL Lab Manual
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HDL Lab Manual
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1. Write HDL code to realize logic gates and demonstrate the operation.
i) VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity basic_gates is
Port ( a,b : in std_logic;
and_g, or_g, not_a, nand_g, nor_g, xor_g, xnor_g : out std_logic);
end basic_gates;
architecture logic_gates of basic_gates is
begin
Truth Table
and_g <= a and b;
a b And_g or_g not_a nor_g nand_g
or_g <= a or b;
0 0
0
0
1
1
1
not_a <= not a ;
0 1
0
1
1
0
1
nor_g <= a nor b;
1 0
0
1
0
0
1
nand_g <= a nand b;
1
1
1
0
0
1
0
xor_g <= a xor b;
xnor_g <=a xnor b;
end logic_gates;
xor_g
xnor_
g
0
1
1
0
1
0
0
1
ii) Verilog code

module bgates(a, b, andg, org, notg, nandg, norg, xorg, xnorg);
input a,b;
output andg,org,notg,nandg,norg,xorg,xnorg;
assign andg = a&b;
assign org = a|b;
assign notg = ~a;
assign norg = ~(a|b);
assign nandg = ~(a&b);
assign xorg= a^b;
assign xnorg=~(a^b);
endmodule
RESULT: The gates were simulated and the truth table and waveforms were
observed on modelsim and verified.
HDL Lab Manual
L.K.S
2. Describe the function of full adder using the following modeling styles
and demonstrate the operation.
a) Data flow
b) Behavioral
c) Structural
a) Data flow
i) VHDL code:
library IEEE;
entity fad is
Port (cin, a, b: in std_logic;
s, c: out std_logic);
end fad;
architecture Behavioral of fad is
begin
s<=(a xor b) xor cin;
c<=(a and b)or (b and cin) or (cin and a);
end Behavioral;
ii) Verilog Code
module dataflow(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign sum = a ^ b ^ c;
assign carry = (a & b) | (b & c) | (c & a);
endmodule
HDL Lab Manual
b) Behavioral
i) VHDL code:
library IEEE;
entity fab is
Port ( d : in std_logic_vector(2 downto 0);
e : out std_logic_vector(1 downto 0));
end fab;
architecture Behavioral of fab is
begin
process(d)
begin
if (d="000") then e<="00";
elsif (d="001") then e<="10";
elsif (d="010") then e<="10";
elsif (d="011") then e<="01";
elsif (d="100") then e<="10";
elsif (d="101") then e<="01";
elsif (d="110") then e<="01";
else e<="11";
end if;
end process;
end Behavioral;
L.K.S
a
0
0
0
0
1
1
1
1
b c
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Truth Table
Sum Carry
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
e=sc
00
10
10
01
10
01
01
11
ii) Verilog code:

module add_bev_v(d, e);
input [2:0] d;
output [1:0] e;
reg[1:0]e;
always @(d)
begin
case(d)
3'd0:e=2'b00;
3'd1:e=2'b10;
3'd2:e=2'b10;
3'd3:e=2'b01;
3'd4:e=2'b10;
3'd5:e=2'b01;
3'd6:e=2'b01;
3'd7:e=2'b11;
default:;
endcase
end
endmodule
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C) Structural
i) VHDL code
library IEEE;
entity FullAdder is
Port ( Ain : in std_logic; Bin : in std_logic; Cin : in std_logic; Cout : out std_logic;
Sum : out std_logic);
end FullAdder;
architecture FullAdder of FullAdder is
-- Half Adder Component being Instantiated
Component Halfadder
Port ( Ain : in std_logic;
Bin : in std_logic;
Sum : out std_logic;
Carry : out std_logic);
end Component;
Signal temp1,temp2, temp3: std_logic; -- Signal Declaration
Begin
L1: Halfadder port map (Ain, Bin, temp1, temp2);
L2: Halfadder port map (temp1, Cin, Sum, temp3);
Cout <= temp2 or temp3;
end FullAdder;
ii) Verilog Code
module fulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
ha h1(b, c, s0, c0);
ha h2(a, s0, sum, c1);
or(carry, c0, c1);
endmodule
/*(module for half-adder)

module ha(a, b, s, c);
input a, b;
output s, c;
xor(s, a, b);
and(c, a, b);
endmodule)*/
RESULT: The full adder using data flow, behavioral and structural models was simulated
and the truth table was verified and waveforms were observed on modelsim.
HDL Lab Manual
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3. Write HDL code for the following combinational design and demonstrate
the operation.
a) 2 to 4 decoder
b) 4 bit binary to gray code converter.
a) 2 to 4 decoder
i)
VHDL code:
library IEEE;
entity 2dec is
Port ( x : in std_logic_vector(1 downto 0);
e : in std_logic;
y : out std_logic_vector(3 downto 0));
end 2dec;
architecture Behavioral of 2dec is
begin
process (x,e)
begin
if (e=0) then y<=0000;
else
case x is
when "00"=>y<="0001";
when "01"=>y<="0010";
when "10"=>y<="0100";
when "11"=>y<="1000";
when others => null;
end case;
end if;
end process;
end Behavioral;
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ii) Verilog code:

module decode_2_4(enable, din, dout);
input enable;
input [1:0] din;
output [3:0] dout;
reg [3:0] dout;
always @(enable,din)
begin
if(enable==1)
dout = 4'b0000;
else
case (din)
2'b00: dout=4'b0001;
2'b01: dout=4'b0010;
2'b10: dout=4'b0100;
2'b11: dout=4'b1000;
default: ;
endcase
end
endmodule
WAVEFORM
RESULT: The HDL program for 2 to 4 decoder is simulated and Truth Table is
verified and the waveforms were observed on modelsim
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b) 4 bit binary to gray code converter.

i) VHDL code:
library IEEE;
entity B2G is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end B2G;
architecture Behavioral of B2G is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end Behavioral;
ii)
Verilog code:
module bin_gray(binary, gray);

input [3:0] binary;
output [3:0] gray;
assign gray[3] = binary[3];
assign gray[2] = binary[3] ^ binary[2];
endmodule
WAVEFORM
RESULT: The HDL program for 4 bit binary to gray code converter were
simulated and the truth table was verified and waveforms were
observed on modelsim.
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4. Write HDL code for the following combinational design and demonstrate
the operation.
a) 8:1 Multiplexer. b) 1:4 Demultiplexer.
a) 8:1 Multiplexer.
i) VHDL code:
library IEEE;
entity multi_81 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC;
en : in STD_LOGIC);
end multi_81;
architecture Behavioral of multi_81 is
begin
process(sel,i,en)
begin
if(en='0')then y<='0';
else
case (sel) is
when "000"=>y<=i(0);
when "001"=>y<=i(1);
when "010"=>y<=i(2);
when "011"=>y<=i(3);
when "100"=>y<=i(4);
when "101"=>y<=i(5);
when "110"=>y<=i(6);
when "111"=>y<=i(7);
when others=>null;
end case;
end if;
end process;
end Behavioral;
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ii) Verilog code:

module mux_1(i, sel, en, y);
input [7:0] i;
input [2:0] sel;
input en;
output y;
reg y;
always @(sel,i,en)
begin
if(en==0) y=0;
else
case(sel)
3'd0: y=i[0];
3'd1: y=i[1];
3'd2: y=i[2];
3'd3: y=i[3];
3'd4: y=i[4];
3'd5: y=i[5];
3'd6: y=i[6];
3'd7: y=i[7];
default:;
endcase
end
endmodule
WAVEFORM
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b) 1:4 Demultiplexers.
i)
VHDL code:
library IEEE;
entity mux_14 is
Port (sel: in std_logic_vector (1 downto 0) ;
d: out std_logic_vector(3 downto 0) ;
y: in std_logic);
end mux_14;
architecture Behavioral of mux_14 is
begin
process (sel,y)
begin
d<= 0000;
case sel is
when "00"=> d(0)<=y;
when "01"=> d(1)<=y;
when "10"=> d(2)<=y;
when "11"=> d(3)<=y;
when others=> null;
end case;
end process;
end Behavioral;
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ii) Verilog code:

module demux_1_4(din, sel, op);
input[1:0] sel;
input din;
output [3:0] op;
reg [3:0] op;
always @ (din, sel)
begin
op = 4'd0;
case(sel)
2'd0: op[0] =din;
2'd1: op[1] = din;
2'd2: op[2] = din;
2'd3: op[3] = din;
endcase
end
endmodule
WAVEFORM
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5. Write VHDL code to realize 8 to 3 encoder with and without priority and
demonstrate the operation.
a) WITH PRIORITY
i) VHDL code:
library IEEE;
entity withp1 is
Port ( i : in std_logic_vector(7 downto 0);
end withp1;
architecture Behavioral of withp1 is
begin
y<="000" when i(0)='1'else
"001" when i(1)='1'else
"010" when i(2)='1'else
"011" when i(3)='1'else
"100" when i(4)='1'else
"101" when i(5)='1'else
"110" when i(6)='1'else
"111" when i(7)='1'else
"000";
end Behavioral;
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ii) Verilog code:

module pri(in, out);
input [7:0] in;
output [2:0] out;
reg[2:0] out;
always @ (in)
begin
casex (in)
8'bxxxxxxx1: out = 3'd0;
8'bxxxxxx10: out = 3'd1;
8'bxxxxx100: out = 3'd2;
8'bxxxx1000: out = 3'd3;
8'bxxx10000: out = 3'd4;
8'bxx100000: out = 3'd5;
8'bx1000000: out = 3'd6;
8'b10000000: out = 3'd7;
default: out = 3'd0;
endcase
end
endmodule
WAVEFORM
RESULT: The VHDL program for 8 to 3 encoder with priority was simulated
and the truth table was verified and the waveforms were observed on
modelsim.
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b) WITHOUT PRIORITY:
i) VHDL code:
library IEEE;
entity enc_83 is
Port ( i : in std_logic_vector(7 downto 0);
end enc_83;
architecture Behavioral of enc_83 is
begin
process (i)
begin
case i is
when "00000001"
when "00000010
when "00000100"
when "00001000"
when "00010000"
when "00100000"
when "01000000"
when "10000000"
when others
=> y<="111";
=> y<="110";
=> y<="101";
=> y<="100";
=> y<="011";
=> y<="010";
=> y<="001";
=> y<="000";
=> y<="000";
end case;
end process;
end Behavioral;
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ii) Verilog code:

module enc_no_pr(enable, din, dout);
input enable;
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
always @(enable,din)
begin
if(enable==1)
dout=4'b000;
else
case (din)
8'd1: dout=3'd0;
8'd2: dout=3'd1;
8'd4: dout=3'd2;
8'd8: dout=3'd3;
8'd16: dout=3'd4;
8'd32: dout=3'd5;
8'd64: dout=3'd6;
8'd128: dout=3'd7;
default: dout=3'd0;
endcase
end
endmodule
WAVEFORM
RESULT: The VHDL program for 8 to 3 encoder without priority was

simulated and the truth table was verified and the waveforms were
observed on modelsim.
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6. Design and implement HDL code for any Sequence counter and
demonstrate its operation:
i) VHDL code:
library IEEE;
entity anyseq is
Port ( clk,rst : in std_logic;
q : out std_logic_vector(3 downto 0));
end anyseq;
architecture Behavioral of anyseq is
signal a1: std_logic_vector (3 downto 0);
signal clkdiv : std_logic_vector (20 downto 0);
signal clk1 : std_logic;
begin
process(clk)
begin
if(clkevent and clk=1) then
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv(15);
end process;
process(clk1)
begin
if (rst ='1') then
a1<="0001";
elsif (clk1'event and clk1='1')then
case a1 is
when "0001" => a1 <="0011";
when "0011" => a1 <="0101";
when "0101" => a1 <="1001";
when "1001" => a1 <="0001";
when others=> a1<="0000";
end case;
end if;
end process;
q<=a1;
end Behavioral;
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ii) Verilog code:

module any_sequence_counter (clk,rst,qout);
input clk,rst;
output [3:0] qout;
reg[3:0] qout;
reg [20 :0] temp;
reg clk1;
always@(posedge clk)
begin
temp =temp+1;
clk1=temp[15];
end
always@(posedge clk1)
begin
if(rst==1)
qout=0001;
else
case (qout)
4b0001:qout=4b0011;
4b0011:qout=4b0010;
4b0010:qout=4b0110;
4b0110:qout=4b0111;
4b0111:qout=4b0001;
endcase
end
endmodule
WAVEFORM
RESULT: The VHDL code for Sequence counter was simulated and waveforms
were observed on modelsim and verified.
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7. Design and implement HDL code for a BCD counter using synchronous
and asynchronous reset and demonstrate its operation:
a) Synchronous BCD counter :
i) VHDL code:
library IEEE;
entity syncbcdcntr is
end syncbcdcntr;
architecture Behavioral of syncbcdcntr is
signal q1 : std_logic_vector (3 downto 0);
begin
process(clk)
begin
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv(15);
end process;
process(clk1)
begin
if(clk1'event and clk1='1')then
if(rst='1')then q1 <= "0000";
else
q1 <= q1+1;
if(q1=1001)then
q1=0000;
end if;
end if;
end if;
end process;
q <= q1;
end Behavioral;
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ii) Verilog code:

module synreset_bcd_upcounter(clk,rst,qout);
input clk,rst;
output [3:0] qout;
reg [3:0] qout;
reg [20 :0] temp1;
reg clk1;
begin
temp1 =temp1+1;
clk1=temp1 [15];
end
if (rst)
qout =4b0000;
else
begin
qout=qout+1;
if(qout==4b1010)
qout=4b0000;
end
endmodule
WAVEFORM
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b) Asynchronous BCD counter:

i) VHDL code:
library IEEE;
entity bcdasyn is
count : inout std_logic_vector(3 downto 0));
end bcdasyn;
architecture Behavioral of bcdasyn is
begin
process(clk)
begin
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv (15);
end process;
process (clk1,rst)
begin
if (rst='1') then
count<=0000;
elsif (clk1'event and clk1='1') then
count <= count +1;
if count ="1001" then
count <=0000;
end if;
end if;
end process;
end Behavioral;
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ii) Verilog code:

module asynreset_bcd_upcounter(clk,rst,qout);
input clk,rst;
output [3:0] qout;
reg [3:0] qout;
reg [20 :0]temp1;
reg clk1;
begin
temp1 =temp1+1;
clk1=temp1[15];
end
always@(posedge clk1 or posedge rst)
if (rst)
qout=4b0000;
else
begin
qout =qout+1;
if(qout==4b1010)
qout=4b0000;
end
endmodule
WAVEFORM
RESULT: The HDL code for BCD Counter using both synchronous and
asynchronous reset was simulated and waveforms were observed on
modelsim and verified.
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8. Design and implement HDL code for a Binary counter using synchronous
and asynchronous reset and demonstrate its operation:
a) Synchronous Binary counter
i) VHDL code:
library IEEE;
entity synbincntr is
end synbincntr;
architecture Behavioral of synbincntr is
signal q1 : std_logic_vector (3 downto 0);
begin
process(clk)
begin
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv(15);
end process;
process(clk1)
begin
if(clk1'event and clk1='1')then
if(rst='1')then
q1 <= "0000";
else
q1 <= q1+1;
end if;
end if;
end process;
q <= q1;
end Behavioral;
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Verilog code:
module synreset_bin_upcounter(clk,rst,qout);
input clk,rst;
output [3:0] qout;
reg [3:0] qout;
reg [20:0] temp1;
reg clk1;
begin
temp1 =temp1+1;
clk1=temp1[15];
end
begin
if (rst)
qout =4b0000;
else
qout=qout+1;
end
endmodule
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b) Asynchronous Binary counter

i)
VHDL code:
library IEEE;
entity asy_bin is
count : out std_logic_vector(3 downto 0));
end asy_bin;
architecture Behavioral of asy_bin is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk)
begin
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv(15);
end process;
process(clk1,rst)
begin
if (rst='1') then
temp<=0000;
elsif (clk1'event and clk1='1') then
temp <= temp+1;
end if;
end process;
count<=temp;
end Behavioral;
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ii)
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Verilog code:
module asynreset_bin_upcounter(clk,rst,qout);
input clk,rst;
output [3:0] qout;
reg [3:0] qout;
reg [20 :0] temp1;
reg clk1;
begin
temp1 =temp1+1;
clk1=temp1[15];
end
always@(posedge clk1 or posedge rst)
if (rst==1)
qout=4b0000;
else
begin
qout =qout+1;
end
endmodule
RESULT: The HDL program for 4 bit comparator was simulated and the
truth table was verified and waveforms were observed on modelsim.
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9. Write HDL code for 4 bit comparator and demonstrate the operation.
i) VHDL code:
library IEEE;
entity comparator is
Port ( a,b : in std_logic_vector(3 downto 0);
e,g,l : out std_logic);
end comparator;
architecture Behavioral of comparator is
begin
process(a,b)
begin
if a=b then e<='1';g<='0';l<='0';
elsif a<b then l<='1';e<='0';g<='0';
else g<='1';l<='0';e<='0';
end if;
end process;
end Behavioral;
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ii) Verilog code:

module comp(a, b, alb, agb, aeb);
input [3:0] a;
input [3:0] b;
output alb,agb,aeb;
reg alb,agb,aeb;
always @ (a,b)
begin
if(a<b) alb=1;
else alb=0;
if(a>b) agb=1;
else agb = 0;
if(a==b) aeb=1;
else aeb =0;
end
endmodule
WAVEFORM
RESULT: The HDL program for 4 bit comparator was simulated and the
truth table was verified and waveforms were observed on modelsim.
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10. Write a HDL for model for 4 - bit ALU to implement the
following functions:
(i) A + B
(ii) A B
(iii) not A
(iv) A x B
(v) A and B
(VI) A or B
(vii) A nand B
(viii) A xor B
i) VHDL code:
library IEEE;
entity ALU is
Port ( a1,b1 : in STD_LOGIC_VECTOR (3 downto 0);
opcode: in STD_LOGIC_VECTOR (2 downto 0);
zout: out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Behavioral of ALU is
signal a: std_logic_vector(7 downto 0);
signal b: std_logic_vector(7 downto 0);
begin
a<="0000" & a1;
b<="0000" & b1;
zout<= a+b when opcode="000" else
a-b when opcode="001" else
a or b when opcode="010" else
a and b when opcode="011" else
not a when opcode="100" else
a1*b1 when opcode="101" else
a nand b when opcode="110" else
a xor b when opcode="111";
end Behavioral;
Locked UCF file

NET "a1<0>"
LOC = "S:PIN1";
NET "a1<1>"
LOC = "S:PIN2";
NET "a1<2>"
LOC = "S:PIN3";
NET "a1<3>"
LOC = "S:PIN4";
NET "b1<0>"
LOC = "S:PIN5";
NET "b1<1>"
LOC = "S:PIN6";
NET "b1<2>"
LOC = "S:PIN7";
NET "b1<3>"
LOC = "S:PIN11";
NET "opcode<0>" LOC = "S:PIN13";
NET "zout<0>" LOC = "S:PIN17";
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ii) Verilog code:

module aluv2(a,b, opcode, m);
input [3:0] a,b;
input [2:0] opcode;
output [7:0] m;
reg [7:0] m;
always @ (opcode,a,b)
begin
case(opcode)
3'b000:m=a+b;
3'b001:m=a-b;
3'b010:m=a|b;
3'b011:m=a&b;
3'b100:m=~a;
3'b101:m=a*b;
3'b110:m=~(a&b);
3'b111:m=a^b;
endcase
end
endmodule
Locked UCF file

NET "a1<0>"
LOC = "S:PIN1";
NET "a1<1>"
LOC = "S:PIN2";
NET "a1<2>"
LOC = "S:PIN3";
NET "a1<3>"
LOC = "S:PIN4";
NET "b1<0>"
LOC = "S:PIN5";
NET "b1<1>"
LOC = "S:PIN6";
NET "b1<2>"
LOC = "S:PIN7";
NET "b1<3>"
LOC = "S:PIN11";
WAVEFORM
RESULT: The HDL program for 4 bit ALU was simulated and the truth
table was verified and waveforms were observed on modelsim.
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11. Develop the HDL code for the following flip-flops and demonstrate the
operation.
a) SR-FF
i) VHDL code:
library IEEE;
entity s_r_flip_flop is
Port (s, r, clk: in std_logic;
q: inout std_logic);
end s_r_flip_flop;
architecture Behavioral of s_r_flip_flop is
begin
process (clk)
begin
if (clk'event and clk = '1')then
if(s='0' and r='0') then
q <= q;
elsif (s = '0' and r = '1') then
q <= '0';
elsif (s = '1' and r = '0') then
q <= '1';
elsif (s= '1' and r = '1') then
q <= '0';
end if ;
end if ;
end process;
end Behavioral;
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ii) Verilog code:

module srff(s, r, clk, q);
input s,r,clk;
output q;
reg q;
always @(posedge clk)
begin
if (s==1'b0 & r==1'b0)
else if (s==1'b0 & r==1'b1)
else if (s==1'b1 & r==1'b0)
else if (s==1'b1 & r==1'b1)
end
q = q;
q = 0;
q = 1;
q = 0;
endmodule
WAVEFORM
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b) T- FF
i) VHDL code:
library IEEE;
entity t_ff is
Port ( t,clk : in std_logic;
q : inout std_logic:=0;
qb: out std_logic);
end t_ff;
architecture Behavioral of t_ff is
begin
process(clk)
begin
if(clk'event and clk='1') then
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv (15);
end process;
process (clk1,t)
begin
if (clk1'event and clk1 = '1')then
if (t='0') then
q<= '0';
elsif ( t = '1') then
q<= not q;
end if ;
end if ;
end process;
qb<=not q;
end Behavioral;
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ii) Verilog code:

module tff(clk, t,rst, q,qb);
input clk,t,rst;
output q,qb;
reg q,qb;
reg [20:0] temp1;
reg clk1;
always @ (posedge clk)
begin
temp1 = temp1+1;
clk1 = temp1[15];
end
always @ (posedge clk1)
begin
if(rst==1) q = 0;
else if(t==1)
q = ~q;
qb=~q;
end
endmodule
WAVEFORM
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c) D-FF
i) VHDL code:
library IEEE;
entity d_ff is
Port ( d,clk : in std_logic;
q,qb : inout std_logic);
end d_ff;
architecture Behavioral of d_ff is
begin
process (clk)
begin
if (clk'event and clk = '1') then
q<= d;
qb<=not d;
end if ;
end process;
end Behavioral;
ii) Verilog code:
module dff(clk, d, q, qb);
input clk,d;
output q,qb;
reg q,qb;
begin
q=d;
qb = ~q;
end
endmodule
WAVEFORM
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d) JK-FF
i) VHDL code:
library IEEE;
entity jkff is
Port ( clk,rst,j,k : in std_logic;
q : inout std_logic:=0;
qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
begin
process(clk)
begin
if(clk'event and clk='1') then
clkdiv <= clkdiv+1;
end if;
clk1<= clkdiv(15);
end process;
process(clk1,rst)
begin
if(rst='1')then q<='0';
elsif(clk1'event and clk1='1')then
if(j='0' and k='0')then q<=q;
elsif(j='0' and k='1')then q<='0';
elsif(j='1' and k='0')then q<='1';
elsif(j='1' and k='1')then q<=not q;
end if;
end if;
end process;
qb<= not q;
end Behavioral;
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ii) Verilog code:

module jkff(jk,reset,clk, q,qb);
input[1:0] jk;
input reset;
input clk;
output q,qb;
reg q,qb;
reg[20:0] temp1;
reg clk1;
begin
temp1 = temp1+1;
clk1 = temp1[20];
end
always @ (posedge clk1)
begin
if(reset==1)
q=0;
case(jk)
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
endcase
qb=~q;
end
endmodule
WAVEFORM
RESULT: The HDL program for all flip flops were simulated and the
Truth table was verified and waveforms were observed on modelsim.
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1. PROGRAM FOR SPEED CONTROL OF A DC-MOTOR

-- ALS NIFC37 DC motor
-- connect J4-pin 26 to GND
-- connect J4-pin 25 to +5V
-- connect J4-pin 5 to CPLD pin 9 (pdcm)
-- connect tkbase clk 500khz to CPLD pin 20
-- CPLD Pin 1,2,3 as SW 0,1,2;
-- sw0 sw1 sw2
-- 0 0
0
= 500rpm
-- 1 0
0
= 800rpm
--0 1
0
--- 1 1
1 = 2500rpm
library IEEE;
entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic );
end TKBDCM;
architecture behavioral of TKBDCM is
signal sclkdiv : std_logic_vector(11 downto 0);
begin
-- count upto 3000
process(p100k)
begin--+
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;
if(sclkdiv = "101110111000") then
sclkdiv <= "000000000000";
end if;
end process;
process(psw,sclkdiv)
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variable vdcm : bit;

begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4, 320, 44c, 578, 6a4, 7d0, 8fc, 9c4

if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
end if;
if(vdcm = '1') then pdcm <= '1';
else pdcm <= '0';
end if;
end process;
end behavioral;
UCF FILE FOR DC-MOTOR
NET "p100k"
NET "psw<0>"
NET "psw<1>"
NET "psw<2>"
NET "pdcm"
LOC = "S:PIN20";
LOC = "S:PIN1";
LOC = "S:PIN2";
LOC = "S:PIN3";
LOC = "S:PIN9";
PIN CONNECTION ON CPLD BOARD
DC Motor Module pin of 26 connected to GND of CPLD board.

25 connected to Vcc of CPLD board
5 connected to pin 9 of CPLD board
CPLD connections pin 20 is connected to clk
Pin 2, 3, 4 switch connected to Vcc or Gnd, because its
combination of inputs like 0 0 0
0 0 1 it means that the connection do like
difference combination) this increase
010
the motor speed.
1 1 1 (0 means connected to Ground of CPLD
1 means connected to +5V of CPLD)
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2. PROGRAM FOR AN ELEVATOR

library IEEE;
entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic );
end TKBELE;
architecture behavioral of TKBELE is
signal scurflr,skeyflr : integer range 0 to 15;
signal skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sflrclk,skeyclk : std_logic;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
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-- process keyval
process(skeyhit)
begin
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
then skeyflr <= 2;
then skeyflr <= 3;
then skeyflr <= 4;
then skeyflr <= 5;
then skeyflr <= 6;
then skeyflr <= 7;
then skeyflr <= 8;
then skeyflr <= 9;
then skeyflr <= 10;
then skeyflr <= 11;
then skeyflr <= 12;
then skeyflr <= 13;
then skeyflr <= 14;
then skeyflr <= 15;
end if;
end if;
end process;
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-- process clk divider

process(pclk100k)
begin
if( rising_edge(pclk100k)) then
end if;
skeyclk <= sclkdiv(6);
sflrclk <= sclkdiv(15);
end process;
-- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-- process floor motion
process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;
-- process display 7seg
process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval
: tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","000011
1","1111111","1101111","1110111","1111100","1011000","1011110","1111001","11100
01");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
end behavioral;
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UCF FILE FOR ELEVATOR

NET "pclk100K" LOC = "p66" ;
NET "pkeyret<0>" LOC = "P1" ;
NET "pkeyscn<0>" LOC = "P5" ;
NET "pkeyscn<1>" LOC = "P6" ;
NET "pkeyscn<2>" LOC = "P7";
NET "pkeyscn<3>" LOC = "P9";
NET "pdspmux<0>"
NET "pdspmux<1>"
NET "pdspmux<2>"
NET "pdspmux<3>"
NET "pdspseg<0>"
NET "pdspseg<1>"
NET "pdspseg<2>"
NET "pdspseg<3>"
NET "pdspseg<4>"
NET "pdspseg<5>"
NET "pdspseg<6>"
LOC = "P14" ;
LOC = "P15" ;
LOC = "P17" ;
LOC = "P18" ;
LOC = "P31"
LOC = "P32"
LOC = "P33"
LOC = "P34"
LOC = "P35"
LOC = "P36"
LOC = "P37"
;
;
;
;
;
;
;

Header-1
CNKEY
Header-2
CHANNEL
MUX
Header-3
Of CPLD
SEGMENT
1st 4 pins are columns

Last 4 pins are rows
66th pin is connected to clock.
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3. PROGRAM FOR AN HEXKEYPAD

library IEEE;
entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
end TKBHKY;
architecture behavioral of TKBHKY is
signal skeyval : integer range 0 to 15;
signal skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal skeyclk : std_logic;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
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-- process keyval
process(skeyhit)
begin
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyval <= 0;
then skeyval <= 1;
then skeyval <= 2;
then skeyval <= 3;
then skeyval <= 4;
then skeyval <= 5;
then skeyval <= 6;
then skeyval <= 7;
then skeyval <= 8;
then skeyval <= 9;
then skeyval <= 10;
then skeyval <= 11;
then skeyval <= 12;
then skeyval <= 13;
then skeyval <= 14;
then skeyval <= 15;
end if;
end if;
end process;
-- process clk divider
process(pclk100k)
begin
end if;
skeyclk <= sclkdiv(6);
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end process;
-- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-- process display 7seg
process(skeyval)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval
: tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","
0000111","1111111","1101111","1110111","1111100","1011000","1011110","111
1001","1110001");
begin
pdspseg <= segval(skeyval);
pdspmux <= "1101";
end process;
end behavioral;
UCF FILE FOR HEXKEYPAD
NET "pclk100K"
LOC = "p66" ;
NET "pkeyret<0>"
NET "pkeyret<1>"
NET "pkeyret<2>"
NET "pkeyret<3>"
NET "pkeyscn<0>"
NET "pkeyscn<1>"
NET "pkeyscn<2>"
NET "pkeyscn<3>"
LOC = "P1"
LOC = "P2"
LOC = "P3"
LOC = "P4"
LOC = "P5"
LOC = "P6"
LOC = "P7"
LOC = "P9"
NET "pdspmux<0>"
NET "pdspmux<1>"
NET "pdspmux<2>"
NET "pdspmux<3>"
NET "pdspseg<0>"
NET "pdspseg<1>"
NET "pdspseg<2>"
NET "pdspseg<3>"
;
;
;
;
;
;
;
;
LOC = "P14"
LOC = "P15"
LOC = "P17"
LOC = "P18"
LOC = "P31"
LOC = "P32"
LOC = "P33"
LOC = "P34"
;
;
;
;
;
;
;
;
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NET "pdspseg<4>" LOC = "P35" ;
L.K.S

Header-1
CNKEY
Header-2
CHANNEL
MUX
Header-3
Of CPLD
SEGMENT
1st 4 pins are columns

Last 4 pins are rows
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4. PROGRAM FOR A LCD DISPLAY

library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity tkblcd is
Port ( plcddat : out std_logic_vector (7 downto 0);
plcdrs,plcdrw,plcden : out std_logic;
end tkblcd;
architecture behavioral of tkblcd is
signal sdspclk : std_logic;
signal tchr1 : character;
constant mystr : string := "TKBASE";
begin
--clkdivider
process(pclk100k)
begin
end if;
sdspclk <= sclkdiv(15);
plcden <= sclkdiv(15);
end process;
-- display
process(sdspclk)
variable vdspseq : integer range 0 to 15;
variable vdspnum : integer range 0 to 15;
variable i1 : integer;
type tlcdtyp is array(0 to 15) of std_logic_vector (7 downto 0);
constant tlcddat : tlcdtyp :=
("00111000","00001110","00000010","00000001",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000" );
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begin
if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if;
if(vdspseq < 4) then
plcddat <= tlcddat(vdspseq);
vdspnum := 0;
else
plcddat <= tlcddat(vdspseq);
tchr1 <= mystr(vdspnum);
plcddat <=
std_logic_vector(to_unsigned(character'pos(tchr1),8));
end if;
plcdrw <= '0';
if(vdspseq < 4) then
plcdrs <= '0';
else
plcdrs <= '1';
end if;
end process;
end behavioral;
UCF FILE FOR LCD

NET "pclk100K"
NET "plcdrs"
NET "plcdrw"
NET "plcden"
LOC = P77";
LOC = P1";
LOC = P2";
LOC = P3";
NET "plcddat<0>LOC = P10";

NET "plcddat<1>LOC = P11";
NET "plcddat<2> LOC = "P12";
NET "plcddat<3>" LOC = "P13";
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Header-1
Control
Header-2
of CPLD
Data
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5. PROGRAM TO GENERATER RAMP

library IEEE;
entity rvc_dac is
op : out std_logic_vector(7 downto 0));
end rvc_dac;
architecture Behavioral of rvc_dac is
signal q: std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if(rst='0') then q<=(others=>'0');
elsif (clk'event and clk='1') then
q<= q+1;
end if;
----for step q<=q+8

end process;
op<=q;
end Behavioral;
#PINLOCK_BEGIN
NET "clk"
LOC =
NET "rst"
LOC =
NET "op<0>"
LOC =
NET "op<1>"
LOC =
NET "op<2>"
LOC =
NET "op<3>"
LOC =
NET "op<4>"
LOC =
NET "op<5>"
LOC =
NET "op<6>"
LOC =
NET "op<7>"
LOC =
#PINLOCK_END
"S:PIN1";
"S:PIN2";
"S:PIN3";
"S:PIN4";
"S:PIN5";
"S:PIN6";
"S:PIN7";
"S:PIN9";
"S:PIN10";
"S:PIN11";
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6. PROGRAM FOR A RELAY

library IEEE;
entity realy is
Port ( p : in std_logic;
m : out std_logic);
end realy;
architecture Behavioral of realy is
begin
process(p)
begin
if (p='1')then
m<='1';
else
m<='0';
end if;
end process;
end Behavioral;
UCF FILE FOR RELAY
NET "m" LOC = P2;
NET "p" LOC = P1;
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7. PROGRAM FOR DIRECTION CONTROL OF A STEPPER MOTOR

library IEEE;
entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
end TKBSTP;
architecture behavioral of TKBSTP is
signal sstpcnt : std_logic_vector(1 downto 0);
signal sstpclk,skeyhit : std_logic;
signal skeysts :std_logic_vector (3 downto 0);
begin
-- clkdivider
process(pclk100k)
begin
end if;
sstpclk <= sclkdiv(15);
end process;
-- key process
-- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin
if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;
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-- latch key press

process(skeyhit)
begin
if( falling_edge(skeyhit)) then
skeysts <= pkeycol;
end if;
end process;
-- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;
-- outputs signal pstpsig = D, C, B & A for stepper motor
-- TKBase from ucf file = 14,13,12, 11
-- als stepper controller = 4, 6, 3 & 5
process(sstpcnt)
begin
if (sstpcnt = "00") then pstpsig <= "0001";
elsif(sstpcnt = "01") then pstpsig <= "0111";
end if;
end process;
end behavioral;
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UCF FILE FOR STEPPER MOTOR

NET "pclk100K"
LOC = "S:PIN10";
NET "pkeycol<0>"
NET "pkeycol<1>"
NET "pkeycol<2>"
NET "pkeycol<3>"
LOC =
LOC =
LOC =
LOC =
"S:PIN1";
"S:PIN2";
"S:PIN3";
"S:PIN4";
NET "pkeyrow<0>" LOC = "S:PIN5";

NET "pstpsig<0>"
NET "pstpsig<1>"
NET "pstpsig<2>"
NET "pstpsig<3>"
LOC =
LOC =
LOC =
LOC =
"S:PIN11";
"S:PIN12";
"S:PIN13";
"S:PIN14";
Interfacing Module
Motor
2
HEADER 1
Power
CNKEY
CPLD pin 10 is connected to clock

pin 11 is connected to pin 5 of Interfacing Module
pin 26 of Interfacing Module is connected to GND
pin 25 of Interfacing Module is connected to VCC
59
HDL Lab Manual
L.K.S
8. PROGRAM TO GENERATE A TRIANGULAR WAVEFORM

library IEEE;
entity rvc_dac is
op : out std_logic_vector(7 downto 0));
end rvc_dac;
architecture Behavioral of rvc_dac is
signal q: std_logic_vector(7 downto 0);
signal ud:std_logic:='0';
begin
process(clk,rst)
begin
if(rst='0') then q<=(others=>'0');
elsif (clk'event and clk='1') then
if (ud='0')then q<=q+1;
elsif (ud='1')then q<=q-1;
end if;
end if;
end process;
op<=q;
process (clk)
begin
if (clk'event and clk='1')then
if(q="11111110")then ud<='1';
elsif(q="00000001")then ud<='0';
end if;
end if;
end process;
60
HDL Lab Manual
L.K.S
end Behavioral;
#PINLOCK_BEGIN
NET "clk"
NET "rst"
NET "op<0>"
NET "op<1>"
NET "op<2>"
NET "op<3>"
NET "op<4>"
NET "op<5>"
NET "op<6>"
NET "op<7>"
#PINLOCK_END
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
"S:PIN1";
"S:PIN2";
"S:PIN3";
"S:PIN4";
"S:PIN5";
"S:PIN6";
"S:PIN7";
"S:PIN9";
"S:PIN10";
"S:PIN11";
61
HDL Lab Manual
L.K.S
Ramp / Triangular
CPLD Pin Nos:-
1 is connected to clk
2 is connected to reset
3 is connected to pin21of Interfacing-Module
Pin no.26 of Interfacing Module is connected to ground
CPLD Board Pins
1
* *
26
24
22
20
18
16
6
4
2
Zigzag pattern
(4)22
21(3)
2 3 4 5 6 7 8 9 10 11 12
*
*
*
*
*
*
*
*
*
*
*
*
* * * * * * * *
*
*
*
*
*
*
*
*
*
*
*
*
25
23
21
19
17
15
*
(6)20
19(5)
(9)18
17(7)
(11)16
15(10)
DAC
Interfacing Module
5
3
1
Power supply
62

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HDL LAB

Prepared by: Sudha L.K

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Cycle of Experiments for HDL Lab

IV Cycle (Interfacing Experiments)

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

HDL Lab Manual

/*(module for half-adder)

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

b) 4 bit binary to gray code converter.

module bin_gray(binary, gray);

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

RESULT: The VHDL program for 8 to 3 encoder without priority was

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

HDL Lab Manual

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

ii) Verilog code:

Department of Electronics & Instrumentation, BIT

HDL Lab Manual

b) Asynchronous BCD counter: