Académique Documents
Professionnel Documents
Culture Documents
(I) Arithmetic Logic Unit (ALU): The arithmetic logic unit (ALU) is responsible for arithmetic and logical
operations. Basically an Arithmetic-Logic Unit (ALU) is an electronic circuit used to carry out the arithmetic
operations like addition, subtraction, multiplication and division. It also carries out logical operations like
greater than, less than, equal to etc. It performs the operation on the data provided by the input devices. It also
does the comparison operation which allows a program to make decisions based on its data input and results of
the previous calculations. The ALU operates on the data available in the main memory and sends them back
after processing again to main memory.
(II) Control Unit (CU): CU controls the overall operations of the computer. it is the chief coordinator of all
the operations or activities taking place in the computer system. Its main functions are to control the transfer
of data and information between various units and to initiate appropriate actions by the arithmetic-logic unit.
It fetches instructions from the memory, decodes them, and directs them to various units to perform the
specified tasks.
In addition to ALU and CU, CPU also has a set of registers for temporary storage of data, instructions,
addresses and intermediate results of calculation. The processor is plugged into the computers motherboard.
The processing capacity of a computer is measured in terms the amount of data processed by the CPU in one
operation.
B) Memory Unit: Memory unit stores the data, instructions, intermediate results and output temporarily,
during the processing of data. This memory is also called the main memory or primary memory of the
computer. The input data that is to be processed will be usually brought into the main memory before
processing. It also stores the instructions required for processing of data and any intermediate results. The
output is stored in memory before being transferred to the output device. CPU can work with the information
stored in the main memory. The following points are important as far as memory is concerned.
8 Bits = 1 Byte
1024 Bytes = 1 Kilobyte (KB)
1024 Kilobytes = 1 Megabyte (MB)
1024 Megabytes = 1 Gigabyte (GB)
The number of bits stored in a register is called a memory word. Different kinds of primary memory are
Random Access Memory (RAM) and Read Only Memory (ROM). You can read and write data in RAM but it is
volatile meaning whenever the power is switched off the contents of RAM is lost. So it is required to store the
data in the secondary memory if the data is required for the future use.
calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction
queue. Execution unit use the instruction queue to execute the instructions. Both BIU and EU work
asynchronously to execute instructions by using Pipelining mechanism which means overlapping of instruction
fetch and execute mechanism.
The pipelining results in efficient use of system bus and increases system performance.
The parts of BIU are:
i. Instruction Queue
ii. Segment Registers
iii. Instruction Pointer
i. Instruction Queue
The prefetched instruction bytes are stored in a first in first out (FIFO) group of registers called an
instruction queue for the Execution Unit (EU). When the EU is ready for its next instruction, it simply reads
the instruction from this instruction queue. This is much faster than sending out an address to the system
memory and to send back the next instruction byte.
Because string operations inherently involve looping, the 8086 machine language includes a prefix that
considerably simplifies the use of string primitives with loops. This prefix has the machine code
1 1 1 1 10 0 1 Z
where, for the CMPS and SCAS primitives, the Z bit helps control the loop. By prefixing MOVS, LODS and
STOS, which do not affect the flags, with the REP prefix 11110011, they are repeated the number of times
indicated by the CX register according to the following steps:
1. If (CX) = 0, exit the REP operation.
2. Perform the specified primitive.
3. Decrement CX by 1.
4. Repeat steps 1 through 3.
For the CMPS and SCAS primitives, which do affect the flags, the prefix causes them to be repeated the number
of times indicated by the CX register or until the Z-bit does not match the ZF flag, whichever occurs first.
The Z-bit/ZF flag comparison is made after each repetition. In any case the CX register is decremented with
each repetition and, unless a Z-bit/ZF flag mismatch causes the termination, CX will be 0 when the loop is
exited. Therefore, after repetitively executing the CMPS and SCAS primitives, the contents of ZF can be
examined to determine the cause of termination.
In assembly language the prefix is invoked by placing the appropriate repeat (REP) mnemonic before the
primitive. The REP mnemonics are defined in figure below.
B) Table Translation
It is sometimes necessary to translate from one code to another. A terminal may communicate with the
computer using the EBCDIC (Extended Binary Coded Decimal Interchange Code) alphanumeric code even
though the computer's software is designed to work with the ASCII (American Standard Code for Information
Interchange) code, or vice versa. Code conversions involving fewer than 8 bits (which accommodates up to 256
distinct entities) can be performed most easily by storing the desired code in an array of up to 256 bytes and
letting the original code be the index within the array of the desired code values. If the EBCDIC code were
being converted to the ASCII code, then the EBCDIC code value for "A", which is 11000001, would be added to
the address of the beginning of the array. Then, by putting the ASCII code for A, which is 01000001, in the
array element having the address of the array plus 00C1, the code conversion is readily accomplished.
The 8086 has an instruction specifically designed for executing this procedure. It is the XLAT instruction. This
instruction may appear either as XLATB or XLAT OPR. Both forms produce the following 1-byte machine
language instruction:
1110101111
In the XLAT OPR form, OPR is a dummy operand that is normally the variable name associated with the
translation table and serves only to improve the readability of the program. The XLAT instruction assumes the
base address of the byte array is in the BX register and the byte to be converted is in the AL register. The
desired code value is taken from the array and put in the AL register. None of the flags are affected.
4 Describe about Key-code Data Formats and FIFO Status Word formats. 5+5 10
Answer: Key-code Data Formats:
After a valid Key closure, the key code is entered as a byte code into the FIFO RAM, in the following format, in
scanned keyboard mode. The Key code format contains 3-bit contents of the internal row counter, 3-bit
contents of the column counter and status of the SHIFT and CNTL Keys The data format of the Key code in
scanned keyboard mode is shown in figure 8.26.
Figure 8.26: Data format of the Key code in scanned keyboard mode
In the sensor matrix mode, the data from the return lines is directly entered into an appropriate row of sensor
RAM that identifies the row of the sensor that changes its status. The SHIFT and CNTL Keys are ignored in this
mode. RL bits represent the return lines. Rn represents the sensor RAM row number that is equal to the row
number of the sensor array in which the status change was detected. Data format of the sensor code in sensor
matrix mode is shown in figure 8.27.
Figure 8.27: Data format of the sensor code in sensor matrix mode.
FIFO Status Word:
The FIFO status word is used in keyboard and strobed input mode to indicate the error. Overrun error occurs,
when an already full FIFO is attempted an entry, under run error occurs when an empty FIFO read is
attempted. FIFO status word also has a bit to show the unavailability of FIFO RAM because of the ongoing
clearing operation.
In sensor matrix mode, a bit is reserved to show that at least one sensor closure indication is stored in the
RAM. The S/E bit shows the simultaneous multiple closure error in special error mode. In sensor matrix mode,
a bit is reserved to show that at least one sensor closure indication is stored in the RAM, The S/E bit shows the
simultaneous multiple closure error in special error mode. The FIFO status word format is as shown in figure
below.
5 Write a note on
B) IEEE-488 Standard: IEEE-488 refers to the Institute of Electrical and Electronics Engineers (IEEE)
Standard number 488. IEEE-488 was created as HP-IB (Hewlett-Packard Interface Bus), and is commonly
called GPIB (General Purpose Interface Bus). The IEEE-488, General Purpose Interface Bus (GPIB), is a
general purpose digital interface system that can be used to transfer data between two or more devices. The
GPIB system is a parallel communication system, which can communicate with several devices through the
same interface port. The standard defines three types of devices that are connected to this bus:
controller
listener
Talker
All of which are connected through the IEEE-488 connector. A Talker sends data messages to one or more
Listeners, which receive the data. The Controller manages the flow of information on the GPIB by sending
commands to all devices. A digital voltmeter, for example, is a Talker and is also a Listener. The GPIB or IEEE
488 bus is a very flexible system and it allows the data to flow between any of the instruments on the bus, at a
speed suitable for the slowest active instrument. It is possible to purchase GPIB cards to incorporate into
computers that do not have the interface fitted. As GPIB cards are relatively cheap, this makes the inclusion of
a GPIB card into the system a very cost effect method of installing it.
The important key features are:
Up to 15 devices may be connected to one bus.
Total bus length may be up to 20 m and the distance between devices may be up to 2 m
Communication is digital (as opposed to analog) and messages are sent one byte (8 bits) at a time.
Data rates may be up to 1 Mbyte/sec
The connector used for the IEEE 488 bus is standardized as a 24-way Amphenol 57 series type. This provides
an ideal physical interface for the standard. The IEEE 488 or GPIB connector is very similar in format to those
that were used for parallel printer ports on PCs.
interface at 0x378, and for the second at 0x278. The first port is a bidirectional data register; it connects
directly to pins 2 through 9 on the physical connector. The second port is a read-only status register; when the
parallel port is being used for a printer, this register reports several aspects of printer status, such as being
online, out of paper, or busy. The third port is an output-only control register, which, among other things,
controls whether interrupts are enabled.
B) Universal Serial Bus (USB)
The two main problems associated with peripherals connected to computer systems today are "plug and play"
and speed of data transfer. USB (Universal Serial Bus) is designed to overcome these problems. Each USB port
provides a single connector for any device that previously used parallel, serial, keyboard, and mouse or game
ports. USB provides a serial bus standard for connecting peripherals devices to PC with simplified addition and
removal. USB can connect peripherals such as mice, keyboards, game pads and joysticks, scanners, digital
cameras, printers, external storage, networking components, etc. The design of USB is standardized by the USB
Implementers Forum (USB-IF), an industry standards body incorporating leading companies from the
computer and electronics industries. The figure below shows the typical Universal Serial Bus (USB).