CSC258

Week1: Transistors
Invented by William Shockley
Where do transistors fit?

What it does? Transistor connects point A and point B based on the value at point C.

Everything is made out of atoms

Protons are big and hardly move, it is positively charged. Electrons are small and has negative charged.
Neutrons are big and neutral. An atom is neutral.
How does electron flow? Electrons flow from regions of high electrical potential to region of low
electrical potential. (This is voltage). The direction of current is opposite the direction of the electron
movements, because electrons are negatively charged.

Path of electricity: only flows when the circuit closed, it always flow to the zero voltage point of the
circuit (i.e. the ground) and also refers to take patch with least resistance.
Semiconductors: Semiconductor materials (silicon and germanium) are somewhere in between
conductors and insulators, behaving like one or the other, depending on factors like temp and impurities
of material.
Impurity: Pure semiconductor is stable.
Each Silicon atom has 4 valence electrons forming bonds with other atoms, and the structure is stable

We encourage semiconductors conductivity by adding in to the structure:

N-type: some atoms with 5 valence electrons such as phosphorus (P).
P-Type: some atoms with 3 valence electrons such as baron (B)

The extra electrons and the holes are charge carriers, which can move freely through the material, thus
the conductivity is encourage.
If we put n-type and p-type semiconductors together we will form a PN-junctions.
PN-junctions:
Bringing p and n together, the electrons at the surface of the n-type material are drawn to the holes
(position of the missing electron) in the p-type.

When left alone, the electrons from the n section of the junction will fill the holes of the p section,
cancelling each other and creates a section with no free carriers called the depletion layer. Once this
depletion layer is wide enough, the doping atoms (the atom after losing and gaining electron) that
remain will create an electric field in that region.

Diffusion: This is the electrons initial movement from n-type to p-type to fill the positive holes.
Diffusion increases the width of the depletion layer (the region where there is no charge carrier).
When the phosphorus atoms in n-type semiconductor lose theirs electrons, they develop an overall
positive charge. Similarly, the boron atoms in p-type take on extra electrons, they develop an overall
negative charges.
Drift: The electron when travels to p-type to fill the holes will be pushed back to n-type, because of the
magnetic field generated by the negative charged boron particle. (Remember: same charge repel), this
movement, which is drawn by the electric field, is called drifting. Drifting decreases the width of the
depletion layer.
Equilibrium is reached when the depletion layer is of a certain width.
Depletion layers: Depletion layer is a region where there are no free carriers, made up of many of the
imbalanced phosphorus and boron atoms. The electric field caused by these atoms will cause holes to
flow back to the p section, and electrons to flow back to the n section, thus decreasing the size of
depletion layer.
Applying voltage to PN-junction:
This can be done in two different ways: Positive voltage to the P-size (the boron size) or Positive voltage
to N-size (the phosphorus size).
Forward Bias (Positive voltage to P, Boron, -):
Reverse Bias (Positive voltage to N, Phosphorus,
+):

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Metal Oxide Semiconductor Field Effect Transistor: (MOSFET)

nMOS:
N-P-N junction.
Gate High connected
Gate Low disconnected

pMOS:
P-N-P
Gate low, connected.
Gate high, disconnected.
Model basic use of transistor:
The current only flow
from D to S only when:
Vg is high, the
potential difference
between g and s is
high, so Vgs is high,
the circuit connects
and
Vd is high, the
potential difference
between d and s is
high, so Vds is high.
Transistor to gate:
Not Gate

And

OR

XOR

NAND GATE ??
NAND is the best logic gate
because:
It uses fewer transistors
than other gates.
All other logic functions
(AND, OR, ) can be
implemented using only
NAND.

Week 2: Circuit Creation

Transistors are semiconductor circuits that can connect the source and the drain together, depending
on the voltage value at the gate.

For NPN MOSFETs (nMOS), source and drain are connected when the gate value is high.
For PNP MOSFETS (pMOS), source and drain are disconnected when the gate value is low.

Logic Gates: And, Or, Not

Making boolean expressions:

Logic circuit with the boolean expression: ((A or B) and (not A or not B)) or C

Systematic approach for more complicated circuit:

3 steps:
Creates truth tables based on desired behavior of the circuit.
Good Boolean expression that express that truth table. (* key)
Convert Boolean expression to gates.
Truth table, min term, max term:

Minterm (small letter) : an AND expression with every input present in true or complemented form.
Min-term only has one output which is 1, and the rest are 0.

Maxterm (capital letter): an OR expression with every input presents in true or complemented form.
Max-term only has one output, which is 0, and the rest are 1.
Example: Given 3 inputs (A, B, C),
(A.B.C), (A.~B.C) are min-term. (all values of A, B, C have to be high in order for output to be
high)
A+B+C, A+B+~C, A are max-term. (Any value of A or B or C is low, in order for the output to
be low)
Given n inputs, there always are 2n min-terms and max-terms possible.
Use of min-term and max-term:

Note that: Min-term and Max-term are just the fancy ways to name the sets of input.
Creating Boolean expression from min and max-term:
Sum of min-term (SOM): AB + AB + AB
Product of max-term (POM): (A+B).(A+B).(A+B)

Sum of min-term (SOM) truth table example:

Product of max (P.O.M) truth table example:

Summary:
SOM expresses which inputs cause the output to go high.
POM expresses which inputs cause the output to go low.
SOMs are useful in cases with few input combinations that produce high output.
POMs are useful in cases with few input combination that produce low output.
https://www.youtube.com/watch?v=d-amzrRVhfE
Reducing Boolean expression using Karnaugh-Map:

Use K-Map to simplify the Boolean expression for the truth table below:

Step 1: Draw the corresponding K-Map:

A
A

BC
m0
m4

BC
m1
m5

BC
m3
m7

BC
m2
m6

K-map can be of any size, and have any number of inputs.

Since the adjacent min-term only differ by a single literal, they can be combined into a single term that
omits that value.
Step 2: Draw box to cover all number 1.

Rule for drawing the box:

Boxes must be rectangular, and aligned with map.
Number of values contained within each box must be a power of 2.
Box may overlap with each other.
It may wrap across the edge of map.
Step 3: deriving the Boolean expression from the K-map
The Boolean expression for the K-map above is a sum of min-term:
B.C + AC

Note: If we are given 4 inputs, then the corresponding K maps will be:

Alternatively, everything can be done using Max-terms:

Step 1: draw the corresponding K-Map (Note the difference in column label)
B+C
B+C
B+C
A
M0
M1
M3
A
M4
M5
M7
B+C
0
0

B+C
1
1

B+C
0
1

Step 2: Draw box that cover all of the 0

B+C
B+C
A
0
0
A
1
0

B+C
1
1

B+C
0
1

A
A

B+C
0
1

B+C
M2
M6

Step 3: Deriving the Boolean expression from the K-map

The Boolean expression of the K-map above is the product of max-terms:
(A+C)(B+C)
Note: if we are given 4 inputs, then the corresponding K-Map will be:

Week 3: Logical Device

K-Map review:

Y = BCD + ACD + ABD + ABC

Y = A.B + C.D + BD + BC + AD + AC

Note: There are cases where no combinations are possible. K-maps cannot help these cases:

Multiplexers (Mux)
Behavior: Output is X if S is 0, and Y if S is 1: (X & ~S) | (Y & S)

Multiplexer design:

Verilog 1 bit multiplexer:

module mux(X, Y, S, M);
input X, Y, S;
output M;
assign M = (X & ~S) | (Y & S);
Half Adder:
Input: two 1-bit numbers
Output: 1-bit sum and 1-bit carry

Expression for C (the carrier): X & Y

Expression for S (the sum): X ^ Y X & ~Y | ~X & Y
Half Adder design:

Verilog 1 bit half adder:

module half_adder(X, Y, C, S):
input X, Y;
output C, S;
assign C = X & Y;
assign S = X ^ Y;
endmodule
Full Adder:
It is similar to half-adders, but with another input Z (the carrier), which represents a carry-in bit. C and Z
sometimes labeled as Cout Cin.
When Z is 0, the unit behaves exactly like a half adder, when Z is one:

Full adder design:

Expression for S (the sum): (X & ~Y & ~Z) | (~X & ~Y & Z) | (X & Y & Z) | (~X & Y & ~Z)
(X^Y^Z)
Expression for C (the carrier): (X & Z) | (X & Y) | (Y & Z)

Verilog 1 bit full adder:

module full_adder(sum, cout, a, b, cin);
output sum, cout;
input a, b, cin;
assign cout = (a & b) | (b & cin) | cin & a);
assign sum = a ^ b ^ cin;
endmodule
module full_adder2(sum, cout, a, c, cin);
output sum, count;
input a,b,cin;
assign {cout, sum} = a + b + cin;
endmodule

Ripple-carry adder: Full adder units are chained together in order to perform operation.

Subtractors:
Subtractors are an extension of adders, it perform addition on negative number. There are two types, or
we can say two ways to store negative version of a number.
Unsigned: a separate bit exists for the sign, data bits store the positive version of the number.
Signed: all bits are used to store a 2s complement negative number.
Twos complement:
We have 1s complement: 01001101 10110010, 11001100 00110011, the result is just the negation
of the input.
The 2s complement is similar, but we add 1 to the result of 1s complement. So 01001101 10110010
+ 1 10110011, 11001100 00110011 + 1 00110100
So if we add the 2s complement number to the original number, we will get the result of zero. In other
words, the 2s complement of A is like ~A!
Unsigned subtraction example:
General algorithm for A B:
Get the 2s complement of B.
Add that value to A.
If there is an end carry (Cout is high), the final result is positive and does not change.
If there is no end carry (Cout is low), we get 2s complement of the result (B-A) and add a
negative sign to it.
Example:

Signed Subtraction:
Store negative number in 2s: Negative numbers are generally stored in 2s complement notation.
Subtraction can then be performed by using the modified version of the binary adder circuit with
negative numbers.
Given a 3 bits binary number, the largest unsigned number that it can represent is 7 and the smallest

Comparator: