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CURRICULUM VITAE

M.MURALI
Email-id: muralimunaswamy@gmail.com
Mobile: 9791105891

Objective:
Seeking a challenging position to deploy and use my technical, academic knowledge and
experience in the best possible method to growth of the organization.
Work experience:
Organization name : Oxford Engineering College.
Designation

: Assistant Professor-1 / Research associate.

Duration

: 1year 8 Months (3rd October 2011 to 10th June 2013).

Subjects Handle

: VLSI Design, VLSI Design Lab, Circuits and Devices Lab.

Projects Guided

: 2 UG Projects.
1) ASIC Implementation of CORDIC.
2) ASIC Implementation of FIR Filter using DAA.

Other Projects

: Worked in CADENCE, Mentor Graphics for Design of Wave pipelined


Circuits design (Under Research) at Oxford Engineering College.

Organization Name : Polenza Technologies.


Designation

: VLSI and Embedded Engineer.

Duration

: 1 Year (20th January 2014 to till now)

Academic records

Degree

B.E(ECE)

College

Institution

passing

Anna university of

College, Trichy.

technology, Trichy.

Athimanjeripet.
Govt. Hr. Sec. School,

SSLC

Year

Oxford Engineering

Govt. Hr. Sec. School,


HSC

University/

Athimanjeripet.

2011

% Of Marks

77.5

State board

2007

69.91

State board

2005

80

Technical skills:
Languages

: C, C++.

Operating Systems : Windows XP, Vista, Linux, Windows7.


Tools

: Xilinx, Altera, CADENCE, Mentor Graphic, Microchip IDE, Keil


micro vision, Microwind, Tanner, Protues.

Mini projects:
Title

: 1. Soil moisture controller


Using AND gate the moisture content in the soil is detected.
2. Rain water wiper.
The water sensor is used to detected water and automatically the
shutter is closed.

Project :
Title

: Optimized adder circuit using NOR gates in cadence tool.


Novel implementations of adders and majority circuits evolved
using universal gates contain fewer transistors than the smallest existing
implementations of other gate circuits. So these gates significantly
improve the success rate of the search process and reducing delay. Also
power consumption has been found to be less.

Achievements:

First prize for recitation competition from Andhra Samskrithi Manjari, Athimanjeripet.

Second prize for mini project of Rain water wiper in Oxford engineering college,
Trichy.

Presented a paper on Wireless sensor networks in monitoring crop cultivation in Cape


institute of technology, Tirunelveli.

Presented a paper on Implementation of wireless access nodes in Gnanamani College of


engineering, Namakkal.

Presented a paper on An ATPGA for low power VLSI design using ring counter and
LFSR in Indra Ganesan College of engineering, Trichy.

Presented a paper on Wireless sensor networks in monitoring crop cultivation in Sona


college of Technology, Salem.

Workshop and In-plant training:

Undergone In-Plant training in BSNL, Trichy, for five days from 16-06-09 to
20-06-2009.

Undergone In-Plant training in Blue Chip Technologies, Trichy from 07-12-2009 to


14-12-2009.

Participated in IETE faculty development program on Metamaterials and Microwave


Integrated circuits in Shri Angalamman college of engineering and technology, Trichy.

Attended Soft Skill Development program in Oxford College, Trichy for five days from 2308-2010 to 28-08-2010.

Participated in the two day workshop p on Network On Chip Architectures during 23rd to
25th Feb 2012 at Oxford Engineering College, Trichy.

Attended the six-day Train the-trainer Program on Analog System Design using
ASLKv2010 Starter Kit held at Texas Instruments India, Bangalore during 26-31 March,
2012.

Participated in Staff Development Program on New and Emerging Trends in Image and
Video Processing from 13-24 May 2013, at Jayaram College of Engineering and Technology,
Trichy.

Attended the Faculty development Program on Hands on Training on Design Finishing


for Chip Tapeout during June 2013, at R.M.K Engineering College, Kavaraipettai.

Projects Handle

Project Title

: An area efficient multiplexer based CORDIC

Description

: In this project multiplexer has been proposed for the ASIC implementation of unrolled
CORDIC processor. The efficacy of this approach is studied for the implementation
on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8
stages and using two schemes one using adders in all the stages and another using
multiplexers in the second and third stages.

Project Title

: Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

Description

: Input vector monitoring concurrent built-in self-test (BIST) schemes perform testing
during the normal operation of the circuit without imposing a need to set the circuit
offline to perform the test. These schemes are evaluated based on the hardware
overhead and the concurrent test latency (CTL), i.e., the time required for the test to
complete in FPGA tools, whereas the circuit operates normally. The proposed
scheme is shown to perform significantly better than previously proposed schemes
with respect to the hardware overhead and CTL tradeoff.

Project Title

: Low power High-speed divide-by-4/5 counter

Description

: A new high-speed divide-by-4/5 counter is developed. Based on this divide-by4/5counter, a 3V 2M -1.1 GHz dual-modulus divide-by-128/129 prescaler
designed with 0. 90nm CMOS technology is presented.

Project Title

: Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal FeedThrough Scheme

Description

: In this project, a low-power flip-flop (FF) design featuring an explicit type


pulse- triggered structure and a modified true single phase clock latch based on a
signal feed-through scheme is presented. The proposed design successfully solves the
long discharging path problem in conventional explicit type pulse- triggered FF (PFF) designs and achieves better speed and power performance.

Project Title

: Self controllable voltage level Circuit for low power high-speed 7T-SRAM cell.

Description

: A low leakage power 7T SRAM is designed in this project, The stand-by leakage
power of 7T sram is reduced by incorporating a newly-developed leakage current
reduction circuit called a Self-controllable Voltage Level (SVL) circuit.
Simulation result of 7t SRAM design using CADENCE tool shows the reduction
in total average power.

Project Title

: Design and Simulation of Low Power Dynamic Logic Circuit Using Footed
Diode Domino Logic.

Description

: In this project, we proposed a new technique to reduce power dissipation for domino
logic circuits. In this proposed circuit we put a diode on the foot of domino logic
circuit which results in power reduction as compared to reported and conventional
domino logic. We are using NMOS as a diode and due to this extra diode (NMOS), in
precharge period leakage current reduce due to stacking effect.

Project Title

: Applying Effective Dynamic Frequency Scaling Method in Contactless


Smart Card.

Description

: A creative dynamic frequency scaling method in contactless smart card is presented


for the first time. A low power magnetic field detection circuit, a simple load
detection circuit, the quick load comparator and the simple clock switch scheme in
the method are also presented. We developed low power circuits above blocks.
Compare to the presented circuits results the proposed circuits are less power..

Project Title

: Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders.

Description

: In this work gate diffusion input technique is used to reduce the leakage power in
4*4Wallace tree multiplier which has been designed by using one bit full adder. The
proposed method replaces all the full adders in 4*4 Wallace tree multiplier by gate
diffusion input technique based full adders. The full adders are the main block of

power dissipation in multipliers so by reducing the dissipation in full adders ultimately


power dissipation in the multiplier will be reduced.
Project Title

: Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop.

Description

: In this project we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a
novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs
eliminate the large capacitance present in the precharge node of several state-of-the-art
designs by following a split dynamic node structure to separately drive the output pullup and pull down transistors.

Personal information:
Full Name

: Murali.M

Date of Birth

: 30.06.1989.

Marital Status

: Single.

Nationality

: Indian.

Languages know

: English, Telugu, and Tamil.

Passport Number

: M0168778

Date of Issue

: 14th July 2014

Valid Until

: 13th July 2024

Permanent Address

: 3/1476 Mettu Street,


Athimanjeripet (P.O),
Pallipat (T.K),
Thiruvallur (Dist)-631202,
Tamil Nadu.

Reference:
1.

Mr.P.RENGAPRABHU, M.TECH, M.B.A., (Ph.D)


Associate .Professor, ECE, Department,

2. Mr.C.SRINIVASAN, M.E,
CEO, Polenza Technologies,

Oxford Engineering College,

Singaperumal Kovil,

Trichy-09.

Chengalpattu.

Place: Chennai.

Signature

Date: 12-02-2015
(MURALI.M)