Linear and Digital Ic Lab 2011-12 (KTM & NS)

Department of Electrical and Electronics Engineering
LABORATORY MANUAL
LINEAR AND DIGITAL INTEGRATED CIRCUITS

LABORATORY
LINEAR AND DIGITAL IC LABORATORY
S. NO.
NAME OF THE EXPERIMENT
Page No.
1.a
STUDY OF LOGIC GATES
03
1.b
STUDY OF FLIP FLOPS
07
2.
ADDERS, SUBTRACTORS AND REDUCTION OF A BOOLEAN

EXPRESSION USING KARNAUGH MAP
12
3.a
CODE CONVERTERS, ODD PARITY GENERATOR AND ODD

PARITY CHECKER
18
3.b
STUDY OF ENCODERS AND DECODERS
23
DESIGN AND IMPLENTATION OF 4-BIT MODULO

4.
5.
COUNTERS
DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT
REGISTERS
27
34
STUDY AND DESIGN OF 4 :1 & 8 :1 MULTIPLEXER AND

6.
DEMULTIPLEXER
54
7.
MONOSTABLE AND ASTABLE MULTIVIBRATOR USING 555

TIMER
59
8.
APPLICATIONS OF OPERATIONAL AMPLIFIERS
68
9.a
DIGITAL TO ANALOG CONVERTER
82
9.b
ANALOG TO DIGITAL CONVERTER
88
VOLTAGE TO FREQUENCY CHARACTERISTICS OF

10.a
10.b
NE/SE 566 IC
FREQUENCY MULTIPLICATION USING NE/SE 565 PLL IC
http://annauniversitystudymaterials.blogspot.in/
94
100
Page 2
Experiment: 1.a
STUDY OF LOGIC GATES
Aim:
To study the truth tables of various logic gates and verify them experimentally
using appropriate integrated circuits.
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12
Component Name
AND Gate
OR Gate
NOT Gate
NAND Gate
NOR Gate
EXOR Gate
EXNOR Gate
Bread Board
Light Emitting Diodes
Connecting wires
Regulated Power supply
Current Limiting Resistor
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7400
IC 7402
IC 7486
IC 4077
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
1
1
1
As Req.
As Req.
1
As Req.
Theory:
The logic gates are the basic building blocks of digital systems. A logic gate
produces an output level depending upon the input levels present at that instant. The
functionality of any logic gate can be explained by the corresponding truth table and
logical expression. Both NAND and NOR gates can perform all the three basic logic
functions (AND, OR and NOT), so they are called as Universal gates.
AND Gate Truth Table
IC7408 AND Gate
Page 3
OR Gate Truth Table
IC7432 OR Gate
NOR Gate Truth Table
IC7402 NOR Gate
NAND Gate Truth Table
IC7400 NAND Gate
Page 4
XOR Gate Truth Table
IC7486 XOR Gate
XNOR Gate Truth Table
IC4077 XNOR Gate
NOT Gate Truth Table
IC7404 NOT Gate
Page 5
Procedure:
1. Connections are made as shown in the wiring diagram.
2. The input logic levels are applied from D.C. power supply and the corresponding
output logic level is checked through an LED.
3. All possible input combinations and their corresponding outputs as per the truth
table, are verified.
Page 6
Experiment: 1.b
STUDY OF FLIP FLOPS
Aim:
To study the truth tables of various flip flops and verify them experimentally
using appropriate integrated circuits.
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
Component Name
OR Gate
NOT Gate
NAND Gate
NOR Gate
Bread Board
Connecting wires
Part No/Range
IC 7432
IC 7404
IC 7400
IC 7402
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
As Req.
As Req.
1
As Req.
Theory:
S-R Flip-flop:
The output Q is called the state of the flip-flop
S=1, R=0 Sets the state to 1
S=0, R=1 Resets (or Clears) the state to 0
S=0, R=0 is the Hold state
S=1, R=1 is not allowed
SR Flip-Flop- Excitation Table
Truth Table
Page 7
Because the 11 input will not be allowed, the result is a dont care, and Q = S + Rq. This
is the characteristic equation for an S-R flip-flop.
D Flip-flop:
When CLK = 0, the flip-flop holds
When CLK = 1
D q
0 0
1 0
0 1
1 1
Characteristic Equation: Q = D
D Flip-Flop-Excitation Table
D Flip-Flop-Truth Table
Page 8
J-K Flip-flop
If J and K are different then the output Q takes the value of J at the next clock
edge.
If J and K are both low then no change occurs. If J and K are both high at the
clock edge then the output will toggle from one state to the other.
Characteristic Equation
Q = Jq + Kq
Page 9
JK Flip-Flop Excitation Table
Truth Table:
T Flip-flop:
The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input.
Page 10
T Flip-Flop Excitation Table
Truth Table
Characteristic Equation
Q = Tq + Tq
Procedure:
1. Connections are made as shown in the logic diagram.
2. The input clock pulse are applied from digital trainer and the corresponding output
logic levels are checked through LEDs.
3. The workings of flip-flops are verified using truth table.
Inference:
Result:
Viva Questions:
1. What is mean by flip flop?
2. What is the difference between flip flops and latches?
Page 11

3.
4.
5.
6.
7.
8.
What is mean by edge triggered and level triggered flipflop?

What is the characteristic equation for JKFF?
What is mean by setup time and hold time?
What are the applications of flip flops?
What is the 1's and 2's complement of the decimal number 25?
What types of flip-flops can be used to implement the memory elements of a
counter?
9. How is a J-K flip-flop made to toggle?
10. The term hold always means ________.
Experiment: 2
ADDERS, SUBTRACTORS AND REDUCTION OF A BOOLEAN EXPRESSION
USING KARNAUGH MAP
Aim:
To design, construct and test the following digital circuits;
1. Half-adder
2. Full-adder
3. Half-subtractor
4. Full-subtractor and to reduce the given Boolean expression using a Karnaugh
map, implement the reduced expression and test the same.
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
Component Name
AND Gate
OR Gate
NOT Gate
EXOR Gate
Bread Board
Connecting wires
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7486
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
As Req.
As Req.
1
As Req.
Theory:
Page 12

Adders and subtractors are part of digital arithmetic circuits that perform
arithmetic operations. An adder is a digital circuit that adds two bits and a carry and
outputs a sum bit and carry bit. A subtractor, subtracts the subtrahend bit from the
minuend bit, considering the borrow due to previous subtraction and outputs difference
bit and borrow bit. A Half-adder will not consider the carry obtained from preceding
addition and can be used only for LSB addition. Similarly a half-subtractor can be used
only for LSB subtraction, since the borrow obtained from preceding subtraction is not
considered.
Design Methodology:
The required circuits are designed using appropriate truth tables. Each output is
expressed as a Boolean algebraic function of all the inputs. The obtained logical
expressions for each of the outputs are reduced using either Karnaugh maps or Boolean
laws.
Karnaugh map:
Karnaugh map is a chart, composed of an arrangement of adjacent cells, each
representing a particular combination of variables in sum or product form. K-map
provides a simple, systematic method of simplifying a Boolean expression, without
changing the functionality of the expression. The simplification leads to reduction in
number of gate inputs during implementation.
Half Adder:
S(X, Y) = (1, 2)
S=X'Y+XY'
S= X Y
CARRY(X, Y) = (3)
CARRY=XY
Circuit
Truth Table
Page 13
K MAP
Full Adder:
S(X, Y, Z) = (1, 2, 3)
SUM(X,Y,Z) = X'Y'Z + XY'Z' + X'YZ' + XYZ
S= X Y Z
CARRY(X, Y, Z) = (7)
CARRY= XY + XZ + YZ
Circuit:
Truth Table
X
0
0
0
0
1
Y
0
0
1
1
0
Z
0
1
0
1
0
SUM
0
1
1
0
1
CARRY
0
0
0
1
0
Page 14

1
1
1
0
1
1
1
0
1
0
0
1
1
1
1
K MAP
Half Subtractor:
K MAP
Full Subtractor
Circuit
Page 15
Truth Table
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
Difference
0
1
1
0
1
0
0
1
Borrow
0
1
1
1
0
0
0
1
K MAP
Page 16
Procedure:
output logic levels are checked through LEDs.
3. For adders and subtractors, all possible input combinations and their corresponding
outputs as per their truth tables are verified.
4. The given Boolean expression is entered in an appropriate K-map. Groups are formed
such that all the entries are covered. Equivalent terms representing each group is written
to obtain the simplified expression.
5. Step 4 operations are repeated for the canonical form representation of the given
expression and the simplified expression is obtained.
6. The simplified expressions obtained from step4 and steps 5 are compared for total
number of gate inputs. The expression with minimum number of gate inputs is
implemented using AND, OR and NOT gates and the truth table is verified.
Page 17
Inference:
Result:
Viva Questions:
1.
2.
3.
4.
5.
6.
7.
8.
What is mean by half adder?

What is mean by full adder?
What is mean by parallel adder?
What is mean by carry lookahead adder?
What is mean by ripple carry adder?
What is mean by parallel binary adder?
What are the different types of adder implementation?
Realize the functions of NOT, AND, OR and NAND gates only with NOR
gates.
9. Reduce the following using tabulation method.
F = m2 + m3 + m4 + m6 + m7 +m9 + m11 + m13.
10. List out the differences between half adder and full adder.
Experiment: 3(a)
CODE CONVERTERS, ODD PARITY GENERATOR AND ODD PARITY
CHECKER
Aim:
To design, construct and test the following digital circuits;
1.
Gray to Binary code converter
2.
Binary to gray code converter
3.
4-Bit Odd Parity Generator and
4.
4-Bit Odd Parity Checker
Apparatus Required
S.No
1.
2.
3.
4.
Component Name
Not Gate
EXOR Gate
Bread Board
Part No/Range
IC 7404
IC 7486
-
Quantity in Nos
1
2
1
As Req.
Page 18

5.
6.
7.
Connecting wires
Current Limiting Resister
(0-30V)
330 ohm
As Req.
1
As Req.
Theory:
Code Converter:
Code converters are logic circuits whose inputs are bit patterns representing
numbers or characters in one code and whose outputs are their corresponding
representations in a different code.
Gray Code:
It is a non-weighted code used in instrumentation and data acquisition systems,
where linear or angular displacement is measured and converted into equivalent digital
values. Gray code is an unit-distance code because successive code words in this code
differ by only one bit position.
Parity Generator and Parity Checker:
When binary data is transmitted, it is susceptible to noise that can alter or distort
its contents. The simplest technique for detecting single-bit errors is that of adding an
extra bit, known as the parity bit, to each word being transmitted. There are two types of
parity odd parity and even parity. For odd parity, the parity bit is set to a 1 at the
transmitter such that the total number of 1 bits in the word including the parity bit is an
odd number. When the digital data is received, the parity checking circuit generates an
error signal if the total number of 1 bits is even in an odd-parity system.
Design Methodology:
The required circuits are designed using appropriate truth tables. Each output is
expressed as a Boolean algebraic function of all the inputs. The obtained logical
expressions for each of the outputs are reduced using either Karnaugh maps or Boolean
laws.
Binary to Gray Converter:
Page 19
Gray to Binary Converter:
Four Bit Odd Parity Generator:
Page 20
Four Bit Odd Parity Checker:
Gray to Binary Code Conversion Table:
Page 21
Procedure
Page 22

output logic levels are checked through LEDs.
3. For the first three circuits all possible input combinations and their corresponding
outputs as per their truth tables are verified.
4. For a 4-bit odd parity checker, the error conditions are simulated and appropriate
observations are made for three different cases.
Experiment: 3(b)
Page 23

STUDY OF ENCODERS AND DECODERS
Aim:
To design
1. 8:3 Encoder
2. 3:8 Decoder
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Component Name
AND Gate
OR Gate
Not Gate
NAND Gate
NOR Gate
Bread Board
Connecting wires
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7400
IC 7402
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
1
As Req.
As Req.
1
As Req.
Theory:
Encoder:
An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2n input lines and n output lines. The output lines generate the binary
equivalent of the input line whose value is 1.At any one time, only one input line has a
value of 1. The figure below shows the truth table of an 8:3 encoder. It has got 8 inputs
and 3 outputs.
Page 24

Circuit Diagram:
Truth Table of 8:3 Encoder
Decoder:
It is a logic circuit that converts an n bit binary input code into m bit output
line activated such that any one is selected for each one of possible combination of
inputs.
Page 25
Page 26

Procedure
2. The input clock pulse are applied from digital trainer and the corresponding output
logic levels are checked through LEDs.
3. The working of decoding and encoding are verified for proper operation.
Inference:
Result:
Viva Questions:
1. What is mean by encoder?
2. What is mean by decoder?
3. How does an encoder differ from decoder?
4. What is mean by odd and even parity? Is mean by counter?
5. What are the applications of decoder?
6. What is mean by priority encoder?
7. Convert the decimal 65 to BCD, Excess-3 and Gray code.
8. What are codes? List the different codes with examples.
9. Which digital system translates coded characters into a more useful form?
10. A BCD decoder will have how many rows in its truth table?
Page 27

Experiment: 4
DESIGN AND IMPLENTATION OF 4-BIT MODULO COUNTERS
Aim:
To design, construct and test the following types of counters
1.
Synchronous counter Mod 6
2.
Synchronous 4-Bit Binary Counter
3.
Asynchronous 4 Bit Binary Counter
4.
Asynchronous Decade Counters
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Component Name
AND Gate
OR Gate
Not Gate
NAND Gate
NOR Gate
Flip Flop
Trainer kit
Bread Board
Connecting wires
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7400
IC 7402
IC74LS73
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
2
1
1
As Req.
As Req.
1
As Req.
Theory:
A counter is a sequential machine that produces a specified count sequence. The
count changes whenever the input clock is asserted. There is a great variety of counter
based on its construction.
1. Clock: Synchronous or Asynchronous
2. Clock Trigger: Positive edged or Negative edged
3. Counts: Binary, Decade
4. Count Direction: Up, Down, or Up/Down
5. Flip-flops: JK or T or D
A counter can be constructed by a synchronous circuit or by an asynchronous
circuit. With a synchronous circuit, all the bits in the count change synchronously with
Page 28

the assertion of the clock. With an asynchronous circuit, all the bits in the count do not all
change at the same time.
A counter may count up or count down or count up and down depending on the
input control. Because of limited word length, the count sequence is limited. For an n-bit
counter, the range of the count is [0, 2n-1]. The complement of the count sequence counts
in reverse direction. If the uncomplemented output counts up, the complemented output
counts down. If the uncomplemented output counts down, the complemented output
counts up. The natural count sequence is to run through all possible combinations of the
bit patterns before repeating itself. External logic can be used to arbitrary cause the
counter to start at any count and terminate at any count. A binary counter produces a
count sequence similar to the binary numbers. A decade counter counts from 0 to 9, thus
making it suitable for human interface. Other counters count to 12 making them suitable
for clocks.
Two Classes of Counters
Asynchronous Counters (Ripple counters)
Synchronous Counters
Asynchronous: The events do not have a fixed time relationship with each other and do
not occur at the same time.
Synchronous: The events have a fixed time relationship with each other and do occur at
the same time.
Counters are classified according to the way they are clocked. In asynchronous
counters, the first flip-flop is clocked by the external clock pulse and then each
successive flip-flop is by clocked the output of the preceding flip-flop. In synchronous
counters, the clock input is connected to all of the flip-flop so that they are clocked
simultaneously. It is used to count how many clock pulses just have entered. Number of
flip-flops are combined together in order to count the input clock pulses. The count exists
in the form of binary and it is called the state of the counter. If the counter has n flipflops, it can have a maximum of 2n states or unique states; it is called the modulus of the
counter. The number of unique states passed by the counter before coming back to its
initial state is called the module of a counter. If a counter does not utilize all possible
unique states as valid states, it is to be called as shortened modulus counter.
Page 29

The change in state of flip-flop will ripple from LSB to MSB which represents
flip-flop and hence called as ripple counter.
For designing a shortened modulus counter, an appropriate reset signal to clear
inputs of all the flip-flops present is given.
Synchronous Counters:
In synchronous counters, the clock inputs of all the flip-flops are connected
together and are triggered by the input pulses. Thus, all the flip-flops change state
simultaneously (in parallel).
Logic diagram of a synchronous mod-6 counter:
Page 30

Determination of the minimal-sum expressions for a synchronous mod-6 counter
using clocked JK flip-flops.
Synchronous 4-Bit Binary Counter:
Page 31

Asynchronous Counters:
An asynchronous counter is one in which the flip-flop within the counter do not
change states at exactly the same time because they do not have a common clock pulse.
The main characteristic of an asynchronous counter is each flip-flop derives its
own clock from other flip-flops and is therefore independent of the input clock.
Consequently, the output of each flip-flop may change at different time, hence the term
asynchronous. From the asynchronous counter diagram above, we observed that the
output of the first flip-flop becomes the clock input for the second flip-flop, and the
output of the second flip-flop becomes the clock input for the third flip-flop etc. For the
first flip-flop, the output changes whenever there is a negative transition in the clock
input. This means that the output of the first flip-flop produces a series of square waves
that is half the frequency of the clock input. Since the output of the first flip-flop becomes
the clock of the second flip-flop, the output of the second flip-flop is half the frequency
of its clock, i.e. the output of the first flip-flop that in turn is half the frequency of the
clock input. This behavior, in essence is captured by the binary bit pattern in the counting
sequence
Asynchronous 4 Bit Binary Counter:
Page 32

Asynchronous Decade Counters:
The binary counters previously introduced have two to the power n states. But
counters with states less than this number are also possible. They are designed to have the
number of states in their sequences, which are called truncated sequences. These
sequences are achieved by forcing the counter to recycle before going through all of its
normal states. A common modulus for counters with truncated sequences is ten. A
counter with ten states in its sequence is called a decade counter.
Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice
that only Q1 and Q3 are used to decode the count of ten. This is called partial decoding,
as none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.
Page 33

Truth Table:
Procedure:
2. The input clock pulse is applied from digital trainer and the corresponding output is
checked through LEDs.
Inference:
Result:
Viva Questions:
1.
2.
3.
4.
5.
6.
What is mean by counter?

What is mean by synchronous and asynchronous counter?
What is mean by decade counter?
What is mean by binary counter?
What is the difference between the counting sequences of up and down counter?
Give the advantages and disadvantages of a synchronous counter over an
asynchronous counter?
7. What is the difference between combinational logic and sequential logic?
8. How many flip-flops are required to construct a decade counter?
9. The terminal count of a typical modulus-10 binary counter is ________.
10. To operate correctly, starting a ring counter requires ______________.
Page 34

Experiment: 5
DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT REGISTERS
Aim:
To design, construct and test the following types of shift registers
1. 4 bit Serial in Serial out Shift Register
2. 4 bit Serial in Parallel out Shift Register
3. 4 bit Parallel in Parallel out Shift Register
4. 4 bit Parallel in Serial out Shift Register
Apparatus Required:
S.No
1.
2.
3.
4.
6.
7.
8.
9.
10.
11.
12.
Component Name
AND Gate
OR Gate
Not Gate
NAND Gate
Flip Flop
Trainer kit
Bread Board
Connecting wires
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7400
IC 7474
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
2
1
1
As Req.
As Req.
1
As Req.
Theory:
Shift registers, like counters, are a form of sequential logic. Sequential logic,
unlike combinational logic is not only affected by the present inputs, but also, by the
prior history. In other words, sequential logic remembers past events. Shift registers
produce a discrete delay of a digital signal or waveform. A waveform synchronized to a
clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the
number of shift register stages. Thus, a four stage shift register delays "data in" by four
clocks to "data out". The stages in a shift register are delay stages, typically type "D"
Flip-Flops or type "JK" Flip-flops.
Page 35

Formerly, very long (several hundred stages) shift registers served as digital
memory. This obsolete application is reminiscent of the acoustic mercury delay lines
used as early computer memory. Serial data transmission, over a distance of meters to
kilometers, uses shift registers to convert parallel data to serial form. Serial data
communications replaces many slow parallel data wires with a single serial high speed
circuit.
Serial data over shorter distances of tens of centimeters, uses shift registers to get
data into and out of microprocessors. Numerous peripherals, including analog to digital
converters, digital to analog converters, display drivers, and memory, use shift registers
to reduce the amount of wiring in circuit boards. Some specialized counter circuits
actually use shift registers to generate repeating waveforms. Longer shift registers, with
the help of feedback generate patterns so long that they look like random noise, pseudonoise.
Basic shift registers are classified by structure according to the following types:
Serial-in/serial-out
Parallel-in/serial-out
Serial-in/parallel-out
Universal parallel-in/parallel-out
Above we show a block diagram of a serial-in/serial-out shift register, which is 4stages long. Data at the input will be delayed by four clock periods from the input to the
output of the shift register. Data at "data in", above, will be present at the Stage A output
after the first clock pulse. After the second pulse stage A data is transfered to stage B
Page 36

output, and "data in" is transfered to stage A output. After the third clock, stage C is
replaced by stage B; stage B is replaced by stage A; and stage A is replaced by "data in".
After the fourth clock, the data originally present at "data in" is at stage D, "output". The
"first in" data is "first out" as it is shifted from "data in" to "data out".
Data is loaded into all stages at once of a parallel-in/serial-out shift register. The
data is then shifted out via "data out" by clock pulses. Since a 4- stage shift register is
shown above, four clock pulses are required to shift out all of the data. In the diagram
above, stage D data will be present at the "data out" up until the first clock pulse; stage C
data will be present at "data out" between the first clock and the second clock pulse; stage
B data will be present between the second clock and the third clock; and stage A data will
be present between the third and the fourth clock. After the fourth clock pulse and
thereafter, successive bits of "data in" should appear at "data out" of the shift register
after a delay of four clock pulses.
If four switches were connected to DA through DD, the status could be read into a
microprocessor using only one data pin and a clock pin. Since adding more switches
would require no additional pins, this approach looks attractive for many inputs.
Page 37

Above, four data bits will be shifted in from "data in" by four clock pulses and be
available at QA through QD for driving external circuitry such as LEDs, lamps, relay
drivers, and horns. After the first clock, the data at "data in" appears at QA. After the
second clock, The old QA data appears at QB; QA receives next data from "data in". After
the third clock, QB data is at QC. After the fourth clock, QC data is at QD. This stage
contains the data first present at "data in". The shift register should now contain four data
bits.
A parallel-in/parallel-out shift register combines the function of the parallel-in,

serial-out shift register with the function of the serial-in, parallel-out shift register to
yields the universal shift register. The "do anything" shifter comes at a price the
increased number of I/O (Input/Output) pins may reduce the number of stages which can
be packaged. Data presented at DA through DD is parallel loaded into the registers. This
data at QA through QD may be shifted by the number of pulses presented at the clock
input. The shifted data is available at QA through QD. The "mode" input, which may be
more than one input, controls parallel loading of data from D A through DD, shifting of
data, and the direction of shifting. There are shift registers which will shift data either left
or right.
Page 38

Serial-in/serial-out shift register:
Serial-in, serial-out shift registers delay data by one clock time for each stage.
They will store a bit of data for each register. A serial-in, serial-out shift register may be
one to 64 bits in length, longer if registers or packages are cascaded. Below is a single
stage shift register receiving data which is not synchronized to the register clock. The
"data in" at the D pin of the type D FF (Flip-Flop) does not change levels when the clock
changes for low to high. We may want to synchronize the data to a system wide clock in
a circuit board to improve the reliability of a digital logic circuit.
The obvious point (as compared to the figure below) illustrated above is that
whatever "data in" is present at the D pin of a type D FF is transfered from D to output Q
at clock time. Since our example shift register uses positive edge sensitive storage
elements, the output Q follows the D input when the clock transitions from low to high as
shown by the up arrows on the diagram above. There is no doubt what logic level is
present at clock time because the data is stable well before and after the clock edge. This
is seldom the case in multi-stage shift registers. But, this was an easy example to start
with. We are only concerned with the positive, low to high, clock edge. The falling edge
can be ignored. It is very easy to see Q follow D at clock time above. Compare this to the
diagram below where the "data in" appears to change with the positive clock edge.
Page 39
Since "data in" appears to changes at clock time t 1 above, what does the type D
FF see at clock time? The short over simplified answer is that it sees the data that was
present at D prior to the clock. That is what transfered to Q at clock time t1 is. The
correct waveform is QC. At t1 Q goes to a zero if it is not already zero. The D register
does not see a one until time t2, at which time Q goes high.
Since data, above, present at D is clocked to Q at clock time, and Q cannot

change until the next clock time, the D FF delays data by one clock period, provided that
the data is already synchronized to the clock. The Q A waveform is the same as "data in"
with a one clock period delay. A more detailed look at what the input of the type D FlipFlop sees at clock time follows. Refer to the figure below. Since "data in" appears to
changes at clock time (above), we need further information to determine what the D FF
sees. If the "data in" is from another shift register stage, another same type D FF, we can
draw some conclusions based on data sheet information. Manufacturers of digital logic
make available information about their parts in data sheets, formerly only available in a
collection called a data book. Data books are still available; though, the manufacturer's
web site is the modern source.
Page 40
Three type D Flip-Flops are cascaded Q to D and the clocks paralleled to form a
three stage shift register above.
Type JK FFs cascaded Q to J, Q' to K with clocks in parallel to yield an alternate

form of the shift register above. A serial-in/serial-out shift register has a clock input, a
data input, and a data output from the last stage. In general, the other stage outputs are not
available otherwise; it would be a serial-in, parallel-out shift register. The waveforms
below are applicable to either one of the preceding two versions of the serial-in, serial-out
shift register. The three pairs of arrows show that a three stage shift register temporarily
stores 3-bits of data and delays it by three clock periods from input to output.
Page 41

At clock time t1 a "data in" of 0 is clocked from D to Q of all three stages. In
particular, D of stage A sees a logic 0, which is clocked to QA where it remains until time
t2. At clock time t2 a "data in" of 1 is clocked from D to QA. At stages B and C, a 0, fed
from preceding stages is clocked to QB and QC. At clock time t3 a "data in" of 0 is
clocked from D to QA. QA goes low and stays low for the remaining clocks due to "data
in" being 0. QB goes high at t3 due to a 1 from the previous stage. QC is still low after t3
due to a low from the previous stage. QC finally goes high at clock t 4 due to the high fed
to D from the previous stage QB. All earlier stages have 0s shifted into them. And, after
the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s
Parallel-in, Serial-out Shift Register:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/
serial-out shift registers do plus input data to all stages simultaneously. The parallel-in/
serial-out shift register stores data, shifts it on a clock by clock basis, and delays it by the
number of stages times the clock period. In addition, parallel-in/ serial-out really means
that we can load data in parallel into all stages before any shifting ever begins. This is a
way to convert data from a parallel format to a serial format. By parallel format we mean
that the data bits are present simultaneously on individual wires, one for each data bit as
shown below. By serial format we mean that the data bits are presented sequentially in
time on a single wire or circuit as in the case of the "data out" on the block diagram
below.
Below we take a close look at the internal details of a 3-stage parallel-in/ serialout shift register. A stage consists of a type D Flip-Flop for storage, and an AND-OR
Page 42

selector to determine whether data will load in parallel, or shift stored data to the right. In
general, these elements will be replicated for the number of stages required. We show
three stages due to space limitations. Four, eight or sixteen bits is normal for real parts.
Above we show the parallel load path when SHIFT/LD' is logic low. The upper
NAND gates serving DA DB DC are enabled, passing data to the D inputs of type D FlipFlops QA QB DC respectively. At the next positive going clock edge, the data will be
clocked from D to Q of the three FFs. Three bits of data will load into QA QB DC at the
same time. The type of parallel load just described, where the data loads on a clock pulse
is known as synchronous load because the loading of data is synchronized to the clock.
This needs to be differentiated from asynchronous load where loading is controlled by
the preset and clear pins of the Flip-Flops which does not require the clock. Only one of
these load methods is used within an individual device, the synchronous load being more
common in newer devices.
Page 43

The shift path is shown above when SHIFT/LD' is logic high. The lower AND
gates of the pairs feeding the OR gate are enabled giving us a shift register connection of
SI to DA , QA to DB , QB to DC , QC to SO. Clock pulses will cause data to be right shifted
out to So on successive pulses. The waveforms below show both parallel loading of three
bits of data and serial shifting of this data. Parallel data at DA DB DC is converted to serial
data at SO.
What we previously described with words for parallel loading and shifting is now
set down as waveforms above. As an example we present 101 to the parallel inputs DAA
DBB DCC. Next, the SHIFT/LD' goes low enabling loading of data as opposed to shifting
of data. It needs to be low a short time before and after the clock pulse due to setup and
hold requirements. It is considerably wider than it has to be. Though, with synchronous
logic it is convenient to make it wide. We could have made the active low SHIFT/LD'
almost two clocks wide, low almost a clock before t 1 and back high just before t3. The
important factor is that it needs to be low around clock time t 1 to enable parallel loading
of the data by the clock. Note that at t 1 the data 101 at DA DB DC is clocked from D to Q
of the Flip-Flops as shown at QA QB QC at time t1. This is the parallel loading of the data
synchronous with the clock.
Page 44
Now that the data is loaded, we may shift it provided that SHIFT/LD' is high to
enable shifting, which it is prior to t 2. At t2 the data 0 at QC is shifted out of SO which is
the same as the QC waveform. It is either shifted into another integrated circuit, or lost if
there is nothing connected to SO. The data at QB, a 0 is shifted to QC. The 1 at QA is
shifted into QB. With "data in" a 0, QA becomes 0. After t2, QA QB QC = 010. After t3, QA
QB QC = 001. This 1, which was originally present at QA after t1, is now present at SO
and QC. The last data bit is shifted out to an external integrated circuit if it exists. After t 4
all data from the parallel load is gone. At clock t 5 we show the shifting in of a data 1
present on the SI, serial input. Why provide SI and SO pins on a shift register? These
connections allow us to cascade shift register stages to provide large shifters than
available in a single IC (Integrated Circuit) package. They also allow serial connections
to and from other ICs like microprocessors.
Serial-in, Parallel-out Shift Register:
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift
register in that it shifts data into internal storage elements and shifts data out at the serialout, data-out, pin. It is different in that it makes all the internal stages available as
outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format
to parallel format. If four data bits are shifted in by four clock pulses via a single wire at
data-in, below, the data becomes available simultaneously on the four Outputs QA to QD
after the fourth clock pulse.
Page 45
The practical application of the serial-in/parallel-out shift register is to convert data from
serial format on a single wire to parallel format on multiple wires. Perhaps, we will
illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD ).
The above details of the serial-in/parallel-out shift register are fairly simple. It
looks like a serial-in/ serial-out shift register with taps added to each stage output. Serial
data shifts in at SI (Serial Input). After a number of clocks equal to the number of stages,
the first data bit in appears at SO (QD) in the above figure. In general, there is no SO pin.
The last stage (QD above) serves as SO and is cascaded to the next package if it exists.
If a serial-in/parallel-out shift register is so similar to a serial-in/ serial-out shift
register, why do manufacturers bother to offer both types? Why not just offer the serialin/parallel-out shift register? They actually only offer the serial-in/parallel-out shift
register, as long as it has no more than 8-bits. Note that serial-in/ serial-out shift registers
come in gigger than 8-bit lengths of 18 to to 64-bits. It is not practical to offer a 64-bit
Page 46

serial-in/parallel-out shift register requiring that many output pins. See waveforms below
for above shift register.
The shift register has been cleared prior to any data by CLR', an active low
signal, which clears all type D Flip-Flops within the shift register. Note the serial data
1011 pattern presented at the SI input. This data is synchronized with the clock CLK.
This would be the case if it is being shifted in from something like another shift register,
for example, a parallel-in/ serial-out shift register (not shown here). On the first clock at
t1, the data 1 at SI is shifted from D to Q of the first shift register stage. After t2 this first
data bit is at QB. After t3 it is at QC. After t4 it is at QD. Four clock pulses have shifted
the first data bit all the way to the last stage QD. The second data bit a 0 is at QC after the
4th clock. The third data bit a 1 is at QB. The fourth data bit another 1 is at QA. Thus, the
serial data input pattern 1011 is contained in (QD QC QB QA). It is now available on the
Page 47

four outputs. It will available on the four outputs from just after clock t4 to just before t5.
This parallel data must be used or stored between these two times, or it will be lost due to
shifting out the QD stage on following clocks t5 to t8 as shown above.
Parallel-in, Parallel-out or Universal Shift Register:
The purpose of the parallel-in/ parallel-out shift register is to take in parallel data,
shift it, then output it as shown below. A universal shift register is a do-everything device
in addition to the parallel-in/ parallel-out function.
Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA

DB DC DD. The mode control, which may be multiple inputs, controls parallel loading vs.
shifting. The mode control may also control the direction of shifting in some real devices.
The data will be shifted one bit position for each clock pulse. The shifted data is available
at the outputs QA QB QC QD . The "data in" and "data out" are provided for cascading of
multiple stages. Though, above, we can only cascade data for right shifting. We could
accommodate cascading of left-shift data by adding a pair of left pointing signals, "data
in" and "data out", above. The internal details of a right shifting parallel-in/ parallel-out
shift register are shown below. The tri-state buffers are not strictly necessary to the
parallel-in/ parallel-out shift register, but are part of the real-world device shown below.
Page 48
The 74LS395 so closely matches our concept of a hypothetical right shifting

parallel-in/ parallel-out shift register that we use an overly simplified version of the data
sheet details above. See the link to the full data sheet more more details, later in this
chapter. LD/SH' controls the AND-OR multiplexer at the data input to the FF's. If
LD/SH'=1, the upper four AND gates are enabled allowing application of parallel inputs
DA DB DC DD to the four FF data inputs. Note the inverter bubble at the clock input of the
four FFs. This indicates that the 74LS395 clocks data on the negative going clock, which
is the high to low transition. The four bits of data will be clocked in parallel from DA DB
DC DD to QA QB QC QD at the next negative going clock. In this "real part", OC' must be
low if the data needs to be available at the actual output pins as opposed to only on the
internal FFs.The previously loaded data may be shifted right by one bit position if
LD/SH'=0 for the succeeding negative going clock edges. Four clocks would shift the
data entirely out of our 4-bit shift register. The data would be lost unless our device was
cascaded from QD' to SER of another device.
Page 49

Above, a data pattern is presented to inputs DA DB DC DD. The pattern is loaded to
QA QB QC QD . Then it is shifted one bit to the right. The incoming data is indicated by
X, meaning the we do no know what it is. If the input (SER) were grounded, for
example, we would know what data (0) was shifted in. Also shown, is right shifting by
two positions, requiring two clocks.
The above figure serves as a reference for the hardware involved in right shifting of data.
It is too simple to even bother with this figure, except for comparison to more complex
figures to follow.
Right shifting of data is provided above for reference to the previous right shifter.
If we need to shift left, the FFs need to be rewired. Compare to the previous right
shifter. Also, SI and SO have been reversed. SI shifts to QC. QC shifts to QB. QB shifts to
QA. QA leaves on the SO connection, where it could cascade to another shifter SI. This
left shift sequence is backwards from the right shift sequence.
Page 50
Above we shift the same data pattern left by one bit. There is one problem with the "shift
left" figure above. There is no market for it. Nobody manufactures a shift-left part. A
"real device" which shifts one direction can be wired externally to shift the other
direction. Or, should we say there is no left or right in the context of a device which shifts
in only one direction. However, there is a market for a device which will shift left or right
on command by a control line. Of course, left and right are valid in that context.
What we have above is a hypothetical shift register capable of shifting either

direction under the control of L'/R. It is setup with L'/R=1 to shift the normal direction,
right. L'/R=1 enables the multiplexer AND gates labeled R. This allows data to follow
the path illustrated by the arrows, when a clock is applied. The connection path is the
same as the too simple" "shift right" figure above. Data shifts in at SR, to QA, to QB, to
QC, where it leaves at SR cascade. This pin could drive SR of another device to the right.
What if we change L'/R to L'/R=0?
Page 51
With L'/R=0, the multiplexer AND gates labeled L are enabled, yielding a path, shown
by the arrows, the same as the above "shift left" figure. Data shifts in at SL, to QC, to QB,
to QA, where it leaves at SL cascade. This pin could drive SL of another device to the
left. The prime virtue of the above two figures illustrating the "shift left/ right register" is
simplicity. The operation of the left right control L'/R=0 is easy to follow. A commercial
part needs the parallel data loading implied by the section title. This appears in the figure
below.
Now that we can shift both left and right via L'/R, let us add SH/LD', shift/ load,
and the AND gates labeled "load" to provide for parallel loading of data from inputs D A
DB DC. When SH/LD'=0, AND gates R and L are disabled, AND gates "load" are
Page 52

enabled to pass data DA DB DC to the FF data inputs. the next clock CLK will clock the
data to QA QB QC. As long as the same data is present it will be re-loaded on succeeding
clocks. However, data present for only one clock will be lost from the outputs when it is
no longer present on the data inputs. One solution is to load the data on one clock, then
proceed to shift on the next four clocks. This problem is remedied in the 74ALS299 by
the addition of another AND gate to the multiplexer. If SH/LD' is changed to SH/LD'=1,
the AND gates labeled "load" are disabled, allowing the left/ right control L'/R to set the
direction of shift on the L or R AND gates. Shifting is as in the previous figures.
The only thing needed to produce a viable integrated device is to add the fourth AND
gate to the multiplexer as alluded for the 74ALS299. This is shown in the next section for
that part.
PIN Diagram
Page 53

Procedure:
2. The input clock pulses are applied from digital trainer and the corresponding output is
Inference:
Result:
Viva Questions:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
What is mean by shift register?

What are the qualitative differences between parallel loading and serial
loading shift register?
How can a serial in / parallel out register be used as a serial in/ serial out
register?
What is mean by parallel in/ parallel out register?
What is mean by serial in /serial out register?
What is mean by parallel data transfer?
What is a shift register that will accept a parallel input, or a bidirectional
serial load and internal shift features, called?
What is meant by parallel load of a shift register?
What is the difference between a ring shift counter and a Johnson shift
counter?
What is the difference between a shift-right register and a shift-left
register?
Page 54

Experiment: 6
STUDY AND DESIGN OF 4 :1 & 8 :1 MULTIPLEXER AND DEMULTIPLEXER
Aim:
To design
1. 4:1 and 8:1 Multiplexer
2. 1:4 and 1:8 Demultiplexer
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
Component Name
AND Gate
OR Gate
Not Gate
NAND Gate
Bread Board
Connecting wires
Part No/Range
IC 7408
IC 7432
IC 7404
IC 7400
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
1
As Req.
As Req.
1
As Req.
Theory:
Multiplexer:
Multiplexing is defined as the process of feeding several independent signals to a
common load, one at a time. The device or switching circuitry used to select and connect
one of these several signals to the load at any one time is known as a multiplexer.
A multiplexer is a combinatorial circuit that is given a certain number (usually a
power of two) data inputs, let us say 2n, and n address inputs used as a binary number to
select one of the data inputs. The multiplexer has a single output, which has the same
value as the selected data input. The multiplexer works like the input selector of a home
music system. Only one input is selected at a time, and the selected input is transmitted to
the single output. Here is such an abbreviated truth table for n = 3. The full truth table
would have 2(3 + 23) = 2048 rows.
Page 55

4:1 Multiplexer
Page 56

8:1 Multiplexer
De Multiplexer:
The process of feeding several independent loads with signals coming
from a common signal source, one at a time. A device used for de-multiplexing is known
as a de-multiplexer the de-multiplexer circuit takes a single data input and one or more
address inputs, and selects which of multiple outputs will receive the input signal. The
address input determine which data output is going to have the same value as the data
input. The other data outputs will have the value 0.
Page 57

1:4 Demultiplexer
1:8 Demultiplexer
Page 58

Procedure:
2. The input clock pulses are applied from digital trainer and the corresponding output is
Inference:
Result:
Viva Questions:
1. What is mean by multiplexer?
2. What is the another name of multiplexer and why we are calling it as like that?
3. What are the applications of multiplexer?
4. Write the truth table for 4 input multiplexer
5. What is meant by multiplexing?
6. What is meant by demultiplexer?
7. What is the another name of demultiplexer?
8. What are the applications of Demultiplexer?
9. What is mean by clock demultiplexer?
10. How can we construct 2n to 1 multiplexer from an n to 2n decoder?
Page 59

Experiment: 7
MONOSTABLE AND ASTABLE MULTIVIBRATOR USING 555 TIMER
Aim:
1.To study and testing of Astable Multivibrator operation using NE/SE 555 Timer
2.To study and testing of Monostable Multivibrator operation using NE/SE 555 Timer
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
Component Name
Timer IC
Bread Board
DRB
DCB
Connecting wires
Function Generator
Part No/Range
NE/SE 555
(0-30V)
-
330 ohm
-
Quantity in Nos
1
1
1
As Req.
1
1
As Req.
As Req.
1
Theory:
555 Timer IC
The 555 timer IC was first introduced around 1971 by the Signetics Corporation
as the SE555/NE555 and was called "The IC Time Machine" and was also the very first
and only commercial timer IC available. It provided circuit designers with a relatively
cheap, stable, and user-friendly integrated circuit for both monostable and astable
applications. The 555 contains more than 28 transistors and it is basically a chip
containing a number of building blocks that end up very similar to an oscillator without
the TIMING COMPONENTS. It needs two or three external components to produce an
oscillator capable of operating at a frequency from 1Hz to 500 kHz. When it oscillates at
a frequency less than 1Hz, the circuit is called a Timer or Delay. . It can be used with any
power supply in the range 5-18 volts, thus it is useful in many analog circuits. When
connected to a 5-volt supply, the circuit is directly compatible with TTL or CMOS digital
devices.
Page 60
Description of Functional Block Diagram:

Referring to the functional diagram (Fig. 2.2), three 5k resistors act as a voltage
divider, providing bias voltage of 2/3 V cc to the upper comparator and 1/3 V cc to the
lower comparator, where Vcc is the activation supply voltage to the 555 timer. These two
voltages are used to fix the threshold voltage for the two comparators and aid to
determine time interval. The time interval can be varied by giving voltage to control
voltage terminal (pin 5). In actual application, where no such input voltage is given to
Page 61

control voltage terminal, a capacitor (0.01F) will be connected between control
voltage terminal (pin 5) and ground to bypass noise or ripple from the supply.
In standby (stable state), the output Q of the control flip flop (FF) is at logic one
(HIGH). This makes the output (pin 3) logic zero (LOW) because the power
amplifier is basically an inverting amplifier.
Triggering is accomplished by taking the pin 2 from above to below a voltage

level of 1/3 Vcc. The action of the trigger input is level-sensitive, allowing slow
rate-of-change waveforms, as well as pulses, to be used as trigger sources. The
trigger pulse must be of shorter duration than the time interval determined by the
external R and C.
When the trigger input is slightly lower than 1/3 Vcc, the lower comparator
output goes to positive saturation which in turn it sets the control flip flop. The
flip flop will be in set state i.e. Q= logic one (HIGH) and Q =logic zero (LOW).
Then the output of timer will be at logic one(HIGH)
Applying a positive trigger at the Threshold terminal (pin 6), when the voltage is
slightly higher than 2/3 Vcc, the upper comparator goes to positive saturation
which in turn resets the control flip flop. The flip flop goes to reset state i.e. Q=
logic zero (LOW) and Q = logic one (HIGH). Then the output of timer will be
logic zero (LOW)
The reset input (pin 4) provides a mechanism to reset the Control flip flop in a
manner which overrides the effect of any instruction coming to control flip flop from
lower comparator. This overriding reset is effective when the reset input is less than
about 0.4V. When this reset is not used, it is returned to Vcc. the transistor T2 serves as a
buffer to isolate the reset input from the control flip flop and transistor T1. The transistor
T2 is driven by an internal voltage Vref obtained from supply voltage Vcc.
Page 62

Monostable Operation:
In the standby (stable) state, control flip flop holds transistor T1 ON, thus
clamping the external timing capacitor C to ground.
The output remains at
ground potential, i.e., LOW.
As the trigger in Fig. 2.3(a) passes through Vcc/3(i.e. trigger input is slightly
lesser than 1/3 Vcc), the lower comparator is triggered to positive saturation and
the control flip flop is set, i.e. Q= logic one (HIGH) and Q =logic zero (LOW).
This makes the transistor T1 OFF and the short circuit across the timing capacitor
C is released.
As Q is LOW, output (pin 3) goes HIGH (=Vcc). The timing cycle now begins.
Since C is unclamped, voltage across it rises exponentially through R towards
Vcc with a time constant RC as in Fig. 2.3(b)
After a time period T, the capacitor voltage is just greater than 2/3V cc (which is
applied in pin 6) and the upper comparator is triggered to positive saturation,
and resets the control flip flop(R=1, S=0) that is, Q= logic zero (LOW) and Q =
Page 63

logic one (HIGH)(assuming very small trigger pulse width).
This makes
transistor T1 go ON (i.e. saturates), thereby discharging the capacitor C rapidly to

ground potential. The output returns to the standby state or ground potential as
shown in Fig. 2.3(c) .
The voltage across the capacitor as in Fig is given by
vc Vcc (1 e
t
RC
At t =T,
2
vc Vcc
3
Therefore,
2
Vcc Vcc (1 e RC )
3
0.66 1 e
T
RC
ln( 0.33) ln( e
T
RC
) (
Or,
T = RC ln(0.33)
Or,
T = 1.09 RC (seconds)
T
T
)
RC
RC
Page 64

From the above equation it is evident that timing interval is independent of the
supply voltage. It may also be noted that once triggered, the output remains in the HIGH
state until time T elapses, which depends only upon R and C. Any additional trigger pulse
coming during this time will not change the output state.
However, if a negative going reset pulse as in Fig. 2.4(d) is applied to the reset terminal
(pin-4) during the timing cycle, transistor T2 goes OFF, T1 becomes ON and the external
timing capacitor C is immediately discharged. The output now will be as in Fig. 2.4(c)
with doted lines. It may be seen that the output of T2 is connected directly to the input of
T1 so as to turn ON T1 immediately and thereby avoid the propagation delay through the
FF. Now, even if the reset is released, the output will still remain LOW until a negative
going trigger pulse is again applied at pin2.
Astable Operation:
The timing resistor is split into two sections Ra and Rb. Pin 7 of discharging
transistor T1 is connected to the junction of Ra and Rb.
When the power supply Vcc is connected, the external timing capacitor C charges
towards Vcc with a time constant (Ra + Rb)C.
During this time, the lower
comparator will be in positive saturation which in tern sets the control flip flop
(i.e. Reset R=0, Set S=1), this makes Q =0 Output (pin 3) goes high (equals Vcc),
which has unclamped the timing capacitor C.
Page 65
When the capacitor voltage is just greater than (2/3)Vcc the upper comparator
triggers to positive saturation and resets the control flip flop(i.e. Reset R=1, Set
S=0) so that Q =1. This in turn, makes transistor T1 on and capacitor C starts
discharging towards ground through Rb and transistor T1 with a time constant RbC
(neglecting the forward resistance of T1).
Current also flows into transistor T1 through Ra. Resistors Ra and Rb must be
large enough to limit this current and prevent damage to the discharge transistor
T1.
The minimum value of Ra is approximately equal to Vcc/0.2 where 0.2A is the
maximum current through the on transistor T1.
During the discharge of the timing capacitor C, as it reaches just less than) Vcc/3,
the lower comparator is triggered and sets the control flip flop (i.e. Reset R=0,
Set S=1), which turns Q =0.
Now Q =0 unclamps the external timing capacitor C.
The capacitor C is thus periodically charged and discharged between (2/3) Vcc and
(1/3) Vcc respectively.
Fig. 2.6 shows the timing sequence and capacitor voltage waveform. The time duration
for which the output remains HIGH is the time taken by the capacitor to charge from
(1/3) Vcc to (2/3) Vcc. This may be calculated as follows:
Let Ra+Rb=R
The capacitor voltage for a low pass RC circuit subjected to a step input of V cc volts is
given by
vc Vcc (1 e
t
RC
The time ta taken by the circuit to charge from 0 to 2/3 Vcc is
2
V cc V cc ( 1 e
3
0 . 66
(1
t a
RC
ln( 0 . 33 ) ln( e
ta
RC
ta
RC
ta
RC
Page 66

t a 1.09 RC
and time tb is to change from 0 to 1/3Vcc is,
1
V cc V cc ( 1 e
3
tb
RC
tb=0.405RC.
Or,
So the time to change from 1/3 Vcc to 2/3 Vcc is
t1 = ta-tb
t 1 1.09RC - 0.405RC 0.69RC 0.69(R a Rb )C
The output is low while capacitor is discharging from (2/3)Vcc to (1/3)Vcc through the
resistor Rb and the voltage across the capacitor is given by
1
V
3
cc
V
3
cc
(1 e
t
R
2
b
By solving we get t 2 0.69Rb C

The charging path of the capacitor is through Ra and Rb and discharging is only through
Rb. Therefore total time,
T = t1+t2
T = 0.69(Ra+2Rb)C
1.45
( Ra 2Rb )C
The duty cycle defined here as the ratio of the time the output is low as compared to the
total time period
Duty cycle =
t2
Rb
T R a 2R b
Duty cycle %=
Rb
100
R a 2R b
The duty cycle is always less than 50% in other words, the off time t2 is always
less than the ON time t1. Thus the output of the 555 astable circuit is asymmetric. By
making Rb large compared to Ra,(i.e. Ra=minimum) the waveform becomes more
symmetric and the 555 output approaches a square wave. If Ra is very small, the pin 7 will
be connected to Vcc through a very low resistance and extra current flows through T1
Page 67

when it is ON. This may damage the transistor T1 and hence the timer. To avoid this, a
diode can be connected across the resistance Rb in forward bias.
Procedure:
1. The connections are given as per the given circuit diagrams (Fig. 2.3 and Fig 2.5)
drawn as per the design values.
2. The values of Vcc = 5V, R =5k (use decade resistance box) and C=0.1F (use
decade capacitance box) are set.
3. Appropriate Trigger input (400 Hz, 5V p-p, square wave) is applied from the
signal generator for monostable operation.
4. The output signals from Pin no.3 and pin no.6 (voltage across the capacitor) are
observed using a CRO and the frequency and amplitude (p-p) of the output
waveforms are recorded.
5. The output waveforms are plotted under same scale.
Inference:
Result:
Viva Questions:
1.
2.
3.
4.
5.
6.
7.
What is mean by astable multivibrator?

What is mean by duty cycle?
What are the types of astable multivibrator?
Write the equation for time intervals present in an astable multivibrator.
What is the another name of astable multivibrator?
What is mean by monostable multivibrator?
What is the difference between an astable multivibrator and a monostable
multivibrator?
8. What is the another name of monostable multivibrator?
9. What are the types of monostable multivibrator?
10. What is mean by quasi-stable state?
Page 68

Experiment No: 8
APPLICATION OF OPERATIONAL AMPLIFIERS
Aim:
To design, construct and test the following Op-Amp applications.
(a) Inverting Amplifier
(b) Non-inverting Amplifier
(c) Adder
(d) Comparator
(e) Integrator
(f) Differentiator.
Apparatus required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Component Name
Op amp IC
Connecting wires
Bread Board
Cathode Ray Tube
Resister
Resister
Resister
Capacitor
Function Generator
Part No/Range
IC 741
(0-30V)
(0-20MHz)
10K
1K
10K,1.5K159
0.1uf,0.01uf
1-1MHz
Quantity in Nos
1
2
As Req.
1
1
3
2
Each one
Each one
1
Theory:
Ideal op-amp characteristics
Infinite open-loop voltage gain
Infinite input impedance
Zero output impedance
Zero noise contribution
Zero DC output offset
Infinite bandwidth
Differential inputs that stick together
Page 69

Inverting Amplifier:
The op-amp is connected using two resistors R1 and Rf such that the input signal
is applied in series with R1 and the output is connected back to the inverting input
through Rf. The non-inverting input is connected to the ground or the center tap of the
dual polarity power supply. In operation, as the input signal moves positive, the output
will move negative and vice versa. The amount of voltage change at the output relative to
the input depends on the ratio of the two resistors R1 and Rf.
Since the input resistance is infinite, current through R1 will be equal to the current
through Rf. Assuming that the op-amp is an ideal one, then Vd = 0 and node a is at
ground potential.
Current through R1 and Rf is given by
Output voltage, Vout i1 R f Vin
i1
vin
R1
Rf
R1
Hence the closed loop gain of the inverting amplifier is, Acl
Alternatively, the node equation at node a is
Rf
Vout
Vin
R1
Va Vin Va Vout
0
R1
Rf
Where Va is the voltage at node a. Since node a is at virtual ground, Va=0. Therefore
by rearranging the above equation the closed loop gain can be written as
Acl
Rf
Rf
Vout
. The output voltage is Vout Vin
Vin
R1
R1
Page 70

The negative sign indicates a Phase shift of 180 between Vin and Vout. Also inverting
input is at virtual ground, the effective input impedance is R1.
Non-inverting Amplifier:
The non-inverting amplifier is connected so that the input signal goes directly to
the non-inverting input (+) and the input resistor R1 is grounded. In this configuration, the
input impedance as seen by the signal is much greater since the input will be following
the applied signal and not held constant by the feedback current. As the signal moves in
either direction, the output will follow in phase to maintain the inverting input at the same
voltage as the input (+). The voltage gain is always more than unity.
Analysis:
As the difference voltage Vd is zero, the voltage at node A is Vin, same as the iput
voltage applied to non-inverting terminal. Now, Rf and R1 forms a potential divider.
Hence Vin
Vout
R1 , as no current flow through the op-amp,
R1 R f
Rf
Vout R1 R f
1
Acl . Where Acl is closed loop voltage gain of the non-inverting
Vin
R1
R1
Rf
Vin .
operational amplifier. Hence output voltage Vout 1
R
1
Page 71

Summing Amplifier or Adder Circuit:
Inverting Summing Amplifier:

Operational amplifiers are used to design a circuit whose output is sum of several
inputs. Such a circuit is called Summing amplifier or Adder Circuit or summer.
Analysis:
Assume the op-amp is ideal one (Fig.8.3) i.e. a virtual ground exists at the
inverting input, Input resistance Ri is infinite and input current is zero. Hence current
through Rf can be obtained by applying KCL at node A
R
R
V1 V2 Vout
0 . Hence, output voltage Vout= 3 V1 3 V 2 . Thus the output is an

R2
R1 R2 R3
R1
inverted, weighted sum of the input the inputs. When R1= R2= R3, we have Vout=(V1+V2) in this case the output Vo is the inverted sum of the input signal.
Let R1= R2= 2R3 then the output voltage Vout is the average of two input signals
V V2
(inverted) i.e. Vout 1
Page 72

Non-Inverting Summing Amplifier:
The summer that gives a non-inverting sum is the non-inverting summing
amplifier (Fig. 8.4). Let the voltage at the inverting input terminal is Va. The voltage at
non-inverting input terminal will also be Va. By applying KCL at node a we get
V1 V2
V1 Va V2 Va
R1 R2
0 . By solving Va we have Va
1
1
R1
R2
R1 R2
The op-amp and two resisters constitutes a non-inverting
R
amplifier with Vout 1 3 V a . Therefore the output voltage
R
V out
R 3
V1 V 2
R1 R 2 which is non-inverted weighted sum of inputs. Let R = R =

1
2
1
1
R1 R 2
R=R3/2, then Vout=V1+V2.
Comparator
Since the gain of the open loop amplifier is extremely high, the output of an opamp will be saturated fully positive, if the non-inverting input is more positive than the
inverting input, and saturated fully negative if the non-inverting input is less positive than
the inverting input. So an op-amp without feedback can be used to compare two different
Page 73

voltages. It compares two voltages and when one input exceeds the other in magnitude,
the states of output voltage will change.
In the circuit shown in the Fig. 8.7, we have an op-amp connected as a
comparator, comparing the input voltage with a reference voltage set by the
potentiometer (R2). If Vin drops below the reference voltage set by R2, the op-amp's
output will saturate to +V. Otherwise, if Vin is above the reference voltage, the op-amp's
output will saturate to -V. The output voltage would transition between opposing states of
saturation whenever the input voltage was equal to the reference voltage produced by the
potentiometer. The result would be a square wave. Fig. 8.8 and Fig. 8.9 show the output
of cooperator for positive and negative reference voltages.
Fig 3: Comparator
Page 74

Differentiator and Integrator
By introducing electrical reactance into the feedback loops of op-amp amplifier
circuits, we can cause the output to respond to changes in the input voltage over time.
Drawing their names from their respective calculus functions, the integrator produces a
voltage output proportional to the product (multiplication) of the input voltage and time;
and the differentiator (not to be confused with differential) produces a voltage output
proportional to the input voltage's rate of change. Capacitance can be defined as the
measure of a capacitor's opposition to changes in voltage. Capacitors oppose voltage its
ge change across it. i C
dv
. Capacitors oppose voltage change by creating current in
dt
the circuit: that is, they either charge or discharge in response to a change in applied
voltage. So, the more capacitance a capacitor has, the greater its charge or discharge
current will be for any given rate of voltage change across it.
dv
dt
Differentiator:
We can build an op-amp circuit (Fig. 1.5) which measures change in voltage by
measuring current through a capacitor, and outputs a voltage proportional to that current:
By referring the fig.1.5, the right-hand side of the capacitor is held to a voltage of
0 volts, due to the "virtual ground" effect. Therefore, current "through" the
capacitor is solely due to change in the input voltage.
A steady input voltage won't cause a current through C, but a changing input
voltage will.
Capacitor current moves through the feedback resistor, producing a drop across it,
which is the same as the output voltage.
A linear, positive rate of input voltage change will result in a steady negative
voltage at the output of the op-amp. Conversely, a linear, negative rate of input
voltage change will result in a steady positive voltage at the output of the op-amp.
This polarity inversion from input to output is due to the fact that the input signal
is being sent (essentially) to the inverting input of the op-amp.
Page 75

Analysis:
In the differentiator circuit (Fig. 1.5) node a is at virtual ground potential i.e.
Va=0the current ic through the capacitor is
ic C
d
vin va C dvin . The current if
dt
dt
through the feed back resistor is vout/R and there is no current into op-amp. Therefore
current at node a can be described by C
vout RC
dvin
dt
dvin vout
0 from this we have

dt
R
. Thus the output voltage vout is a constant(-RC) times the derivative of
the input voltage vin. the negative sign indicates a 1800 phase shift of the output
waveform with respect to input signal.
By taking laplace transform the output equation can be written as Vout(s)= -RCsVin(s).
V
f
substitute s=j and =2f then gain A out j 2fRC 2fRC
where
Vin
fa
fa
1
. Gain can be adjusted by changing frequency, resistor or capacitor.
2RC
Page 76

Differentiator Wave Forms:
Fig 4 :Input and output waveforms of Differentiator
Page 77

Integrator:
The op-amp circuit would generate an output voltage proportional to the
magnitude and duration that an input voltage signal has deviated from 0 volts. Stated
differently, a constant input signal would generate a certain rate of change in the output
voltage: differentiation in reverse i.e. integration. To do this a capacitor is connected in
feedback path along with an input resistor R1. The integrator circuit is shown in the Fig.
The negative feedback of the op-amp ensures that the inverting input will be held at 0
volts (the virtual ground).
If the input voltage is exactly 0 volts, there will be no current through the resistor,
therefore no charging of the capacitor, and therefore the output voltage will not
change.
We cannot guarantee what voltage will be at the output with respect to ground in
this condition, but we can say that the output voltage will be constant.
By applying a constant, positive voltage to the input, the op-amp output will fall
negative at a linear rate, in an attempt to produce the changing voltage across the
capacitor necessary to maintain the current established by the voltage difference
across the resistor. Conversely, a constant, negative voltage at the input results in
a linear, rising (positive) voltage at the output.
The output voltage rate-of-change will be proportional to the value of the input
voltage.
Page 78

Analysis:
In the circuit of Fig.1.6, nodal equation at node a is
t
integrating both sides, we get
dv
0
vin
dv
dv
v
C out 0 or out in
R
dt
dt
RC
out
vin dt
RC 0
t
1
vout (t )
vin (t )dt vout (0) .
RC 0
Where v0(0) is the initial output voltage. The output is -1/RC times the integral of input
and RC is the time constant of the integrator.
By taking laplace transform, the output equation becomes Vout ( s )
1
Vin ( s ) (assume
sRC
Initial voltage V0(0)=0). Substitute s=j and =2f and get the magnitude of the gain of
the integrator is A
Vout ( j )
1
1
. The gain of the integrator can be
Vin ( j )
jRC 2fRC
adjusted by changing frequency, resistor or capacitor

Integrator Wave Forms:
Page 79
Fig 3: Input and output waves forms of integrator

Procedure:
Inverting Amplifier:
1. Connections are made as per the circuit diagram drawn as per the design values.
2. The input sinusoidal signal with a particular frequency and amplitude (p-p) is
applied from a signal generator. Input signal frequency and amplitude (p-p) are
noted.
3. The output signal is observed using a CRO and the frequency and amplitude (p-p)
of the same are noted.
4. The gain for which the circuit is designed is verified by comparing the input and
output signals.
5. The input and output signals are plotted with same scale.
Non-inverting Amplifier:
2. The input sinusoidal signal with a particular frequency and amplitude (p-p) is
applied from a signal generator. Input signal frequency and amplitude (p-p) are
noted.
Page 80

3. The output signal is observed using a CRO and the frequency and amplitude (p-p)
of the same are noted.
4. The gain for which the circuit is designed is verified by comparing the input and
output signals.
5. The input and output signals are plotted with same scale.
Summing Amplifier:
2. The input D.C. voltages of appropriate values are applied from a D.C. power
supply and the values are also noted.
3. The output voltage is measured using a voltmeter / multi-meter and it is noted.
4. The output voltage is verified for validity by comparing the gain for which the
circuit is designed and input voltages
Comparator:
1. Connections are made as per the circuit diagram drawn.
2. The positive and negative reference voltages are applied to the non-inverting
terminal of the op-amp by adjusting the potentiometer.
3. A sinusoidal signal with a particular frequency and amplitude (p-p) is applied to
the inverting terminal of the op-amp from a signal generator. Input signal
frequency and amplitude (p-p) are noted.
4. The output signals are observed using a CRO and the frequency and amplitude
(p-p) of the output waveforms are recorded.
Differentiator and Integrator:
2. The input square wave with a particular frequency and amplitude (p-p) is applied
from a signal generator. Input signal frequency and amplitude (p-p) are noted.
3. The output signals are observed using a CRO and the frequency and amplitude (pp) of the output waveforms are recorded.
4. The output voltage is verified for validity.
Page 81
Inference:
Result:
Viva Questions:
1. What is an op-amp?
2. What are the characteristics of an ideal opamp?
3. What is mean by open loop and closed loop operation of an opamp?
4. What is the input impedance of a non-inverting op-amp amplifier?
5. Define common mode rejection ratio.
6. What is mean by slew rate?
7. What are the limitations of an ordinary op-amp differentiator?
8. What is the difference between the integrator and differentiator?
9. Why the integrators are preferred over differentiators in analog computer?
10. What are the difference between ac amplifiers and dc amplifiers?
Page 82

Experiment No: 9.a
DIGITAL TO ANALOG CONVERTER
Aim:
To design the following digital to analog converters and test their functionality by
conducting an experiment;
i) 4 bit weighted resistor type.
ii) 4 bit R-2R Ladder type.
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Component Name
Bread Board
Resistor
Op-Amp IC
CRO
Resistor
Resistor
Resistor
Function Generator
Connecting wires
Part No/Range
(0-30V)
8K
IC 741
4K
2K
1K
-
Quantity in Nos
1
1
1
1
1
1
6
5
1
As Req.
Theory:
Digital to Analog converters (DACs) are circuits that convert digital signal into
analog electrical quantities directly related to the digitally encoded input number. DACs
allow computer to communicate with analog world. The digital output from a process
computer cannot be used to directly to operate a valve that controls gas flow to a furnace.
But the output of a digital system might be changed to operate a servo motor which
drives the arm of a plotter.
Conversion of n digital voltage levels into one equivalent analog voltage can be
achieved by designing a resistive network. The resistive network changes each digital
level into an equivalent binary weighted voltage or current, which can be added using a
summing circuit to get the equivalent analog signal.
Page 83

Weighted resistor digital to analog converter:
The weighted binary resistive summing network is shown in the Fig. 3.1. The
input signals are applied to the inverting terminal of the op-amp. The magnitude of
current proportional to the value of each bit in the digital input word is generated by the
reference voltage, Vref, divided by the weighed binary resistor (i1=Vref/1k). The input
impedance of the op-amp is infinity, and almost no current can enter into the input
terminals. So the current from weighted binary resistors I has to go through Rf. the
output Vout is the product of current I and feedback resistor Rf. The weightings of the
resistors are that of straight binary coding (8, 4, 2, 1 for 4-bit DAC), with the most
significant bit (MSB) in a 4-bit DAC having a weighting resistance one-eighth that of the
least significant bit (LSB).
Let all the switches D0 to D3 are open, the current through the Rf will be
Vref Vref Vref Vref

0
0
0
0
0 A and the output

1k
2k
4k
8k 1k 2k 4k 8k
Vout I R f 0 1k 0V
I
If the switch D0 and D3 are connected with Vref and the other two switches are open (the
digital word is 1 0 0 1) the current through the Rf will be
Vref Vref Vref Vref 8V 0

0 8V
9mA
1k
2k
4k
8k
1k 2k 4k 8k
and
the
output
Vout I R f 9mA 1K 9V
Since the input is connected in the inverting terminal of the op-amp, the polarity of the
output will be just opposite to the polarity of Vref.
Page 84

Disadvantage:
Weighted binary resistance DACs with more number of bits requires large range
of resistance values. The resistance tolerances that must exist in DACs to achieve
accurate conversions are difficult to maintain over large value of resistance. In addition,
the power requirement varies inversely with the resistance value. In a 4 bit DAC circuit,
this means that if 1/8-W resistor is used for the LSB, a 1-W resistor is needed for MSB.
R-2R Ladder digital to analog converter
Ladder Resistive network (R-2R ladder) is shown in the Fig. 3.2. Only two
resistance values are required, making this circuit ideal for integrated circuit
manufacturing.
Analysis using superposition theorem:
This is done by assuming that an input signal Vref (Fig. 3.2) is applied to only one
input at a time and all other inputs are at zero. The output current is calculated by
applying each of these individual input. Finally all of these outputs are added to get the
total output.
Consider a current that flows into any single input. Whenever such a current
reaches a node, it divides into half, since an equivalent resistance of 2R is exhibited in
both branches. This is shown in the Fig. 3.3 and Fig. 3.4. The current flowing through the
feedback resistor Rf due to the LSB is 1/8 of the current due to the MSB.
The Fig. 3.3 shows, the reference voltage Vref is connected only to MSB,(the
V Va
R
1
digital word is 1 0 0 0) then current i= ref
Va
V ref ; i
V ref
2R
3R
3R
V Va
connected only to LSB,(the digital word is 0 0 0 1) then current i= ref
2R
R
1
Va
V ref
V ref
3R
3R
Vref R f
i
16V 33k
Vout R f
1V
16
16 3 R 16 3 11k
Similarly, analog output for all other digital inputs can be calculated theoretically
Page 85

MSB
LSB
Observations:
Weighted resistor DAC
S.No
10
11
12
13
14
15
16
Theoretical Voltage(V)
Practical Voltage(V)
Page 86

R-2R Ladder Network:
S.No
10
11
12
13
14
15
16
Theoretical Voltage(V)
Practical Voltage(V)
Design:
1. Weighted Resistor DAC
b
b
b
b
Vo = -Rf A B c D
8R 4 R 2R R
For input 1111, Rf = R = 4.7K

Vo = -
Rf
1 1 1
x5
8 4 2
R
Vo = - 9.375 V
2. R-2R Ladder Network:

b
b
b
b
Vo = -Rf A B c D
16 R 8R 4 R 2 R
X5
Page 87

For input 1111, Rf = R= 1K
Procedure:
1. The connections are given as per the given circuit diagrams (Fig. 2.3 and Fig 2.5)
drawn as per the design values.
2. Output voltages for various digital inputs are measured using an analog voltmeter
and they are recorded
3. The output voltage obtained for a particular digital input is verified for validity by
comparing design.
Page 88

Experiment: 9.b
ANALOG TO DIGITAL CONVERTER
Aim:
To convert an analog signal into an equivalent Digital signal using IC ADC0808
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.
7.
Component Name
ADC IC
Trainer kit
Bread Board
Connecting wires
Part No/Range
IC ADC0808
(0-30V)
330 ohm
Quantity in Nos
1
1
1
As Req.
As Req.
1
As Req.
Theory:
General Description
The ADC0808, ADC0809 data acquisition component is a monolithic CMOS
device
with
an
8-bit
analog-to-digital converter,
8-channel
multiplexer
and
microprocessor compatible control logic (Fig. 4.1). The 8-bit A/D converter uses
successive approximation as the conversion technique. The converter features a high
impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree
and a successive approximation register. The 8-channel multiplexer can directly access
any of 8-single-ended analog signals. The device eliminates the need for external zero
and full scale adjustments. Easy interfacing to microprocessors is provided by the latched
and decoded multiplexer address inputs and latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized by incorporating the
most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809
offers high speed, high accuracy, minimal temperature dependence, excellent long-term
accuracy and repeatability, and consumes minimal power. These features make this
device ideally suited to applications from process and machine control to consumer and
automotive applications.
Page 89

Functional Description
MULTIPLEXER
The device contains an 8-channel single-ended analog signal multiplexer. A
particular input channel is selected by using the address decoder. Table 4.1 shows the
input states for the address lines to select any channel. The address is latched into the
decoder on the low-to-high transition of the address latch enable signal.
Table 4.1
CONVERTER CHARACTERISTICS
The heart of this single chip data acquisition system is its 8-bit analog-to-digital
converter. The converter is designed to give fast, accurate, and repeatable conversions
over a wide range of temperatures.
The basic block diagram of the converter is shown in the Fig. 4.1 with doted lines.
The converter is partitioned into three major sections: the 256R ladder network,
the successive approximation register, and the comparator. The converters digital
outputs are positive true.
The 256R ladder network approach was chosen over the conventional R/2R
ladder because of its inherent monotonic, which guarantees no missing digital
codes. The 256R network does not cause load variations on the reference voltage.
When the start pulse signal activates the control circuit, the successive
approximation register (SAR) is cleared.
The output of the SAR is 00000000. V out of the D/A converter is 0. Now, if
Vin>Vout the comparator output is positive. During the first clock pulse, the
control circuit sets a 1 in MSB of the control resistor SAR and a 0 in all bits.
Page 90
Vi
Vo
This initial setting of the register causes the output of the D/A converter (256R
ladder with tree switch) to be half the reference voltage, i.e. Vref.
This converter output is compared to the unknown input Vin by the comparator. If
the input voltage Vin is greater than the converter reference voltage, the
comparator produces a positive output, that causes the control register to retain
the 1 setting in its MSB and the converter continues to supply its reference output
voltage of Vref. The SAR output is 10000000
The switch tree sets 1 in the second MSB of the control register and its reading
becomes 11000000. This causes the D/A converter to increase its reference output
by 1 increment to Vref, i.e. Vref + Vref, and again it is compared with the
unknown input Vin.
Page 91
In this case the total reference voltage exceeds the unknown voltage, the
comparator produces an output (Negative saturation) that cause the control
register to reset its second MSB to 0. The converter output then returns to its
previous value of Vref and awaits another input from the SAR.
When the switch tree changes, the third MSB is set to 1 and the converter output
rises by the next increment of Vref+1/8Vref.
The measurement cycle thus proceeds through a series of successive

approximations. Finally, when the switching (switch tree) reaches up to full scale,
the measurement cycle stops and the digital output of the control register
represents the final approximation of the unknown input voltage.
The A/D converters successive approximation register (SAR) is reset on the

positive edge of the start conversion start pulse. The conversion is begun on the falling
edge of the start conversion pulse. A conversion in process will be interrupted by receipt
of a new start conversion pulse. Continuous conversion may be accomplished by tying
the end of-conversion (EOC) output to the SC input. If used in this mode, an external
start conversion pulse should be applied after power up. End-of-conversion will go low
between 0 and 8 clock pulses after the rising edge of start conversion.
ADC 0808
The chopper-stabilized comparator converts the DC input signal into an AC signal. This
signal is then fed through a high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the drift is a DC component
which is not passed by the AC amplifier. This makes the entire A/D converter extremely
insensitive to temperature, long term drift and input offset errors.
The Fig. 4.2 shows the pin configuration and connection for single channel ADC for the
IC ADC 0808 and the table 4.2 shows the pin description for the IC ADC 0808
Page 92
Table 4.2
Procedure:
1. Connections are made as per the circuit diagram (Fig. 4.2).
2. An appropriate square wave input (5Vpp & 10 kHz) is applied at the pin no. 10 of
IC ADC 0808.
3. Digital output values are recorded for various values of analog inputs.
Page 93

Inference:
Result:
Viva Questions:
1. What are the classifications of DACs on the basis of their output?
2. Name the essential parts of DAC.
3. What are the types of electronic switches used in D/A converter?
4. How many resistors are required in a 12-bit weighted resistor DAC?
5. Why is an inverted R-2R ladder network DAC better than R-2R ladder DAC?
6. What are the various A/D conversion techniques?
7. Which is the fastest ADC and why?
8. What is the conversion time for counting ADC, successive approximation ADC
and dual-slope ADC?
9. How the dual slope ADC provides noise rejection?
10. What are the important specifications of D/A and A/D converters?
Page 94

Experiment: 10a
VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/SE 566 IC
Aim:
To Study the Voltage controlled oscillator and obtain its frequency characteristics
Apparatus required:
S.No
Component Name
1.
VCO IC
2.
CRO
3.
Function Generator
4.
Bread Board
5.
6.
Connecting wires
7.
8.
9.
Resister
10.
Capacitor
Part No/Range
NE/SE 566 IC
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
As Req.
As Req.
1
As Req.
As Req.
Theory:
Voltage-controlled Oscillator:
In oscillators, the frequency is determined by the RC time constant. However,
there are applications, such as frequency modulation (FM), tone generators, and
frequency shift keying (FSK), where the frequency needs to be controlled by means of an
input voltage called control voltage. This function is achieved in the voltage-controlled
oscillator (VCO), also called a voltage -to- frequency converter.
A typical example is the Signets NE/SE 566 VCO, which provides simultaneous
square wave and triangular wave outputs as a function of input voltage. Fig. 5.1 and
Fig. 5.2 show the bin configuration and block diagram of the IC 566 respectively. An
external resistor RT, capacitor CT, and the voltage Vc applied to the control terminal 5 are
used to determine the frequency of oscillation. Alternately charging the external capacitor
CT by one current source and then linearly discharging it by another generates the
triangular wave. The charge-discharge levels are determined by Schmitt trigger action.
The Schmitt trigger also provides the square wave output. From the block diagram (Fig.
5.2) it shows that, the op-amp A2 with positive feedback resistance Ra and Rb forms the
Schmitt trigger circuit. Both the output waveforms are buffered to reduce output
impedance.
Page 95

Operation of Schmitt trigger:
The Schmitt trigger circuit is shown in the Fig. 5.3. Input voltage is applied to the
inverting terminal of the op-amp and feedback voltage to non-inverting terminal. The
input voltage Vin triggers the output Vout every time it exceeds the certain voltage levels.
These voltage levels are called upper threshold voltage VUT and lower threshold voltage
VLT. These two voltages are calculated as follows.
Suppose the output Vout is at positive saturation +Vsat, the voltage at non-inverting
terminal will be Vref
R b (Vsat Vref )
VUT . As long as Vin is less than VUT, the output
Ra Rb
Vout remains constant at positive saturation +Vsat. When Vin is just greater than VUT, the
output switches to negative saturation-Vsat and remains this level as long as V in is geater
than VUT. For Vout = -Vsat ( negative saturation) the voltage at the non-inverting input
terminal is , Vref
R b ( Vsat Vref )
R (V Vref )
Vref b sat
VLT . When the Vin just less
Ra Rb
Ra Rb
than VLT, the output switches to negative saturation -Vsat. If the polarity of input voltage
Vin is keep changing, the above operation repeats and generates output of square wave.
Page 96
Operation of VCO:
Referring to Fig. 5.2, a timing capacitor CT is linearly charged or discharged by a

constant current source/sink.
The amount of current can be controlled by
changing the voltage Vc applied at the modulating input (pin 5) or by changing

the timing resistor RT external to IC 566.
The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the modulating
voltage at pin 5 is increased, the voltage at pin 6 also increases, resulting in less
voltage across RT and thereby decreasing the charging current.
Page 97
The voltage across the capacitor CT is applied to the inverting input terminal of
Schmitt trigger A1 via buffer amplifier A1. The output voltage swing of the
Schmitt trigger is designed to Vcc and 0.5 Vcc.
If Ra = Rb in the positive feedback loop, the voltage at the non-inverting input

terminal of A2 swings from 0.5 Vcc to 0.25 Vcc.
When the voltage on the capacitor CT exceeds 0.5Vcc (VUT) during charging, the
output of the Schmitt trigger goes LOW (0.5Vcc).
The capacitor now discharges and when it is at 0.25 Vcc, the output of Schmitt
trigger switches to logic HIGH (Vcc).
Since the source and sink currents are equal, capacitor charges and discharges for
the same amount of time. This gives a triangular voltage waveform across CT
which is also available at pin 4.
The square wave output of the Schmitt trigger is inverted by inverter A3 and is
available at pin 3.
The output frequency of the VCO can be calculated as follows:

The total voltage on the capacitor changes from 0.25 Vcc to 0.5 Vcc. Thus
v 0.25Vcc . The capacitor charges with a constant current source.
v
i
t C T
0.25 Vcc
i
t
CT
t
0.25 Vcc C T
i
The time period T of the triangular waveform = 2 t . The frequency of oscillator f0 is,
f0
But,
1
1
i
T 2t 0.5Vcc C T
Vcc - vc
where, vc is the voltage at pin 5. therefore
RT
f0
2(Vcc v c )
R T C T Vcc
Page 98

The output frequency of the VCO can be changed either by changing the values of
RT and CT or by varying the voltage vc at the modulating input terminal pin 5. The
voltage vc can be varied by connecting an external resistances R1 and R2 between Vcc to
grounds, through pin no 5. This is shown in the Fig. 5.4. With no modulating input signal,
if the voltage at pin 5 is biased a (7/8)Vcc as, f 0
7
V cc )
1
0.25
8
R T C T V cc
4R T C T
R TCT
2(V cc
Voltage to frequency conversion factor:

A parameter of importance for VCO is voltage to frequency conversion factor Kv
and is defined as K v
f 0
. Hare vc is the modulation voltage required to produce the
v c
frequency shift f 0 for a VCO. If we assume that the original frequency is f0 and the new
frequency is f1, then
f 0 f1 f 2
2(Vcc vc v c ) 2(Vcc v c )
2v c
R T C T Vcc
R T C T Vcc
R T C T Vcc
v c
f 0 R T C T Vcc
2
v c
f 0 Vcc
8f 0
Kv
f 0 8f 0
vc Vcc
calculate R T C T from f 0
0.25
and substitute in v c
R T CT
Page 99

Procedure:
1. Connections are made as per the circuit diagram obtained as per the design values.
2. The activation input (Vcc)of 5V d.c. is applied from a regulated power supply
unit
3. The modulating input Vc of 2V d.c. is applied from regulated power supply unit.
4. The output signals (VCO output and buffer amplifier output) are observed using a
CRO and the frequency and amplitude (p-p) of the output waveforms are
recorded.
5. The output is verified for validity by comparing the frequency which the circuit is
designed and input voltages.
Page 100

Experiment: 10b
FREQUENCY MULTIPLICATION USING NE/SE 565 PLL IC
Aim:
To Study the operation of Phase-Locked Loop and obtain its frequency
characteristics.
Apparatus required:
S.No
1.
2.
3.
4.
5.
6.
7.
Component Name
PLL IC
Function Generator
CRO
Bread Board
Connecting wires
Part No/Range
NE/SE 565 IC
(0-30V)
330 ohm
Quantity in Nos
1
1
1
1
As Req.
1
As Req.
INTRODUCTION
The phase-locked loop is a feedback system comprised of a phase comparator, a
low-pass filter and an error amplifier in the forward signal path and a voltage-controlled
oscillator (VCO) in the feedback path. The block diagram of a basic PLL system is
shown in Fig. 6.1. Designers use this device to lock a locally generated waveform onto
both the phase and frequency of a received waveform. Phase-locked-loop (PLL)
frequency synthesizers are used throughout communications systems to provide a stable
source of carrier and base band signals. It also has many interesting applications,
including frequency synthesis, FM demodulation, and television sweep circuits.
Page 101
Phase-Locked Loop Operation:

The basic principle of the PLL operation can be briefly explained as follows:
With no signal input applied to the system, the VCO control voltage Vd(t) is equal to
zero(Fig.6.1). The VCO operates at a set frequency, f0 which is known as the freerunning frequency. When an input signal vs(t) is applied to the system, the phase
comparator compares the phase and the frequency of the input with the VCO frequency
and generates an error voltage ve(t) that is related to the phase and the frequency
diHerence between the two signals. This error voltage is then filtered, amplified, and
applied to the control terminal of the VCO. In this manner, the control voltage V d(t)
forces the VCO frequency to vary in a direction that reduces the frequency difference
between f0 and the input signal. If the input frequency fs is sufficiently close to f0, the
feedback nature of the PLL causes the VCO to synchronize or lock with the incoming
signal.
Once in lock, the VCO frequency is identical to the input signal except for a finite
phase difference. This net phase difference of where = 0- s is necessary to generate
the corrective error voltage Vd to shift the VCO frequency from its free-running value to
the input signal frequency fs and thus keep the PLL in lock. This self correcting ability of
the system also allows the PLL to track the frequency changes of the input signal once it
is locked.
Page 102

The range of frequencies over which the PLL can maintain lock with an input
signal is defined as the lock range of the system. The band of frequencies over which
the PLL can acquire lock with an incoming signal is known as the capture range of the
system and is never greater than the lock range.
The phase comparator is in actuality a multiplier circuit that mixes the input
signal with the VCO signal. This mix produces the sum and difference frequencies fs f0
shown in Fig. 6.1. When the loop is in lock, the VCO duplicates the input frequency so
that the difference frequency component (fs - f0) is zero; hence, the output of the phase
comparator contains only a DC component. The low-pass filter removes the sum
frequency component (fs + f0) but passes the DC component which is then amplified and
fed back to the VCO. (Note: When the loop is in lock, the difference frequency
component is always DC, so the lock range is independent of the band edge of the lowpass filter.)
Let the input signal is
v s Vs sin(2 f s t) and the VCO output voltage is
v 0 V0 sin (2 f s t ) then the phase comparator output is given by

v e KV s V0 sin(2 f s t) sin(2 f s t ) where the K is the phase comparator
gain (or attenuation constant) and is the phase shift between the input signal and VCO
output. The above equation is like sinAsinB, so it can be written as
ve
KV s V0
[cos(2 f s t - 2 f 0 t - ) - cos(2 f s t 2 f 0 t )]
2
When the loop is in lock, fs=f0
ve
component
KV s V0
[cos(- ) - cos(2 2 f 0 t )] The
2
frequency
KV s V0
[ - cos(2 2 f 0 t )] is eliminated by the low pass filter
2
and the DC component
KV s V0
cos( ) is applied to the modulating input terminal
2
of a VCO.
Page 103

Phase detector:
A circuit which performs phase comparison with square wave input is shown in
the Fig. 6.2. This is a balanced modulator used as full-wave switching phase detector.
The input signal is applied to the differential pair Q1Q2. Transistors Q3-Q4 and Q5-Q6 are
two sets of SPDT switches activated by the VCO output. (Assumption: Input vs and VCO
output v0 are high enough to switch the transistors)
In Fig. 6.3 (a) when vs and v0 both are high during the time period 0 to -, transistors
Q1 and Q3 are driven ON and current IE flows trough Q1 and Q3. This gives an output
voltage
ve = -IERL
Next for the period (-) to , when vs is high and v0 is low, transistors Q1 and Q4 are
driven ON resulting in an output voltage
ve = IERL
Page 104
Page 105

In this way, the output voltage waveform ve in Fig. 6.3 (a) is obtained. The
average value of the phase detector output ve can be calculated as
1
[(area A 1 ) area A 2 )]
1
[I E R L (-I E R L ) ( - )]
IER L
1

4I R
Q L

2
ve
K - - - - - - - - - - - - - (1)
2
Since I E 2 I Q
Where K
4I Q R L
K is the phase angle to voltage transfer coefficient or, the conversion ratio of the phase
detector. This linear relationship between ve and is depicted in Fig. 6.3 (b).
IC PLL 565
IC NE/SE 565 is available as a 14-pin DIP package and as 10-pin metal can
package. The pin configuration and basic block diagram are shown in Fig. 6.4 and Fig.6.5
respectively. The output frequency of VCO can be written as,
f0
0.25
Hz
R TCT
-------------------------------- (2)
Where RT and CT are the external resistor and capacitor connected to pin 8 and pin 9. A
value between 2k and 20k is recommended for RT. The CVO free running frequency
is adjusted with RT and CT to be at the centre of the input frequency range. It may be
seen that phase locked loop is internally broken between the VCO output and the phase
comparator input. A short circuit between pins 4 and 5 connects the CVO output to the
phase comparator so as to compare f0 with input signal fs. A capacitor C is connected
between pin 7 and pin 10 (supply terminal) to make a low pass filter with the internal
resistance of 3.6k.
The output voltage of the phase detector is limited by the diode connected
transistors to a maximum of 0.7V which minimizes the effect of high amplitude noise
Page 106

pulses and other transient effect on the operation of the PLL. This makes the conversion
ratio of the phase detector of 565 PLL as,
0 .7 ( 0 .7 ) 1 .4
. ------------------------------- (3)
Page 107

A balanced output is taken from the phase detector and amplified with the gain of
1.4. The amplified signal is given to a low pass filter (LPF) to remove the high frequency
component. The output from LPF is connected to the modulating input of VCO.
DERIVATION OF LOCK-IN RANGE:
If radian is the phase difference between the signal and the VCO voltage, then
the output voltage of the analog phase detector is given by,
ve K
2
(From Equation (1))
Where, K is the phase angle to voltage transfer coefficient of the phase detector. The
control voltage to VCO is,
vc AK
2
------------------------ (4)
Where, A is the voltage gain of the amplifier. This vc shifts VCO frequency from its free
running frequency f0 to a frequency f given byu,
f f 0 K v vc
-------------------------(5)
Where, Kv is the voltage to frequency transfer coefficient of the VCO. When PLL is
locked in to signal frequency fs, then we have
f f s f 0 K v vc
vc
- - - - - - - - - - - - - (6)
fs f0
AK - - - - - - - - - -(7) (From the equation (4))

Kv
2
Then, the phase difference between the signal and the VCO voltage is given by
f f0
s
2 K vK A
The maximum output voltage magnitude available from the phase detector occurs for
= and 0 radian, which is shown in the Fig.6.3 (b) and ve(max)=K/2 from equation
(1). The corresponding values of the maximum control voltage to drive thee VCO will
be,
vc (max)
KA
2
Page 108

The maximum VCO frequency swing that can be obtained is given by,( from equation
(f f 0 ) max K v vc(max) K v K A
(7))
Therefore, the maximum range of signal frequencies over which the PLL can remain
locked will be,
f s f 0 (f f 0 ) max f 0 K v K A
f 0 f L
2
Where 2fL will be the lock-in frequency range and is given by,
Lock-in range =
2f L K v K A
f L K v K A
The lock-in range is symmetrically located with respect to VCO free running frequency
f0.
For the IC PLL 565
Kv
8f 0
(Voltage to frequency conversion factor of VCO)
V
V Vcc (Vcc ) and K
Where
1 .4
. (From the equation (3)).
The voltage gain for IC PLL 565, A=1.4.

The lock-in range can be written as
f L K v K A
7.8f 0
2
V
Derivation of Capture range:

When PLL is not initially locked to the signal, the frequency of the VCO will be
free running frequency f0. The phase angle difference between the signal and the VCO
output voltage will be,
(s t s ) (0 t 0 ) (s 0 )t
Thus the phase angle difference does not remain constant but will change with time at
a rate given by
Page 109
d
(s 0 )
dt
The phase detector output voltage will therefore not have a dc component but will
produce an ac voltage with a triangular waveform of peak amplitude K/2 and a
fundamental frequency (fs-f0) = f.
The low pas filter is a simple RC network having transfer function
T(s)
1
(s 0 )
RCs 1
T(j )
Where
f1
1
1
jRC 1 j2fRC 1
1
1
f
f1
1
is the cutoff frequency or 3-dB pint of Low Pass Filter. Magnitude
2RC
of the of the transfer function is given by
f
T(j )
1 , then
2 . If the term
f
f
1
1
f1
f
T(j ) 1
f
The fundamental frequency term supplied to the LPF by the phase detector will be the
difference frequency f = (fs-f0). If f>3f1, the LPF transfer function will be
approximately.
f
f
T(j ) 1 1
f f s f 0
The voltage vc to drive VCO is
f
f
v c v e 1 A or v c max v e max 1 A
f
f
Page 110
v c max K v K
f1
2 f
The corresponding value of the maximum VCO frequency shift is given by,
f
(f f 0 ) max K v vc(max) K v K A 1
2 f
For the acquisition of signal frequency, we should put f=fs, then
f
(fs f 0 ) max K v vc(max) K v K A 1
2 f c
(fs f 0 ) max f c so,

f
f c K v K A 1
2 f c
fc 2 K v K A f1
2
Since f L K v K A
f c 2 f1f L
f c f1f L
Therefore the total capture range is
2f c 2 f1f L
Where the lock-in range =2fL=KvKA. In case of IC PLL 565, R=3.6k so the capture
range is
f c
f L
2 (3.6103 )C
The capture range is symmetrically located with respect to VCO free running
frequency f0 as is shown in fig.6.6.
Page 111
The PLL cannot acquire a signal outside the capture range, but once captured, it
will hold on till the signal frequency goes beyond the lock-in range.
Procedure:
1. Connections are made as per the circuit diagram obtained as per the design
values.
2. The activation input (Vcc)of 6V d.c. is applied from a regulated power
supply unit
3. The VCO output is connected to phase comparator VCO input terminal.
4. Modulating input Vc of 2V d.c. is applied from regulated power supply unit.
5. The output signals (VCO output, Demodulated output and Reference output
and capacitor output) are observed using a CRO and the frequency and
amplitude (p-p) of the output waveforms are recorded.
6. The output is verified for validity by comparing the frequency for which the
circuit is designed and input voltages.
Inference:
Page 112

Result:
Viva Questions:
1. What are the basic building blocks of a PLL?
2. What is mean by capture range and lock range?
3. What is the major difference between digital and analog PLLs?
4. What is mean by pull in time?
5. What is the range of modulating input voltage applied to a VCO?
6. What are the applications of PLL?
7. Which is greater capture range or lock range and why?
8. What are the important electrical parameters of 565PLL?
9. When the PLL is said to be in locked state?
10. What is mean by phase detector?
Page 113

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Department of Electrical and Electronics Engineering

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LINEAR AND DIGITAL IC LABORATORY

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ADDERS, SUBTRACTORS AND REDUCTION OF A BOOLEAN

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STUDY OF ENCODERS AND DECODERS

DESIGN AND IMPLENTATION OF 4-BIT MODULO

STUDY AND DESIGN OF 4 :1 & 8 :1 MULTIPLEXER AND

MONOSTABLE AND ASTABLE MULTIVIBRATOR USING 555

APPLICATIONS OF OPERATIONAL AMPLIFIERS

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