CURRICULUM VITAE

KESHAVA A
Resume Highlights:
Master of Technology in VLSI Design and Embedded
Systems.
Bachelor of Engineering Degree in Electronics and
Communication.
Knowledge of Verilog, VHDL, CMOS VLSI Design,
Embedded systems, Microcontroller, Nanoelectronics.
Willingness to improve Skills and Knowledge.

Address:
S/O Achappa, Gowdahalli (V),
Doddatumakur (P), Doddaballapur
(T), Bangalore Rural (D) 561203.
Mobile : +919538537826
Email : keshava.2805@gmail.com

GOAL
To associate myself with a professionally driven esteemed organization by pursuing a challenging,
dynamic, responsible and rewarding career and applying my professional expertise, skills and enthusiasm in
a position for career growth.
PROFESSIONAL QUALIFICATION
Course

Name of the
Institution

Board /
University

Combination
Taken

Percentage
Obtained

Year &
Month of
Passing

Master of
Technology
(Full Time)

Reva Institute of
Technology and
Management,
Yelahanka, Bangalore

Visvesvaraya
Technological
University

VLSI Design and

Embedded
Systems

75.87%

October
2013

Bachelor of
Engineering

S.J.B Institute of
Technology, Kengeri,
Bangalore.

Visvesvaraya
Technological
University

Electronics &
Communication

64.57%

June 2011

PUC or +2

Seshadripuram
Composite PU
College, Bangalore.

Karnataka Pre
University
Board

PCMB

71.83%

May 2007

Vishwamanava
English Medium
School,
Kommerahalli,
Mandya.

Karnataka
Secondary
Education
Board

Nil

79.20%

April 2005

SSLC or 10
Std

th

WORKING EXPERIENCE
Working as a Part Time Lecturer in Bangalore Institute of Technology (BIT), Bangalore, from February
2014 to till date.

COMPUTER PROFICIENCY
Programming Languages: Verilog, VHDL, Assembly, C and C++.
Assembly Languages: Microprocessor (8086) and Microcontroller (8051, MSP430).
Operating Systems: Windows, RTOS.
Interest subjects: CMOS VLSI Design, VLSI verification, Embedded Systems and RTOS.
PROJECTS UNDERTAKEN DURING PG

VLSI-Oriented Architecture for Twos Complement Serial-Parallel Multiplication without Speed

Penalty
The proposed architecture requires up to 30 percent smaller size without speed penalty compared to
the previous architecture. Tools used: LT Spice, Xilinx ISE Design Suite.

Physical Layer Implementation of Orthogonal Frequency Division Multiplexing for Software

Defined Radio
This project discusses the implementation of a software defined radio (SDR) that uses orthogonal
frequency division multiplexing (OFDM). The transmitter and receiver were modeled and simulated using
the Xilinx blockset in MATLAB Simulink then implemented on hardware using Xilinx ISE 10.1.
Performance of the SDR system was evaluated by measuring Bit Loss, Packet Loss and spectral
efficiency under simulated channel conditions with SNR of 60 dB. Tools used: Xilinx ISE 10.1,
ModelSim6.3f, Xilinx Spartan-3, MATLAB Simulink.

PROJECTS UNDERTAKEN DURING U G

Implementation of Leaky Bucket Algorithm in ATM Networks

This project aims in controlling congestion by using a reactive congestion control method called
Leaky Bucket Algorithm, which helps in traffic shaping.

SEMINARS IN PG AND WORKSHOPS ATTENDED

UG (BE) seminar - Digital Technique to Generate Variable and Multiple PWM Signals, Year 2011.

PG (M.Tech) seminar in 1st semester IP Reuse in Modern Day SoC, Year 2011.

PG (M.Tech) seminar in 2nd semester Finite State Machine (FSM) Design, Year 2012.

Attended 3 day workshop on VLSI circuits and systems conducted by Sandeepani school of
Embedded System Design, learnt the open source electric tool and cadence tool, Year 2012.

Attended one day workshop on Research Methodology and was exposed to the various methods of
research work, Year 2012.

INDUSTRIAL TRANING
Undergone Internship Program in National Aerospace Laboratories, Bangalore. Duration Aug 2012 to
July 2013.

CONFERENCES

Keshava A, Implementation of Physical Layer for Software Defined Radio Using Orthogonal
Frequency Division Multiplexing on FPGA, Proceedings of the National Conference on VLSI,
Communication & Computer Networks, AMCEC, Bangalore, Karnataka, India, May 3rd, 2013.

ASSETS

Self- Confidence

Adaptable and positive attitude

Ability to work with sincerity and hard worker

LANGUAGES KNOWN

English

Kannada

INTEREST AND ACTIVITIES

Playing and Watching Cricket

Solving Sudoku

Listening to music

PERSONAL PROFILE
Father Name

: Achappa

Mother Name

: Rama devi

Gender

: Male

Date of Birth

: 28th May 1990

Nationality

: Indian

DECLARATION
I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Date:
Place: Bangalore

KESHAVA A