A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s

Pipelined ADC Using Hybrid Dynamic Amplifier

Hariprasath Venkatram*, Taehwan Oh**, Kazuki Sobue1, Koichi Hamashita1, Un-Ku Moon

Oregon State University, Corvallis, OR, U.S.A; 1Asahi Kasei Microdevices, Atsugi, Japan
venkatha@eecs.oregonstate.edu
(A4), the effective phase margin and DC gain of the amplifier,
Abstract
A hybrid dynamic amplifier is proposed which combines the shown in Fig. 2, for a given unity gain bandwidth (UGB),
desirable features of a dynamic amplifier and a class AB increases from 40 degrees and 65 dB to 60 degrees and 95 dB
amplifier. This technique allows us to achieve a power respectively. The dynamic path provides fast signal dependent
efficient high resolution pipeline ADC. A proof of concept charge transfer and higher bandwidth while the slow, large DC
pipelined ADC in a 0.18 m CMOS process achieves 74.2 dB main path provides final settling and accuracy. This emulates
SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline the trends shown in Fig. 1 [3]. Table-I compare performance
ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 trade-offs among the different architecture choices.
mm2. The ADC achieves a FoM of 48 fJ/CS without any form
Table I Comparison against conventional two-stage amplifier
of calibration.
Value
Class
Dynamic
PGE
Hybrid
Introduction
AB
[3]
[5]
Dynamic
The high resolution ADC power consumption in Nyquist ADC
Speed
High
Low
Med
High
is dominated by the power consumption of the amplifier [1, 2].
Accuracy
Low
High
High
High
The theoretical power consumption bound for a pipeline ADC,
Power
Med
Low
Med
Med
shown in [2], is considerably lower than the existing high
A
13-bit
thermal
noise
limited
prototype
pipeline
ADC
was
resolution Nyquist ADC. In order to improve power efficiency
designed
to
verify
the
hybrid
class
AB
amplifier
as
shown
in
for a high resolution, wide bandwidth ADC, a hybrid dynamic
stages followed
amplifier is proposed. The prototype ADC using the proposed Fig. 3. The pipeline ADC consists of six 2.5 bit
by a 3 bit flash ADC. The main path (1st stage) sampling
amplifier achieves the energy efficiency predicted by [2].
capacitor was 2 pF, GM = 4 and dynamic path capacitor was
Hybrid Dynamic Amplifier
500
fF, Gp = 5 as shown in Fig. 3. The dynamic amplifier
Dynamic amplifiers have been utilized to improve power
allows
for signal dependent charge transfer, higher UGB, a
efficiency [3, 4]. In a given time period, as shown in Fig. 1, the
simple
SC-CMFB and achieves 50% higher bandwidth (15
bandwidth of the dynamic amplifier reduces while the
MHz)
for
same power and accuracy as compared to [5].
DC-gain/output impedance increases [3]. However, the
trade-off between accuracy and bandwidth is skewed towards
accuracy at the expense of bandwidth [3]. On the other hand,
class AB amplifier provides higher bandwidth at the expense
of increased non-linearity. The proposed hybrid dynamic
amplifier enables us to combine features of dynamic and class
AB amplifier effectively to produce a high accuracy and
bandwidth amplifier as compared to a stand-alone class AB
amplifier or a dynamic amplifier.

Fig. 2. Hybrid dynamic amplifier

Fig.1. Dynamic Amplifier (a) UGB, Gain vs. time (b) Error vs. time

Pipeline ADC with hybrid dynamic amplifier

Fig. 2 shows differential switched capacitor hybrid dynamic
amplifier. The dynamic amplifier is biased using Vyp1, Vyn1,
Vxp2, Vxn2. The dynamic amplifier (A4) reduces the power
consumption of the second stage by a factor of 3x as compared
to a conventional amplifier without sacrificing accuracy or
bandwidth. The second stage size is 0.2x and the dynamic
amplifier size is 0.15x as compared to a second stage of a
conventional two-stage (1x). By adding the dynamic amplifier

Fig.3. Pipelined ADC with hybrid dynamic amplifier

Measurement Results
The prototype pipeline ADC occupies 3.6 mm x 0.8 mm active

* Hariprasath Venkatram is now with Intel Corporation, Hillsboro, OR and ** Taehwan Oh is now with Tektronix, Inc., Beaverton, OR

978-1-4799-3328-0/14/$31.00 2014 IEEE

2014 Symposium on VLSI Circuits Digest of Technical Papers

area and operates at 1.3 V supply voltage at 30 MHz clock

frequency. Fig. 4 shows the measured spectrum for a 2 MHz
input with 30 MHz clock. The measured SNDR, SFDR and
THD were 74.2 dB, 87 dB and -85dB respectively. The
measured SNDR, SFDR and THD at 15 MHz Input were 72
dB, 86 dB and -84 dB. Fig. 4 shows the performance with
dynamic path ON and OFF. With dynamic path switched OFF,
the amplifier gain and phase margin degrades, as discussed
above, leading to degraded SNDR and THD performance. As
shown in Fig. 5, the measured 13-bit INL and DNL were
+0.61/-0.64 and +0.41/-0.34 LSB, respectively. The opamps
were not shared or switched off during the sampling phase
owing to the power consumption of 4.2 mW for the analog
portion. The digital portion consumes 1.8 mW and the total
power consumption is 6 mW.
0

Nyquist-ISSCC '97-'13

Nyquist-VLSI '97-13

Epipe

10000

1000
FoM, fJ/C-S

[5]

100

This Work
10
70

72

74
SNDR, dB

76

78

Fig. 7. ADC BW > 5 MHz, SNDR > 70 dB & Pipeline ADC bound[2]

Dynamic (A ) OFF Dynamic (A ) ON

4
4

SINAD = 62.12 dB SINAD = 74.24 dB

Magnitude dBFS

-20

SFDR = 74.35 dB

SFDR = 87.28 dB

-40

SNR = 62.60 dB

SNR = 74.61 dB

-60

THD = -71.92 dB THD = -85.03 dB

ENOB = 10.03 bits ENOB = 12.04 bits

-80
-100
-120
-140

2000 4000 6000 8000 10000 12000 14000 16000

Sample Points

Fig. 4. Measured FFT Spectrum with 30 MHz Clock

DNL

Fig.8. Performance Summary and Die-Micrograph along with STG-1

-1
-4000

-3000

-2000

-1000

-3000

-2000

-1000

1000

2000

3000

4000

0
1000
Digital Code

2000

3000

4000

INL

1
0

-1
-4000

Fig. 5. DNL, INL, 13-bit LSB

SNDR, SFDR, THD [dB]

90

Fig.6 shows the dynamic performance. The SFDR and THD

remain fairly constant throughout signal bandwidth validating
the improved distortion performance through increased gain
and bandwidth of the dynamic amplifier. Fig. 7 contains the
comparison among high resolution (>70 dB SNDR) and
bandwidth (>5 MHz) Nyquist ADC and the theoretical
pipeline ADC bound. Fig. 8 shows the die micrograph and
performance summary.
Acknowledgement
The authors thank AKM for supporting this work and
providing fabrication.
References

85

[1]

SNDR
SFDR
THD
SNR

80

[2]

75

[3]
2

6
8
10
Frequency[Hz]

12

[4]

14
6

x 10

Fig. 6. Dynamic Performance, SNDR & SNR are the same

[5]

B. Murmann, "ADC Performance Survey 1997-2013," [Online].

Available: http://www.stanford.edu/~murmann/adcsurvey.html.
T. Sundstrom, B. Murmann, and C. Svensson, "Power
Dissipation Bounds for High-Speed Nyquist Analog-to-Digital
Converters", TCAS- I, vol. 56, no. 3, pp. 509-518, Mar. 2009.
J. B. Hosticka, "Dynamic CMOS amplifiers," JSSC, vol.15, no.5,
pp.881-886, Oct 1980.
H. Venkatram, T. Oh, J. Guerber, and U. Moon, "Class-A+
amplifier with controlled positive feedback for discrete-time
signal processing circuits", ISCAS., May 2012.
H. Venkatram, et al, "Parallel gain enhancement technique for
switched-capacitor circuits," CICC, 2013 IEEE, vol., no., pp.1,4,
22-25 Sept. 2013.

2014 Symposium on VLSI Circuits Digest of Technical Papers