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Hctor Sucar
Alejandro Moreno
Maestra en Diseo de Circuitos Integrados
ITESO
1. Intro to Verification
Development flow
Device specification
System requirements, external interface, architecture
Verification framework (test bench)
Micro-architecture specification
Design hierarchy and interfaces
Reference model
Verification plan, functional coverage
Functional implementation
RTL model
Verification checkers
RTL verification vs reference model
Coverage evaluation
Fabrication
Mask generation
Wafer fabrication and packaging
Test generation (BIST, ATPG)
Fault grading
*Built-in Self-Test
*Automatic Test Pattern Generation
What is Verification?
To prove equivalence
To check/compare the expected or correct result
To find errors in the result
You are always verifying:
DESIGN
Implementation
VERIFICATION
Validate
To prove that the implementation is a correct physical
representation of its specification.
HW Design
Spec
Silicon
RTL/Netlist
Verification
Verification
Proves the pre-silicon design
(implementation errors)
Testing
Testing
Proves the post-silicon design
(manufacturing defects)
Common Errors
Pre-Silicon
Low Cost
Post-Silicon
Pre-Production
Post-Production
Very Expensive
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Critical path
Verification increases or decreases TTM, and it impacts
cost significantly.
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Functional Verification
Proves the equivalence between two representations or models,
Reference Model and Functional Model -RTL- using simulation tools.
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Functional Verification
The FV process is based on two principles:
Controllability - Ability of internal/external inputs to move the
model from any initial state to any other state: Stimuli
Observability - Ability of internal/external outputs to get the
current state of the model for analysis: Responses
Controllability
Stimuli
Functional
Models
RTL/RM
Observability
Response
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Conclusions
Hardware Verification is the process to prove that an
implementation behaves according to the specification for all
possible scenarios.
Verification is the measure of quality of the product.
Verification time can be reduced through: Parallelism,
Abstraction, Automation, Randomization and Functional
Coverage.
Structural Verification proves the equivalence between two
representations or models using formal methods.
FV proves the equivalence between two models: RM vs RTL
using simulation tools. FV is based on Controllability and
Observability.
Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO
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