The World Leader in High Performance Signal Processing Solutions

Simplifying Radio Design Using a Wideband

IF Receiver Subsystem IC
Presented by: Paul Hendriks
Applications Engineer
February 2015

AGENDA
Overview

of Wideband Heterodyne Radio Using IF Sampling

Design

Challenges for Next Generation Reconfigurable

Receivers

Example

of Industry Leading High Dynamic Range Radio

Overview
Support
Q

of Enabling IF Rx Subystem IC

Tools facilitating quick evaluation and prototyping

& A Session

Heterodyne Wideband Digital Receiver

Duplexer

RF
SAW

Image-Reject
Filter
ATT

Heterodyne

High Order
LC LPF

IF
SAW
DGA

Receiver

Most

widely deployed receiver for high performance receivers

Architecture (and limitations) are well understood.
IF Sampling ADCs (introduced in late 1990s) eliminated need for
second down conversion stage
While advances in Direct Conversion Receivers are being
madechallenges still remain to achieve SFDR<<-80 dBc
The
RF

Challenge Moving Forward

Bandwidths continue to increase (from 20 MHz to 160+MHz)

One SDR Platform covering wide range of RF bands (0.7-3.8 GHz)
3

The Wireless Environment is a Harsh Place!

New

wideband standards (LTE) co-existing with old ones (GSM)

Co-location, self-blockers from transmitter in FDD (i.e. Tx Leakage)

High User Demand with High Quality of Service Demands

Consider Superbowl 2015 and usage right after game ended!

It

all has to workand receiver dynamic range is key!!

http://www.analog.com/AD6676

IF-Sampling Digital Receiver Challenges

RF
SAW

IR
Filter
ATT

IF

High Order
LC LPF

IF
SAW
DGA

Signal Path Complexity

IF

Filtering due to ADC Nyquist Constraints (i.e. FS/2)

Lossy 15+ dB IF SAW Filter and Higher Order LC LPF
AGC Control.especially if RF/IF AGC used in tandem
Goal: Maximize Receivers Instantaneous Dynamic Range to
increase AGC threshold level (i.e. reduce probability of its use)
IF

Strips PCB Area and Power Consumption

More
5 IF

components>>>More space and power!!

Frequency Planning

IF Frequency Planning Constraints

Mixer
Spurious

IF

selection for Multi-band/mode radio

has its challenges!!!!
Spurious and Image Bands
High vs Low Side Injection (IF/2, IF/3)
ADC Nyquist Zone and Aliasing of Spurs
PLL Spurious (Reference spurs)

The

IF constraint Cube
shrinks with increasing RF BW!!!

High OSR ADC expands IF choices!!!

Oversampling

High
IF
6

(OSR) = FS/2*BW

PLL Spurious

Mixer

Suitable
IFs
(>BW)

ADC Nyquist Zone/

Aliasing Spurious

OSR (w/ digital filtering) reduces IF filtering!!

can be optimized for mixer and PLL

Aliasing and close in Mixer spurs (2x2) are not an issue

Mixer MxN Spurious

Mixer

Spur Charts or CAD tools help identify

potential suitable IFs

Mixer

Spur Tables

provided on datasheet for popular RF and IF

combinations as well as other characterization provide
insight on a mixers behavior.

(N-M)/M

Often

N/M
7

ADC Nyquist and Alias Spurious

Mixer

Spur Charts or CAD tools help identify

potential suitable IFs
Mixer Spur Tables
Often

provided on datasheet for popular RF and IF

combinations as well as other characterization provide
insight on a mixers behavior.

Mixer MxN Spurious and ADC Nyquist

ADL5355

Mixer Output w/ LO=1550 MHz and IF=250 MHz

RF

tone swept from 1774 to 1826 MHz (Peak Hold for Spec. Ana.)
Nyquist Zones=100 MHz for 200 MSPS ADC, IF centered in 3rd
For

RF BWs >50 MHz, Mixers 2X2 sets LPF transition band

95 dB SFDR requires extra 27 dB rejection under an octave!!

200 MSPS ADC Nyquist Zone
Swept CW @ -1 dBm Output
SA Set to Peak Hold
1st
LPF

2nd
27dB

3rd

4th

5th

6th

7th
Mixer
2x2

8th

9th
Mixer
3x3

10th

Mixer MxN Spurious and ADC Nyquist

IF

(cont.)

Sampling ADCs have Input BWs of 800+ MHz

Mixer

M x LO harmonics are visible by ADC

LO Leakage (0,1). lots of suppression if aliasing back into ADC IF
Other spurious can also be problematic for <-95 dB SFDR

1,-1
IF

10

0,1
LO

0,2
2xLO

0,3

Benefit of High Oversampling ADC

Larger

Mixer MxN products fall out-of-band.no aliasing!!

IF

frequency planning still applies for MxN terms that fall in-band
Mixer IMD still an issue
Digital

filtering removes out-of-band noise spurs

BPSDADC Output Before Filtering BPSDADC Output After Filtering

FADC=3200 MSPS
11

FIQ=100 MSPS
Dec-by-32

PCB AreaIf Size Really Matters!

Industry
Higher

What

Trend

integration, Lower Size/Power, Higher Performance

if a Rx IF Subsystem could result in

70%

PCB savings with lower BOM

30+% in Power Savings
And.More Dynamic Range!!!!
12 mm x 45 mm
Mixer
5x5mm

IF SAW
5x7mm

DGA
5x5mm

AAF

10 mm x 15 mm
ADC
7x7mm

Mixer
5x5mm

>70% smaller
PCB Area
12

IF Subsystem

Seeing is Believing!

High Performance Receiver Example

(RF=1800, LO=1550, IF=250, BW=40, CLK=3200, FDATA_IQ=100 MSPS)

15 mm

Mixer

13

LPF

IF Rx
Subsytem IC 10
mm

High AGC-free Dynamic Range

w/ NF<16 dB and PIN_0dBFS=0 dBm

NF=16 dB

14

High Linearity Performance with 2-Tone

IMD=-84 dBc ( IIP3=34 dBm)
(

15

Excellent Swept Spurious Performance

(Frequency Planning Required)

CW swept from
1750 to 1850 MHz

16

http://www.analog.com/AD6676

Passband Flatness of +/-0.2 dB

17

http://www.analog.com/AD6676

AD6676 Wideband IF Receiver Subsystem

Enables Breakthrough Direct VHF or heterodyne UHF Rx Architectures

Industry

leading Dynamic Range

NSD

of -160 dBFS/Hz, IMD3 of -96dBc

IIP3 up to 36dBm, NF of 13dBm
Swept Spurious < -99 dBFS
Nominal PIN_0dBFS = -2 dBm
Adjustable over +13 to -14 dBm range
Easy to drive ZIN of 60 ohms
Based

on Reconfigurable oversampled BP
ADC technology
SAW filter, DGA and IF Gain
PCB area savings up to 70%
Simple RF-to-IF mixer interface with LPF
Very wide tunable IF/BW Rx platform
Same mixer-to-bits line-up can support 0.7-3.8 GHz

4.3mm

Eliminates

18

5.0mm

AD6676 Wideband IF Receiver Subsystem

Enables

Reconfigurable Wideband IF Rx Subsystem

Support

Direct Sampling VHF or Heterodyne UHF Receivers

IF Frequency tunable from 70-450 MHz
Usable Passband BW tunable from 20-160 MHz
Profile Feature allows up to 4 different IF/BW combinations
that can be switched within 1 second
High

Level of Integration/Functionality

IF

Digital Attenuator with AGC Support (Detection/Gain Control)

High Dynamic Range SDADC
On-chip DSP includes QDDC and Decimation filters
I/Q 16-bit data via 1 or 2 lane JESD204B interface
Optional Clock Synthesizer (2.94-3.2 GHz operation)
Power

Consumption of 1.2 W (w/ 1.1 V and 2.5 V supplies

Mixer-to-bits
19

Rx chain of < 2 W (w/ mixer+PLL/VCO)

What is the AD6676?

Only conceptual, inherent
in the SD ADC design

Analog

(cont.)

Digital
I

ATT

ADC CORE

QDDC

Decimation
filter

JESD204B
Serializer

Quadrature Downconversion
and Digital Filtering

Inherent Anti-alias Filter

Quantization Noise Shaping

20

Reconfigurable BP SD ADC
Application Parameters

21

NSD vs Oversampling Ratio Trade-off

Higher

OSR results in lower NSD performance

Lower/Upper

Zeros of NTF become further a part

Less forward gain in feedback loop to suppress ADC
quantization noise (recall only 17-level ADC).

22

Profile Feature allows up to 4 different

IF/BW combinations
User

quickly switch between different pre-saved ADC

configurations (i.e. Wideband vs Narrowband Modes)
Calibration of each profile configuration done at power-up

23

Digital Processing Blocks

QDDC
Dec

(Coarse/Fine) followed by selectable Decimation Filters

Factors of 12, 16, 24, and 32

AGC/Overload

24

Detection and Control.

Want to Learn More? Visit the AD6676 Website

http://www.analog.com/ad6676

LIVE
WEB DEMO
TOOL!!

25

Try Before You Buy!!!

AD6676 Remote Test Tool

26

AD6676 Remote Test Tool Capability

Single-Tone

Frequency Sweep

27

Dual-Tone

Spurious vs Frequency Sweep

Not Shown: In-band Noise vs Amp Sweep

AD6676 Evaluation Platform

Plug

and Play and User-friendly FMC-Compatible EVB

Requires

no external generators/supplies to get operational!

Sophisticated
Provides

Evaluation SW based on MATLAB Executable

various analysis tools: enables detailed customer evaluation

Saves SPI initialization files for rapid software development

28

AD6676 Evaluation Platform

Sophisticated

(cont.)

Evaluation SW based on MATLAB Executable

Provides various analysis tools: enables detailed customer evaluation

Saves SPI initialization files for rapid software development

29

Support Rapid FPGA Proto-typing with

AD6676 FMC EVB
Facilitate

transition from AD6676 evaluation to

software/firmware development using same EVB

Dedicated

Wiki page includes HDL firmware, software,

documentation.

30

FPGA HDL Code and Linux Drivers

http://wiki.analog.com/resources/tools-software/linuxdrivers/iio-adc/ad6676

https://github.com/analogdevicesinc/hdl/tree/dev/projects/ad6676evb

31

Product Availability

AD6676
Samples:

Now

Production

Quantities:
AD6676BCBZRL
1K pricing
AD6676BCBZRL
Evaluation and Prototyping Boards:
AD6676EBZ
HSC-ADC-EVALEZ data capture kit

32

http://www.analog.com/AD6676

Now
$145
$395
$750

Thank You For Watching

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