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CHNG 3
Register Transfer
Specification And Design

Register-transfer design
Each standard or custom IC consists of one or more

datapaths and control units.


To synthesize such IC we introduce the model of a FSM
with a datapath (FSMD).
We demonstrate synthesis algorithms for FSMD model,
including component selection, resource sharing,
pipelining and scheduling.

Example

Design Model

High-level block diagram

Register-transfer-level block diagram

Ones-counter specification

FSDM Definition
In Chapter 6 we defined an FSM as a quintuple < S, I, O, f, h >
o where S is a set of states, I and O are the sets of input and output
symbols: f : S I S , and h : S I O
o More precisely, I
A = A1 A2 Ak
S = Q1 Q2 Qm
O = Y1 Y2 Yn

Where Ai 1 i k , is an input signal, Qi, 1 i m is the flip-

flop output and Yi, 1 i n is an output signal.


To define a FSMD, we define a set of variables V = V1 V2
Vq. which defines the state of the datapath by defining the
values of all variables in each state.
where IC = A1 A2 Ak as before and ID = B1 B2 Bp,
Where OC = Y1 Y2 Yn as before and OD = Z1 Z2 Zr.

FSDM Definition
With formal definition of expressions and relations over a

set of variables we can simplify function f : ( S V ) I


S V by separating it into two parts: fC and fD. The
function fC defines the next state of the control unit
fC : S IC STAT S
while the function fD defines the values of datapath
variables in the next state
fD : S V ID V
fD :={fDi : V ID V : { Vj =ej | Vj V, ej Expr ( V ID )}}
Also,
hC : S IC STAT OC
and
hD : S V ID OD

FSMD specification of Ones-counter

State and output table

FSMD specification of Ones-counter

State and output table with


variable assignments
State and output table

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FSMD specification of Ones-counter

State-action table

State and output table

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Algorithmic-State-Machine
Graphic representation of FSMD model
Equivalent to state-action table
Similar to a flowchart used for program description

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ASM Symbols

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ASM rules
Rule 1: The chart must define a unique next state for

each state and set of conditions.


Rule 2: Every path defined by the network of condition
boxes must lead to another state.

Undefined next state

Undefined exit path

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ASM chart for Ones-counter

(b) Input-based (Mealy) chart


(a) State-based (Moore) chart

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State-action tables for Ones-counter


D2 = Q2(next) = s2DataLSB + S3 + S4(Data 0)
= Q1Q0DataLSB + Q1Q0 + Q2Q0(Data 0)
D1 = Q1(next) = s1 + s2DataLSB + s4(Data 0)
= Q2Q1Q0 + Q1Q0DataLSB + Q2Q0(Data 0)
D0 = Q0(next) = s0Start + s2DataLSB + s4(Data 0)
= Q2Q1Q0Start+Q1Q0DataLSB+Q2Q0(Data 0)

State-based table

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State-action tables for Ones-counter


D1 = Q1 ( next ) = s1+s2 = Q1Q0 + Q1Q0
D0 = Q0 ( next ) = s0Start + s2( Data 0 )
= Q1Q0Start + Q1Q0 ( Data 0 )

Input-based table

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Logic schematics for Ones-counter


D2 = Q2(next) = s2DataLSB + S3 + S4(Data 0)
= Q1Q0DataLSB + Q1Q0 + Q2Q0(Data 0)
D1 = Q1(next) = s1 + s2DataLSB + s4(Data 0)
= Q2Q1Q0 + Q1Q0DataLSB + Q2Q0(Data 0)
D0 = Q0(next) = s0Start + s2DataLSB + s4(Data 0)
= Q2Q1Q0Start+Q1Q0DataLSB+Q2Q0(Data 0)

S1= s4 =Q2Q0
S0 = s2 + s4 = Q1Q0 + Q2Q0
E = s3 = Q1Q0
Load =s1 = Q2Q1Q0
Done = Output enable = s5 = Q2Q0

State-based version

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Logic schematics for Ones-counter


D1 = Q1 ( next ) = s1+s2 = Q1Q0 + Q1Q0
D0 = Q0 ( next ) = s0Start + s2( Data 0 )
= Q1Q0Start + Q1Q0 ( Data 0 )
S1 =s2( Data 0 ) = Q1Q0( Data 0 )
S0 = s1 + s2( Data 0 ) = Q1Q0 + Q1Q0( Data 0 )
E = s2DataLSB = Q1Q0DataLSB
Load = s1 = Q1Q0
Done = Output enable = s3= Q1Q0

Input-based version

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Bi tp
Vit lc gii thut ASM cho bi sau: S = 1 + 2 + 3 +

+n
Vit lc gii thut ASM cho gii thut sau:

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Bi tp
Thit k lc ASM cho b nhn mc vt l ca 3

thanh ghi:

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Bi tp
Chuyn lc trng thi sau sang lc gii thut

ASM moore (ASM da trn trng thi)


Reset

w = 1
w = 0

A z = 0

B z = 0

w = 0
w = 1

w = 0

C z = 1

w = 1

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Bi tp
Chuyn lc sau sang gii thut ASM mealy

Reset
w = 1 z = 0
w = 0 z = 0

B
w = 0 z = 0

w = 1 z = 1

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Bi tp
Cho lc ASM sau. Hy v li lc trng thi (xc

nh ASM thuc dng no: da trn trng thi hay da


Reset
trn input):
Idle

r1

1
gnt1

1
g1

r2

gnt2
g2

r3

r1

r2

1
1

gnt3
g3

0
r3

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Register-transfer synthesis
Register sharing

Functional unit sharing


Bus sharing
(a2+b2)1/2 = max((0,875x+0,5y),x)
x = max (a,b)
y = min (a,b)
ASM Chart of Square-root approximation

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Resource usage in square-root approximation

Variable usage

ASM Chart of Square-root approximation

Operation usage

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Simple library components


a) Absolute value unit
(version 1)

(c) Min unit

b) Absolute value unit


(version 2)

(d) Max unit

(e) Min/Max unit

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Simple library components

(f) 1-bit right shifter

(g) 3-bit right shifter

(i) Adder

(j) Subtractor

(h) 1-bit/3-bit right shifter

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Connectivity requirements

Connectivity table

ASM Chart of Square-root approximation

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Register sharing (Variable merging)


Grouping of variables with nonoverlaping lifetimes
Each group shares one register
Grouping reduces number of registers needed in the

design
Two algorithms:
o left-edge
o graph-partitioning

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Left-edge algorithm

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Register sharing by left-edge algorithm


R1 = {a, t1, x, t7}
R2 = {b, t2, y, t4, t6}
R3 = {t2, t5 }
Register assignments

Sorted list of variables

Datapath schematic

ASM Chart

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Merging variables with common Source and destination

Partial ASM Chart

Datapath with register sharing


Datapath without register sharing

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Graph partitioning algorithm

(a) Initial compatibility graph


Cnh u tin ni 2 node trng lp thi gian
Cnh khng thch hp ni 2 node bng ng nt t
s/d
s-number of shared functional units served at inputs,
d-number of shared functional units servedat outputs.

Chc nng n v ca cc b: B tr tuyt i (1 func), +/- (1 function), min/max


(1 function), shift 1/3 (1 function) (nh slide 25, 26)

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Graph partitioning algorithm for SRA


(a) Initial compatibility
graph
(b) Compatibility graph
after merging t3, t5
and t6
(c) Compatibility graph
after merging t1, x
and t7
(d) Compatibility graph
after merging t2 and y

(e) Final compatibility


graph
ASM Chart

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Register assignment generated by the graph-partitioning algorithm

R1 = [ a , t1 , x , t7 ]
R2 =[b , t2 , y , t3 , t5 , t6 ]
R3= [ t4 ]
Register assignments

Datapath

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Functional unit sharing (operator merging)


Group non-concurrent operations
Each group shares one functional unit
Sharing reduces number of functional units
Prioritized grouping by reducing connectivity
Clustering algorithm used for grouping

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Functional unit sharing

Partial ASM Chart

Non-shared design

Shared design

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Complex library components

Unit for computing minimum,


maximum and absolute value

Unit for computing addition,


subtraction, minimum and maximum

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Complex library components

Unit for computing addition,


subtraction, and absolute value

Unit for computing addition, subtraction,


minimum, maximum and absolute value

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Operator merging for SRA implementation

(a) Compatibiltity graph

(b) Cost table

(c) Merging altermative


(d) Cost table
ASM Chart

(e) Merging altermative

(f) Cost table

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Datapath connectivity

(a) Datapath schematic for unit allocation from figure 8.22 (c)

ASM Chart

(b) Datapath schematic for unit allocation from figure 8.22 (e)

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Priorities in unit merging

(a) Partial ASM Chart


(b) Design without merged units

(c) Design with merged units

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Unit merging for SRA datapath

(a) Compatibility graph

(c) Compatibility graph


after merging of min, + and _

(b) Compatibility graph


after merging of + and -

(d) Final graph partitions

R1 = [ a, t1, x, t7 ]
R2 = [ b, t2, y, t3, t5, t6 ]
R3 = [ t4 ASM
] Chart

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SRA datapath generated by prioritized partitioning


R1 = [ a, t1, x, t7 ]
R2 = [ b, t2, y, t3, t5, t6 ]
R3 = [ t4 ]

AU1 = [ |b| / min / + / - ]


AU2 = [ |a| / max /]
SH1 = [ >>1 ]
SH2 = [ >>3 ]

(a) Register and functional unit allocation

(b) Datapath schematic

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Bus sharing ( connection merging )


Group connections that are not used concurrently
Each group forms a bus
Connection merging reduces number of wires
Clustering algorithm is demonstrated

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Connection merging in SRA datapath


Bus1 = [ A, C, D, E, H ]
Bus2 = [ B, F, G ]
Bus3= [ I, K, M ]
Bus4 = [ J, L, N ]
(e) Bus assignment

(b) Connectivity usage table

(c) Compatibility graph


for input buses

(d) Compatibility graph


for output buses

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Connection merging in SRA datapath


Bus1 = [ A, C, D, E, H ]
Bus2 = [ B, F, G ]
Bus3= [ I, K, M ]
Bus4 = [ J, L, N ]
Bus assignment

(f) Bus oriented datapath

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Chapter summary
We introduced RT design:
o FSMD model
o RT specification with
Static-action
ASM

tables

charts

Procedure for synthesis from RT specification


Design Optimization through
o Register sharing
o Functional unit sharing
o Bus sharing

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Bi tp
Ti thiu ha s lng thanh ghi s dng cho cc bin t

t1 t8 s dng gii thut left-edge. Bit thi gian sng


ca bin cho bng sau:

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Bi Tp
Gom nhm cc node bng gii thut th thch hp. Gi

s trng s ca cc cnh u tin trong supernode bng


tng trong s ca cnh u tin ca mi node trong
supernode

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Bi Tp
Cho php ton S = 1 + 2 + 3 + + n. Thc hin cc

bc sau:
o Vit gii thut thc hin php ton trn.
o Chuyn m gi sang lc ASM (based state hoc based

input).
o S dng gii thut left-edge algorithm hin thc hin chia s
thanh ghi.
o S dng gii thut phn hoch th (partition graph) thc hin
chia s chc nng (Function unit).
o S dng gii thut phn hoch th (partition graph) thc hin
chia s bus.

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Bi tp
Vit chng trnh to datapath tnh tng a2i (i = 1 .. 100).
o Vit gii thut bng m gi.
o Chuyn m gi sang s ASM.
o Lp bng trng thi
o Chia s thanh ghi ?(nu c).
o Chia s chc nng ?(nu c).
o Chia s bus ?(nu c).