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Abstract
A 64kb cache system designed for 32 bit RISC CPU is
realized. The circuits include two 4ns 32kb cache
memories, two 1.4ns 64-entry direct mapped translation
lookaside buffers (TLB), and two 2ns 64-lines tagRAM.
The high-speed decoder and amplifier are employed. The
TLB design contains a line encoder and valid bits with
flash clear. This cache memory reduces the power and
has faster access time by using the optimized decoder
and sense amplifier. SMARCH algorithm makes all the
cache system self-testability.
Cache Architecture
A cache is a high-speed memory store which contains
the instructions and data most likely to be needed by the
processor. Cache divided into instruction and data
section allows the processor simultaneous access to both
instructions and data, thereby doubling the effective
cache-memory bandwidth. If the processor issues a
reference to an item contained in the cache. Then a zero
wait-state access is made; If the reference is not
contained in the cache, then the longer latency associated
with the true processor memory is incurred. Caches rely
on the principles of locality of software. These principles
state that when a datdinstruction element is used by a
processor, it and its close neighbors are likely to be used
again soon.
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Circuit Design
Cache memories in processor system need high-speed
low-power SRAM, because the performance of
processor system is primarily affected by the cache
memories. SRAM with higher speed are always in
demand [l]. The access time for SRAM mainly includes
the delay time of the decoder and the delay time of the
sense amplifier circuits. With the optimized trade-off
decoder and amplifier scheme cache will obtain not only
high speed but also low power. A large portion of cache
energy is dissipated in driving the bitlines, which are
heavily loaded with multiple storage cells. Hence some
energy reduction techniques such as bit equilibration and
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566
In order to make it possible for the cache to offer highspeed low-power consumption and higher integration,
several circuit design technologies are introduced. TO
begin with a block scheme is described in the first
section, which effectively lower the power of cache
memories. Secondly, a decoder structure is introduced.
Thirdly, an optimized sense amplifier is discussed, and
built-in-self-test circuit is shown at last.
Divided Word Line Technology
During an access to some row of memory, the word line
activates all the cells in that row and the desired subword is accessed via the column multiplexers. This
arrangement has two drawbacks: the word line RC delay
grows as the square of the number of cells in the row
increases, and bitline power grows linearly with the
number of columns. Both these drawbacks can be
overcome by dividing the memory into smaller blocks of
cells using the Divided Word Line (DWL) technique,
which is first proposed by Yoshimoto, et.al. in [3]. In the
DWL technique the long word line of a conventional
array is broken up into k sections, with each section
activated independently, thus reducing the word line
length by k and reducing its RC delay by p. This
method has been widely used to realize high speed and
reduce power consumption.
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Sense Amplifier
A sense amplifier is also an important part to obtain
faster access time. The circuit schematic of the sense
amplifier is shown in Fig 4. The sense amplifier contains
two stages. The first stage is a modified current-mirror
circuit to which two additional p-channel transistors
567
Chip Performance
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512 X 32bits
Technology
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References
[I] Hiraki Nambu, Kazno Kanetani, A 1 . h access,
550MHz, 4.5Mb CMOS SRAM, IEEE journal of
solid-state circuits, 33, 11, (1998).
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