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SAP-1

Microcomputer
(Simple As Possible)
Architecture

UST-ECE COMP305
engradc (c) 2009

Program
Counter

W bus
8

Accumulator
A

LA
CLK
EA

CP
CLK
CLR
EP

SU

LM
Input and MAR
4

Instruction
Register

Adder/
Subtracter

B
Register

Output
Register
8

LI
CLK
CLR
EI

16 x 8
RAM

CE

UST-ECE COMP305
engradc (c) 2009

12

Controller/
Sequencer

EU

CLK

CLK
CLK
CLR
CLR

CPEPLMCE LIEILAEA SUEULBLO

Binary
Display

LB
CLK

LO
CLK

Program Counter

Part of control unit that counts from 0000


to 1111.

Its job is to send to the memory the


address of the next instruction to be
fetched and executed.

It is also known as instruction pointer.

UST-ECE COMP305
engradc (c) 2009

BACK

Input and MAR


It includes address and data switch
registers.
Switch register allow you to send 4
address bits and 8 data bits to the RAM.
The memory address register (MAR) is
part of SAP-1 memory.

BACK
UST-ECE COMP305
engradc (c) 2009

RAM (Random Access Memory)

The RAM is 16 x 8 static TTL RAM.

It allows to store a program and data in the


memory before a computer run.

UST-ECE COMP305
engradc (c) 2009

BACK

Instruction Register
It is part of control unit.
The contents of the instruction register are
split into two nibbles. The upper nibble is a
two - state output that goes directly to the
block labeled controller/sequencer. The
lower nibble is a three-state output that is
read onto the W bus when needed.

UST-ECE COMP305
engradc (c) 2009

BACK

Controller-Sequencer

The 12 bits that come out of the controllersequencer form a word controlling the rest
of the computer. The 12 bits are called
control word/ control bus.

CON = CPEPLMCE LIEILAEA SUEULBLO

UST-ECE COMP305
engradc (c) 2009

BACK

Accumulator (A)
It is a buffer register that stores
intermediate answers during a computer
run.
It has two outputs; the two-state output
goes to the adder/subtracter, the threestate output goes to the W bus.

UST-ECE COMP305
engradc (c) 2009

BACK

Adder / Subtractor
When SU is low it will perform addition,
otherwise subtraction.
The adder/subtracter is asynchronous; its
contents can change as soon as the input
words change.

UST-ECE COMP305
engradc (c) 2009

BACK

B Register
It is another buffer register, used in
arithmetic operations.
The two-state output of the B register
drives the adder/subtracter, supplying the
number to be added or subtrahend from
the contents of the accumulator.

UST-ECE COMP305
engradc (c) 2009

BACK

Output Register

The output register is often called an


output port because processed data can
leave the computer through this register.

UST-ECE COMP305
engradc (c) 2009

BACK

Binary Display

It is a row of 8 light emitting diodes, it


shows the contents of the output
register/port.

The result displayed is in the binary form.

UST-ECE COMP305
engradc (c) 2009

BACK

SAP-1 INSTRUCTION SET

LDA (Load Accumulator)


LDA

ADD (Add)
ADD

8H
9H

SUB (Subtract)
SUB

OUT

HLT

UST-ECE COMP305
engradc (c) 2009

AH

MEMORY REFERENCE
INSTRUCTIONS

LDA

ADD

SUB

UST-ECE COMP305
engradc (c) 2009

INSTRUCTION SET
SUMMARY
Mnemonic

Operations

LDA

Load RAM data into accumulator

ADD

Add RAM data to accumulator

SUB

Subtract RAM data from accumulator

OUT

Load accumulator data into output


register

HLT

Stop processing

UST-ECE COMP305
engradc (c) 2009

SAP-1 Programming
Mnemonic

UST-ECE COMP305
engradc (c) 2009

LDA

Operation Code
(Op-code)
0000

ADD

0001

SUB

0010

OUT

1110

HLT

1111

SAP-1 Programming

Instruction = XXXX XXXX


Instruction field
Address field

Example:

UST-ECE COMP305
engradc (c) 2009

ADD 9H 0001 1001

SAP-1 Programming
Assembly Language

LDA FH
ADD EH
HLT
Source Program
UST-ECE COMP305
engradc (c) 2009

Machine Language

0000 1111
0001 1110
1111 XXXX
Object Program

SAP-1 INSTRUCTION CYCLE

Fetch Cycle
Address

State
Increment State
Memory State

Execution Cycle

UST-ECE COMP305
engradc (c) 2009

Clk
t1
t1

t2

t3

t4

t5

t6
UST-ECE COMP305
engradc (c) 2009

t2

t3

t4

t5

t6

t7

Address State (t1)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUTPUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

Increment State (t2)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUTPUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

Memory State (t3)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

LDA (t4)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

LDA (t5)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

LDA (t6)
PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON
UST-ECE COMP305
engradc (c) 2009

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

ADD/SUB (t4)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

ADD/SUB (t5)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

ADD/SUB (t6)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

OUT (t4)

UST-ECE COMP305
engradc (c) 2009

PC

ACC

MAR

ADDER
SUBTRACTER

RAM

B
REG

IR

OUT
REG

CON

DISPLAY

CPEPLMCE LIEILAEA SUEULBLO

SAP-1 FETCH Micro-operation

STATE

CON

ACTIVE BITS

t1

5E3H

EP, LM

t2

BE3H

CP

t3

263H

CE, LI
BACK

UST-ECE COMP305
engradc (c) 2009

SAP-1 EXECUTE Micro-operation


MACRO

State

CON

ACTIVE

LDA

t4

1A3H

LM, EI

t5

2C3H

CE, LA

t6

3E3H

NONE

t4

1A3H

LM,EI

t5

2E1H

CE, LB

t6

3C7H

LA,EU

t4

1A3H

LM,EI

t5

2E1H

CE,LB

t6

3CFH

LA, SU,EU

t4

3F2H

EA,LO

t5

3E3H

NONE

t6

3E3H

NONE

ADD

SUB

OUT

UST-ECE COMP305
engradc (c) 2009

Machine Cycle

Number of clock cycles needed to


complete one fetch and execute cycle.

Eg. In SAP-1 the six T-states is the


machine cycle

UST-ECE COMP305
engradc (c) 2009

Instruction Cycle
Number of clock cycles needed to finish
the fetch and execute cycle of an
instruction
Instruction cycle > Machine cycle

Eg. In SAP-1, the


machine cycle = instruction cycle

UST-ECE COMP305
engradc (c) 2009

Problems
Write an assembly-language program that
performs this operation:
8 + 4 -3 + 5 2
(Use addresses BH to FH for the data)
Convert the program and data in the
previous program into machine language.
Express the result in both binary and
hexadecimal form.

UST-ECE COMP305
engradc (c) 2009