LabVIEW FPGA unleashed: FlexRIO!

Filippo Persia
ATE & RF Systems Engineer
Agenda
• Introduction to FPGAs in Test & Measurement
• LabVIEW FPGA 2009: more power
ƒ CLIP Node
ƒ NI Labs Additional Features
• FPGA for T&M hardware: FlexRIO
ƒ Architecture
ƒ Designing custom I/O adapter modules
 Software Defined System Architecture
Software-Defined
Standard Virtual Bus Interface Measurementt
M
and I/O Analog or
Instrumentation Digital
Control
Model NI LabVIEW Driver Front End
Software Hardware

10011011
 FPGA Based System Architecture
FPGA-Based
Bus Interface/
Open Programmable Measurement
FPGA FPGA Analog or
Digital
System Front End
Model LabVIEW Driver
Software NI Hardware

• System intelligence and decision making can be

movedd from
f software
ft tto hardware
h d
 Benefits of FPGAs in T&M Systems
• High Reliability – Designs implemented in hardware
• Low Latency – Run algorithms at deterministic rates
d
down tto 5 ns
• Reconfigurable – Create application-specific
personalities
• High
g Performance – Computational
p abilities open
p new
possibilities for measurement and data processing speed
• True Parallelism – Enables parallel tasks and pipelining,
pipelining
reducing test times
FPGA for Test Application
pp Areas
• Real-time / co-processing
p g
Processing • Data reduction / in-line processing

• Protocol-aware ATE
Protocols • Interfacing (digital or modulated)

Closed-Loop • Response-stimulus test

Test • Hardware-in-the-loop
Hardware in the loop (HIL)

Test System • Digital DUT interfacing and command

Control • Complex triggers
LabVIEW FPGA: from LabVIEW to HW

Translation Optimization Synthesis Bit Stream

VHDL Generation Analysis Place and Route Generation

Logic Reduction Timing Verification Download / Run
 LabVIEW FPGA Historyy

RIO IF Transceiver
LabVIEW FPGA  Virtex‐5 R Series
LabVIEW FPGA & 
demonstrated at
demonstrated at  R Series Released
NI Week Lots of 
cRIO stuff! FlexRIO
CompactRIO sbRIO

‘97 ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09

Traditional FPGA Design Flow
LVFPGA Design Flow
Why Use LabVIEW FPGA?
G ?
• No HDL experience needed
• No low FPGA or PCB design
• Results comparable in size and speed to HDL
• Everything in one software environment
ƒ Faster code development
ƒ Easier testbench creation
• Faster FPGA code simulation
 Advancements in LabVIEW FPGA

DRAM support
IP Integration (CLIP node)
IP Integration (CLIP node)
External Clocks*
Peer‐to‐Peer Streaming*
p
DMA Transfer rates up to 800MB/s*
Up to 16 DMA channels per device*

*on selected targets
What Is a CLIP?

• Component Level Intellectual Property

• A CLIP is a concept that allows users to add
their own custom HDL code to a LabVIEW FPGA
project
• CLIPs
CLIP are Component
C t Level
L l because
b the
th HDL
code executes in parallel to the LV FPGA VI
Component
p Level IP (CLIP)
( ) Goals
• Run HDL code in parallel with LabVIEW code
• Including custom constraints file
• Facilitate insertion of third-party IP
• Execute HDL in multiple clock domains
• Facilitate high-speed
g p interface design g
• Access FPGA pins directly from CLIP HDL
• Exercise
e c se spec
specificc features
eatu es oof tthee FPGA
G (Se
(SerDesblocks,
esb oc s,
various differential I/O standards)
• Provide flexible communication ppath between CLIP
node and LVFPGA
FPGA for Test Hardware
N ti l IInstruments
National t t FlexRIO
Fl RIO

LabVIEW FPGA-Enabled Instrumentation

 NI FlexRIO System Architecture

PXI

NI FlexRIO Adapter Module NI FlexRIO FPGA Module PXI Platform

• Interchangeable I/O • Virtex-5 FPGA • Synchronization
• Customizable by users • 132 digital I/O lines • Clocking/triggers
• Adapter Module • 128 MB off DDR2 DRAM • Power/cooling
/
Development Kit (MDK) • Data streaming
NI FlexRIO FPGA Modules for PXI
• Virtex
Virtex-55 FPGA
ƒ LX30, LX50, LX85, LX110
• Direct access to FPGA I/O
ƒ 132 single-ended lines or 66
differential pairs
ƒ 400 Mbps single-ended
single ended
ƒ 1 Gbps differential
• 128 MB onboard DRAM
ƒ 2x 64 MB banks
ƒ 800 MB/s per bank
• Adapter module required for IO
 FlexRIO - CLIPs
PXI‐795x FPGA
PXI‐795x FPGA User 
User User 
User User 
User
CLIP CLIP CLIP

Terminaal Blocck
Socketeed CLIP
PXI Bus
PXI Bus LabVIEW FPGA VI
LabVIEW FPGA VI

P
Socketed CLIP Socketed CLIP

DRAM DRAM
Adding a CLIP to the LabVIEW Project
• CLIP Node Files:
ƒ IP source code (HDL, netlists, coregen)
ƒ Constraints file (optional)
ƒ XML file
• Describes the interface between the CLIP and
LabVIEW
• Identifies ppath to source code
Adding
g a CLIP to the LabVIEW Project
j
AnalogFrontEndCLIP.vhd
entity AnalogFrontEnd is
port (
adcCh0_LV : out std_logic_vector(15 downto 0);
adcCh0_TB : in std_logic_vector(15 downto 0) := x"0000"
);
end AnalogFrontEnd;

architecture rtl of AnalogFrontEnd is

begin

adcCh0_LV <= adcCh0_TB;

...

end rtl; AnalogFrontEndCLIP.xml

l d l
<?xml version="1.0" encoding="utf-8"?>
<CLIPDeclaration Name=“AnalogFrontEnd">
<HDLName>AnalogFrontEnd</HDLName>

<InterfaceList>
<I t f Li t>
<Interface Name=“AnalogIO">
<InterfaceType>LabVIEW</InterfaceType>
<Signal Name=“ADC Ch0_LV">
<HDLName>adcCh0_LV</HDLName>
<DataType><I16/></DataType>
<Direction>FromCLIP</Direction>
<SignalType>data</SignalType>
</Signal>
</Interface>
</InterfaceList>
</CLIPDeclaration>
Adding
g a CLIP to the LabVIEW Project
j
Demo: reuse a DDS Netlist
NI FlexRIO Adapter Module

• C
Cardd edge
d connector t
• Defines I/O for NI
LabVIEW FPGA
• Self identification
• Custom connectivityy
• Adapter Module
Development Kit (MDK)
 NI FlexRIO Adapter Module Options
Third-Party
Thi dP t Custom
C t
NI Modules
Modules Modules
• Complete • Expands NI • Requires PCB
integration with I/O breadth and HDL design
LabVIEW FPGA • Custom and work
• R Series-like application- • Supported
experience specific modules through MDK
NI 6581
High-Speed Digital Adapter Module
ƒ 100 MHz digital I/O
ƒ 54 single-ended
g channels
ƒ Selectable voltage levels
ƒ 1.8,
1 8 2.5,
2 5 33.33 V (5 V compatible)
ƒ External DIO voltage reference
Voltage Reference

Data Out
DDC
Output Enable
Data In NI 6581
NI 6581 - CLIPs

• Channel • Both CLIPs

ƒ Write to or read from
individual DIO lines
• Port
ƒ Write to or read from an 8
bit port
ƒ Internal or external
clocking (invert clock)
ƒ I t
Internall or external
t l power
supply
ƒ Selectable internal logic
level (1.8, 2.5, 3.3 V)

You can have multiple CLIPs per Adapter Module

 NI 6585
200 MHz LVDS Digital Instrument
ƒ 200 MHz digital I/O
ƒ 32 / 42 LVDS channels
ƒ 200 Mbps SDR,
SDR 300 Mbps DDR

PXI-6585R
NI FlexRIO Partner Modules

• Gigabit Ethernet interfaces • Camera Link Interface

• MAC and Ethernet frames • High-speed image processing
• Fault-injection software • Low-latency control

• IEEE-1394b interface • 100 MHz vector digital I/O

• 3 ports at 800 Mbps • 8 ch.
ch per-pin
per pin PMU
 Custom NI FlexRIO Adapter
p Module
Development Kit (MDK)
• 6 W Power – electrical and thermal limit
• 3.3
3 3 V (1 A) and 12 V (200 mA) rails
• LVTTL (3.3 V), LVCMOS (1.2, 1.5, 1.8, 2.5, 3.3 V),
LVDCI (1.5, 1.8 V, 2.5, 3.3 V), LVDS (2.5 V)
ƒ 400 Mbps (Single-Ended), 1 Gbps (Differential)
• I2C EEPROM for module identification and user user-
defined storage
• NI Mechanical Enclosures
Requirements
• MDK
ƒ Documentation
ƒ Access to private email address for support
ƒ PCB layout review
• VHDL programming (good level)
• High-Speed PCB layout experience
 Bring Up your Adapter Module

Create or acquire the

socketed CLIP to create
the FPGA/AM interface
Program the IO Module Create the AM • Create or acquire IP Configure the AM in a
ID into the EEPROM configuration (.tbc) file • Generate optional constraints LabVIEW project
• Create Declaration File
Program EEPROM
Program ID Confirm ID
• IO Module ID
• Vendor ID 0xFFFF0001
ƒ Differentiates vendors Vendor ID Prod ct ID
Product
ƒ NI Vendor ID: 0x1093
• Product ID
ƒ Differentiates
e e t ates modules
odu es from
o sa
samee vendor
e do
Program EEPROM

• Optional Parameters
ƒ Serial Number
ƒ User Space
Byte Address Size (Bytes) Field Name Required?
0x0 2 Vendor ID Yes
0x2 2 Product ID Yes
0x4 4 Serial Number No
0x8 24 Reserved No
0x20 224 User Space No
Adapter Module Interface Protocol

• Manages safe adapter module insertion/removal

ƒ At insertion:
• Verifies inserted module matches FPGA bitstream
settings – prevents incompatible IO directions and
voltages
• Enables power supplies and then FPGA outputs
ƒ At removal:
• Disables FPGA outputs and all power rails
 Adapter Module ID Process

1. Check TB_Present_n
ƒ Adapter Module Inserted
ƒ Software forced redetect
ƒ System power up or FPGA download
2. Enable Veeprom
3. Read EEPROM ID, check bitstream for match
4
4. E bl allll power rails
Enable il
5. Wait for TB_Power_Good
6
6. Set CLIP signal rIoModGpioEn high
ƒ Allows CLIP to enable outputs and BUFGCE safely
Adapter Module Configuration File
• Important part of Adapter Module development
• Configure VCCOA and VCCOB
ƒ Ensures proper bank voltages
• Determine Module ID
ƒ Used by LabVIEW project

Add d to
Added t UCF dduring
i compilation
il ti
Virtex 5 FPGA IO Bank Voltage
• User I/O Pins are Divided into 4 Banks
• Each bank is powered by VccoA or VccoB
• Consider Necessary Logic Levels When
Choosingg How to Divide the Voltage
g Banks
GPIO Bank Mapping on Virtex 5

GPIO Banks
FPGA IO Standards
• Xilinx FPGA IO Blocks support several IO
St d d
Standards
• FlexRIO GPIO support
pp a subset of these IO
Standards, including:
IO Standard Vcco
LVTTL 3 3V
3.3V
LVCMOS__ 1.2V, 1.5V, 1.8V, 2.5V, 3.3V
LVDCI__ (DCI R = 50Ω) 1.5V, 1.8V, 2.5V, 3.3V
LVDS_25 (inputs use internal 100Ω) 2.5V

• IO Standards
St d d may be b mixed
i d within
ithi a bank,
b k if
Vcco voltages are the same
• See Virtex 5 User Guide for more details
Example .tbc File
[General]
FormatVersion=1 0
FormatVersion=1.0
Manufacturer=National Instruments
Model=NI 5681
Basic adapter module info
Description= National Instruments IF module
V
VccoALevel=2.5
AL l 2 5
VccoBLevel=3.3
Set Logic Levels: must match I/O Standard constraint
IOModuleID=0x10935681
Used by LV project
DefaultCLIP=IFModuleClip

[Constraints]
INST "*Ibufd*" DIFF_TERM = TRUE; Additional Xilinx Physical Interface Constraints
INST "*Ibufgd*" DIFF_TERM = TRUE;

# Bank 0 & 1: 2.5V

NET "aUserGpio<0>" IOSTANDARD = LVDS_25;
NET "aUserGpio_n<0>" IOSTANDARD = LVDS_25;
NET "aUserGpio<19>" IOSTANDARD = LVDCI_25;
# Bank 2 & 3: 3.3V
NET "aUserGpio<33>" IOSTANDARD = LVDCI_33;
Adapter Module CLIP Socket
• Provides indirect access to
external I/O PXI‐795x FPGA

A
Adapte
So
Interchangeable I/O

ocketeed CLIP
ƒ
hardware defines the FPGA
to hardware interface
LabVIEW 

er Mo
PXI Bus
ƒ The user defines FPGA VI
representation of hardware

odule
P
in LabVIEW
Socketed  Socketed 
• Allows for use of specific CLIP CLIP
FPGA
G I/O
/O ffeatures
DRAM DRAM
Implementing Socketed CLIP

Create or Acquire IP

Create Constraints (if needed)

Create CLIP Declaration XML File

Add CLIP to LV FPGA project

Implementing Socketed CLIPs

• Create or Acquire IP
ƒ Fixed hardware interface (GPIO, etc)
ƒ Shared I2C bus
Adapter
p Module Socket Signals
g
Signal Name Direction Data Type
aUserGpio Bidirectional std_logic_vector(65 downto 0)
aUserGpio_n
p Bidirectional std_logic_vector(65
g ( downto 0))
rIoModGpioEn To CLIP std_logic
UserGClkLvds To CLIP std_logic
UserGClkLvds_n To CLIP std_logic
UserGClkLvttl To CLIP std_logic

Signal
g Name Direction Data Type
yp
IoModClipClock0 From CLIP std_logic
IoModClipClock1 From CLIP std_logic
Shared I2C Bus
• Share bus with
Signal Name Direction Data Type
ƒ Socketed CLIP rLvFpgaReqI2cBus From CLIP std_logic

ƒ FlexRIO fixed logic rLvFpgaAcqI2cBus To CLIP std_logic

rLvFpgaI2cGo From CLIP std_logic
ƒ FlexRIO Host VIs rLvFpgaI2cStart From CLIP std_logic

• Signals must be present rLvFpgaI2cStop

rLvFpgaI2cRd
From CLIP
From CLIP
std_logic
std_logic
in CLIP rLvFpgaI2cWtData From CLIP std_logic_vector(7 downto 0)
rLvFpgaI2cAck To CLIP std_logic
• All I2C signals are rClktoSocket To CLIP std_logic (or boolean)

synchronous to 40MHz rLvFpgaI2cDone To CLIP std_logic

rLvFpgaI2cRdData To CLIP std_logic_vector(7 downto 0)
RioClk
 Demo: AD9752 TxDAC as Adapter

HSDIO Cable

GPIO 0:11 +
clock DDR

Demo PCB NI 6581 “buffer only”

AD9752
TxDAC
Custom Adapter
NI 9999
Upcoming
p g NI FlexRIO Adapter
p Modules
Digitizer Module Baseband Transceiver
• 250 MS/s,
MS/s 4 ch.,
ch 1414-bit
bit • 100 MS/s,
MS/s 2 ch.,
ch 1414-bit
bit ADC
• AC or DC coupled • 100 MS/s, 2 ch., 16-bit DAC
• Q4 2009/ Q1 2010 • Q4 2009

Digitizer Module Camera Link Module

• 1 ch. at 3 GS/s, 8-bit, or • Single full-configuration interface
• 2 ch. at 1.5 GS/s • Digital outputs for control
• Q2 2010 • Q4 2009
P2P Architecture
Conclusions
• FPGAs enable some types of test applications
nott previously
i l possible,
ibl andd make
k others
th ffastert
• LabVIEW FPGA smooths learning curve for
digital desgin
• FlexRIO
Fl RIO bbenefits
fit
ƒ Custom processing and decision making using
COTS platform
ƒ Suitable as co-processor
p with pp2pp data transfer
ƒ Interchangable I/O and custom designed I/O