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Operating frequency:
60 kHz for L type
115 kHz for H type
On-board soft-start
DIP-7
Description
The device is an off-line converter with an 800 V
rugged power section, a PWM control, two levels
of over current protection, over voltage and
overload protections, hysteretic thermal
protection, soft-start and safe auto-restart after
any fault condition removal. Burst mode operation
and device very low consumption helps to meet
the standby energy saving regulations.
Application
Typical topology
+
+
DC input high voltage
wide range
DC Output voltage
DRAIN
DRAIN
BR
VIPER27
GND
Table 1.
VDD
CONT
FB
Device summary
Order codes
Package
Packaging
DIP-7
Tube
VIPER27LN
VIPER27HN
October 2008
Rev 1
1/31
www.st.com
31
Contents
VIPER27
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/31
7.1
7.2
7.3
7.4
7.5
7.6
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.7
7.8
7.9
7.10
7.11
7.12
Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.13
VIPER27
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/31
Block diagram
VIPER27
Block diagram
Figure 2.
Block diagram
VDD
VDD
Vcc
BR
DRAIN
Vin_OK
+
0.45V
SUPPLY
& UVLO
HV_ON
Istart-up
15uA
UVLO
-
CONT
OCP
BLOCK
OTP
OCP
BURST
SOFT
START
.
OVP
LOGIC
THERMAL
SHUTDOWN
OSCILLATOR
PWM
TURN-ON
LOGIC
LEB
S
Q
R1
R2
6uA
+
OVP
2nd OCP
LOGIC
Ref
OLP
OVP
OTP
Rsense
BURST-MODE
LOGIC
BURST
FB
GND
Typical power
Table 2.
Typical power
230 VAC
Part number
VIPER27
85-265 VAC
Adapter(1)
Open frame(2)
Adapter(1)
Open frame(2)
18 W
24 W
10 W
13 W
4/31
VIPER27
Pin settings
Pin settings
3.1
Connection diagram
Figure 3.
GND
DRAIN
VDD
DRAIN
CONT
FB
3.2
BR
Pin description
Table 3.
Pin description
N.
Name
Function
GND
This pin represents the device ground and the source of the power section.
VDD
Supply voltage of the control section. This pin also provides the charging
current of the external capacitor during start-up time.
CONT
FB
Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below 0.6 V activates the burst-mode
operation. A level close to 3.5 V means that we are approaching the cycle-bycycle over-current set point.
BR
Brownout protection input with hysteresis. A voltage below 0.45 V shuts down
(not latch) the device and lowers the power consumption. Device operation
restarts as the voltage exceeds 0.45 V plus hysteresis voltage. It can be
connected to ground when not used.
7,8
DRAIN
High voltage drain pin. The built-in high voltage switched start-up bias current is
drawn from this pin too.
5/31
Electrical data
VIPER27
Electrical data
4.1
Maximum ratings
Table 4.
Symbol
Pin
Parameter
Value
Unit
VDRAIN
7, 8
800
EAV
7, 8
mJ
IAR
7, 8
1.5
IDRAIN
7, 8
VCONT
Self limited
VFB
Feed-back voltage
-0.3 to 5.5
VBR
VDD
Self limited
IDD
Input current
25
mA
-40 to 150
Storage temperature
-55 to 150
Max value
Unit
25
C/W
75 (1)
C/W
PTOT
TJ
TSTG
4.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
RthJP
RthJA
1. When mounted on a standard single side FR4 board with 100 mm (0.155 sq in) of Cu (35 m thick)
6/31
VIPER27
4.3
Electrical data
Electrical characteristics
(TJ = -25 to 125 C, VDD = 14 V; unless otherwise specified)
Table 6.
Symbol
VBVDSS
IOFF
RDS(on)
COSS
Table 7.
Symbol
Power section
Parameter
Break-down voltage
OFF state drain current
Drain-source on state
resistance
Test condition
Min
800
Typ
Max
Unit
V
60
14
VFB = GND
VDRAIN = 0 to 640 V
40
pF
Supply section
Parameter
Test condition
Min
Typ
Max
Unit
60
80
100
VDRAIN = 120 V,
VBR = GND, VFB = GND,
VDD = 4 V
-2
-3
-4
mA
VDRAIN = 120 V ,
VBR = GND, VFB = GND,
VDD = 4 V after fault.
-0.4
-0.6
-0.8
mA
After turn-on
8.5
23.5
IDD = 20 mA
23.5
Voltage
VDRAIN_START
IDDch
VDD
VDDclamp
VDDon
VDDoff
VDD(RESTART)
13
14
15
7.5
8.5
VDRAIN = 120 V,
VBR = GND, VFB = GND
4.5
IDD0
0.9
mA
IDD1
VDRAIN = 120 V,
FSW = 60 kHz
2.5
mA
VDRAIN = 120 V,
FSW = 115 kHz
3.5
mA
400
270
VDRAIN = 120 V,
Current
IDD_FAULT
IDD_OFF
VDD = 7 V
7/31
Electrical data
VIPER27
Table 8.
Controller section
(TJ = -25 to 125 C, VDD = 14 V; unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Feed-back pin
VFBolp
4.7
4.8
5.2
VFBlin
3.2
3.5
3.7
VFBbm
Voltage falling
0.6
VFBbmhys
Voltage rising
100
mV
IFB
RFB(DYN)
HFB
VFB = 0.3 V
-150
VFB / ID
-200
-280
A
A
-3
14
21
V/A
CONT pin
VCONT_l
ICONT = -100 uA
0.5
Current limitation
IDlim
tSS
Soft-start time
TON_MIN
td
tLEB
ID_BM
VFB = 4 V,
ICONT = -10 A
TJ = 25 C
0.66
0.7
0.74
8.5
220
400
A
ms
480
ns
Propagation delay
100
ns
300
ns
155
mA
VFB = 0.6 V
Oscillator section
VIPER27L
FOSC
FD
8/31
VIPER27H
VDD = operating
voltage range,
VFB = 1 V
54
60
66
kHz
103
115
127
kHz
VIPER27L
kHz
VIPER27H
kHz
250
Hz
Modulation depth
FM
Modulation frequency
DMAX
70
80
VIPER27
Electrical data
Table 8.
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
TSTROBE
2.7
3.3
2.2
V
us
VBRhyst
IBRhyst
Current hysteresis
VBR
Operating range
VDIS
0.41
0.45
0.49
50
V
mV
Voltage falling
7
10
0.15
50
150
mV
Thermal shutdown
TSD
Thermal shutdown
temperature
THYST
Thermal shutdown
hysteresis
150
170
30
9/31
Electrical data
VIPER27
Figure 4.
Figure 5.
10 uA
Figure 6.
10/31
VIPER27
Current limit vs TJ
Figure 8.
Figure 9.
Switching frequency vs TJ
11/31
VIPER27
Figure 13. Brown out hysteresis current Figure 14. Operating supply current
vs TJ
(no switching) vs TJ
Figure 17. Power MOSFET on-resistance Figure 18. Power MOSFET break down
vs TJ
voltage vs TJ
12/31
VIPER27
TJ
TSD
THYST
VDD
VDDon
VDDoff
VDD(RESTA RT)
VDS
13/31
Typical circuit
VIPER27
Typical circuit
Figure 20. Flyback application (basic)
D3
AC IN
R1
C2
BR
Vout
C1
C5
AC IN
D1
GND
D2
R2
R3
VVcc
DD
OPTO
DRAIN
R5
BR
CONTROL
C3
R4
CONT
FB
C6
GND
SOURCE
U2
C4
R6
Rh
AC IN
Vout
R1
C2
BR
C1
C5
Rl
AC IN
D1
GND
Daux
Rov p
R2
D2
R3
VVcc
DD
DRAIN
OPTO
R5
BR
CONTROL
C3
R4
CONT
FB
C6
GND
SOURCE
U2
Rlim
C4
14/31
R6
VIPER27
Operation descriptions
Operation descriptions
VIPER27 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
7.1
7.2
15/31
Operation descriptions
7.3
VIPER27
The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is
estimated by applicator according to the output stage configurations (transformer, output
capacitances, etc).
During the converter start up time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of start up converter or after a fault.
Figure 22. Start up IDD current
IDD
VDS = 120V
FSW = 0 kHz
AFTER FAULT
2 mA
1 mA
IDD0
IDD_FAULT
IDD_OFF
IDS_CH_FAULT
-1 mA
VDDrestart
-2 mA
-3 mA
-4 mA
16/31
IDS_CH
VDDoff
VDDon
VDD
VIPER27
Operation descriptions
Figure 23. Timing diagram: normal power-up and power-down sequences
Vin
VDRAIN_START
regulation is lost here
VDD
VDDon
VDDoff
VDD(RESTART)
t
VDRAIN
IDD
3 mA
Normal
operation
Pow er-on
Power-off
I DRAIN
tss
IDlim
t
V FB
V FB_olp
V FB_lin
17/31
Operation descriptions
7.4
VIPER27
7.5
VDD
VDDon
VDDoff
VDD(RESTART)
Trep
VDRAIN
IDD
0.6 mA
< 0.03Trep
7.6
Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching
frequency is modulated by approximately 4 kHz (60 kHz version) or 8 kHz
(115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes.
18/31
VIPER27
7.7
Operation descriptions
7.8
In order to perform the output voltage monitor, the CONT pin has to be connected to the aux
winding through a resistor divider made up by RLIM and ROVP (see Figure 21 and Figure 27).
If the voltage applied to the CONT pin exceeds the internal 3 V reference for four
consecutive times the controller recognizes an over voltage condition. This special feature
uses an internal counter; that is to reduce sensitivity to noise and prevent the latch from
being erroneously activated. see Figure 26 on page 20. The counter is reset every time the
OVP signal is not triggered in one oscillator cycle.
Referring to the Figure 21, the resistors divider ratio kOVP will be given by:
Equation 2
V OVP
k OVP = -------------------------------------------------------------------------------------------------N AUX
-------------- ( V OUTOVP + V DSEC ) V DAUX
N SEC
Equation 3
R LIM
k OVP = --------------------------------R LIM + R OVP
19/31
Operation descriptions
VIPER27
Where:
VOUT OVP is the converter output voltage value to activate the OVP set by designer
Than, fixed RLIM, according to the desired IDlim, the ROVP can be calculating by:
Equation 4
1 k OVP
R OVP = R LIM ----------------------k OVP
The resistor values will be such that the current sourced and sunk by the CONT pin be
within the rated capability of the internal clamp.
Figure 26. OVP timing diagram
VDS
t
VAUX
0
CONT
(pin 4)
3V
2 s
STROBE
0.5 s
t
OVP
COUNTER
RESET
COUNTER
STATUS
t
0
0 1
1 2
2 0
0 1
1 2
2 3
FAULT
NORMAL OPERATION
20/31
3 4
TEMPORARY DISTURBANCE
VIPER27
7.9
Operation descriptions
2.
The Table 9 on page 21 referring to the Figure 27, lists the external resistance combinations
needed to activate one or plus of the CONT pin functions.
Figure 27. CONT pin configuration
R OVP
SOFT
START
CONT
OCP Comparator
Current Limit
Curr. Lim.
BLOCK
D AUX
+
Auxiliary
winding
R LIM
To PWM Logic
OVP DETECTION
LOGIC
From SenseFET
To OVP Protection
Table 9.
RLIM (1)
ROVP
DAUX
IDlim reduction
See Figure 8
No
No
OVP
80 k
See Equation 4
Yes
See Figure 8
See Equation 4
Yes
7.10
21/31
Operation descriptions
VIPER27
through a resistor at the CONT pin (using the RLIM, see Figure 16 on page 12); the PWM
comparator is disabled.
At the same time an internal current generator starts to charge the feedback capacitor
(CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned
off and the start up phase is activated with reduced value of IDDch to 0.6 mA.
During the first start up phase of the converter, after the soft-start up time (typical value is
8.5 ms) the output voltage could force the feedback pin voltage to rise up to the VFBolp
threshold that switches off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure 28
on page 23 and Figure 29 show the two different feedback networks.
The time from the over load detection (VFB = VFBlin) to the device shutdown
(VFB = VFBolp) can be set by CFB value (see Figure 28 on page 23 and Figure 29), using the
formula:
Equation 5
V FBolp V FBlin
T OLP delay = C FB ---------------------------------------3A
In the Figure 28, the capacitor connected to FB pin (CFB) is part of the compensation circuit
as well as it needs to activate the over load protection (see equation 5).
After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at VFBlin,
the output capacitor could not be at its nominal value and the controller interprets this
situation as an over load condition. In this case, the OLP delay helps to avoid an incorrect
device shut down during the start up phase.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29 on page 23.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29 are reported by the equations below:
Equation 6
fZFB =
22/31
1
2 CFB1 RFB1
VIPER27
Operation descriptions
Equation 7
fPFB =
RFB(DYN) + RFB1
2 CFB RFB(DYN) RFB1
1
2 CFB1 RFB1 + RFB(DYN)
Equation 8
fPFB1 =
+
PWM
CONTROL
Cfb
BURST
BURST-MODE
LOGIC
BURST-MODE
REFERENCES
OLP comparator
To disable logic
+
-
4.8V
+
PWM
CONTROL
Rfb1
Cfb
BURST
Cfb1
BURST-MODE
REFERENCES
BURST-MODE
LOGIC
OLP comparator
+
4.8V
To disable logic
23/31
Operation descriptions
7.11
VIPER27
VFB
100
50 mV
hyster.
VFB_bm
IDRAIN
ID_BM
Normal -mode
24/31
Burst-mode
Normal -mode
VIPER27
7.12
Operation descriptions
Brown-out protection
Brown-out protection is a not-latched shutdown function activated when a condition of mains
under voltage is detected.
The Brown-out comparator is internally referenced to VBRth,0.45 V typ value, and disables
the PWM if the voltage applied at the BR pin is below this internal reference. Under this
condition the power MOSFET is turned off. Until the Brown out condition is present, the VDD
voltage continuously oscillates between the VDDon and the UVLO thresholds, as shown in
the timing diagram of Figure 31 on page 25. A voltage hysteresis is present to improve the
noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus the
before said voltage hysteresis. See Figure 31.
The Brown-out comparator is provided also with a current hysteresis, IBRhyst.With this
approach is possible to set the VINon threshold and VINoff thresholds separately, by properly
choosing the resistors of the divider connect to the BR pin.
VINon
VINoff
VBR
VDD
Vcc
0.45V
HV DC Input bus
VinOK
0.1V
R
+
-
AC_OK Disable
IBR HYS
10 A
1
BR
RL
VDD
VinOK
0.45V
10u
VDRAIN
Vout
Fixed the VINon and the VINoff levels, with reference to Figure 31, the following relationships
can be established for the calculation of the resistors RH and RL:
Equation 9
RL =
VBRhyst
IBRhyst
VBRth
IBRhyst
25/31
Operation descriptions
VIPER27
Equation 10
RH =
RL +
RL
V BRhyst
I BRhyst
For a proper operation of this function, VIN on must be less than the peak voltage at
minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, thus it is prone to
pick up noise, which might alter the OFF threshold when the converter operates or gives
origin to undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.
If the Brown-out function is not used the pin has to be connected to GND.
26/31
VIPER27
7.13
Operation descriptions
VDDon
VDDoff
VDD(RESTART)
IDRAIN
IDMAX
VDRAIN
27/31
VIPER27
Dim.
Typ
Min
5,33
A1
0,38
A2
3,30
2,92
4,95
0,46
0,36
0,56
b2
1,52
1,14
1,78
0,25
0,20
0,36
9,27
9,02
10,16
7,87
7,62
8,26
E1
6,35
6,10
7,11
2,54
eA
7,62
eB
L
M
(6)(8)
10,92
3,30
2,92
3,81
0,40
0,60
2,508
0,50
N1
O (7)(8)
0,60
0,548
1- The leads size is comprehensive of the thickness of the leads finishing material.
2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
3- Package outline exclusive of metal burrs dimensions.
4- Datum plane "H" coincident with the bottom of lead, where lead exits body.
5- Ref. POA MOTHER doc. 0037880
6- Creepage distance > 800 V
7- Creepage distance 250 V
8- Creepage distance as shown in the 664-1 CEI / IEC standard.
28/31
Max
VIPER27
29/31
Revision history
VIPER27
Revision history
Table 11.
30/31
Date
Revision
20-Oct-2008
Changes
Initial release
VIPER27
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31/31