EE215A

Fall 14

B. Razavi
HO #2

Single-Stage Amplifiers
Many aspects of the performance of amplifiers are citical. We summarize
the tarde-offs as whown below.

The amplifiers to be studied here include: CS and CG stages, source

followers, and cascades. For each stage, we wish to study both the
large-signal and small-signal properties.
Amplifier Categories

Common Source Stage

- Large-Signal Behavior

EE215A
Fall 14

B. Razavi
HO #2

What is the small-signal gain in this region?

At point A:
How do we maximize the gain?

- Small-Signal Analysis
We assume that the bias currents and voltages are chosen such that M1
is in saturation and QI in forward active region.

Voltage Gain:

Sometimes we dont want to use a resistive load. So we try other tricks:

This device can operate as a resistor. How about this:

Common Source with Diode Load

EE215A
Fall 14

B. Razavi
HO #2

How do we maximize the voltage gain here?

Large Signal Behavior:

Example: Common Source with PMOS Diode Load

Both versions suffer from serious headroom

limitations at low supply voltages.
CS Stage with Current Source Load

What happens to the gain as ID decreases?

CS Stage with Active Load

EE215A
Fall 14

B. Razavi
HO #2

CS Stage with Source Degeneration

It is useful to find the Gm of the stage:

Also, the output impedance:

Now lets compute the gain by noting that:

If =0 and gmb=0, then:

4

EE215A
Fall 14

B. Razavi
HO #2

Example

Source Followers
- Large-Signal Behavior

Sketch the gain vs. input.

- Small-Signal Behavior

Often use a current source in

place RS to have a better definition
of the bias current.

EE215A
Fall 14

B. Razavi
HO #2

How good a buffer is a source follower? Input impedance =

Output Impedance:

Another method of finding

the gain:

Can eliminate body effect in PMOS version:

Source followers are used only occasionally. They introduce noise

and consume voltage headroom. For example:

EE215A
Fall 14

B. Razavi
HO #2

Common-Gate Stage
- Large-Signal Behavior

- Small-Signal Behavior

Input Impedance

Introducing CMOS Devices

NMOS
(Bulk) (Source)

p+

n+

PMOS

(Gate)

p-

(Drain)

n+

(Bulk) (Source)

n+

p+

(Gate)

(Drain)

p+

n(Bulk)

(Bulk)

p-

(Drain)
D
(Gate) G

B (Bulk)
S
(Source)

(Source)
S
(Gate) G

B (Bulk)
D
(Drain)

CMOS: Complementary Metal Oxide Semiconductor

- Current flow through channel between Drain and Source

is controlled by Gate
- Complementary: both PMOS and NMOS are available

M.H. Perrott

Simplified MOS Symbol for Typical Bulk Connections

NMOS
Gnd

(Bulk) (Source)

p+

n+

(Gate)

p-

PMOS
(Drain)

n+

Vdd

(Bulk) (Source)

n+

p+

(Gate)

n-

(Drain)

p+

(Bulk)

(Bulk)

p-

(Drain)
D
(Gate) G

(Gate) G
S
(Source)

(Source)
S

D
(Drain)

Bulk silicon below the channel under the gate also has an
impact on the channel current

- We often tie the Bulk to Gnd/Vdd for NMOS/PMOS devices

M.H. Perrott

In such case, the symbol does not include the bulk terminal

Symbol Notation Often Includes Size

M1

W
W
L

The designer is generally free to choose the width (W)

and length (L) of the device

- Wider width is often chosen to achieve higher channel

current for a given gate bias voltage
- Longer length is often avoided since it lowers the channel
current and decreases the operating speed of the device
The minimum length for the gate is often used to define the
process name (i.e., 0.18u CMOS or 0.13u CMOS)
Longer length is used in cases where better matching or
high resistance is desired

M.H. Perrott

Channel Current as a Function of Gate Voltage

Id

Id

Vds > V

Note that we designate

V as the overdrive voltage
and that V = Vdsat
in strong inversion

M1

Vgs

Id_op

Vgs
VTH Vgs_op

NMOS

If Vgs < VTH, then current density Id/W is small

For Vgs > VTH, then Id/W is much larger

- The device is in the subthreshold operating region

- The device is in strong inversion
- If V > V, then I is relatively independent of V
The device is in the saturation operating region
- If V < V, then I is strongly dependent on V
ds

ds

The device is in the triode operating region

M.H. Perrott

ds

ds

PMOS Devices are Complementary to NMOS Devices

Id

Vsd > V

Vsg

M2

g
d

Id

Id_op
Vsg

PMOS

-VTH Vsg_op
V

Same observations and definitions apply to PMOS

- However, voltage and current signs are flipped

Note that Vsg = -Vgs, Vsd = -Vds

Note that Id as defined above for PMOS is in the
opposite direction as for NMOS
Note that VTH becomes negative
M.H. Perrott

Examine MOS Behavior As Vds is Increased

Triode

ID

VGS
G
S

Overall I-V Characteristic

VDS=0
D

Cchannel = Cox(VGS-VTH)

Pinch-off

ID

ID

Pinch-off

Saturation

VGS
G
S

VD=V
D

Saturation

Triode

ID

VDS

VGS
G
S

M.H. Perrott

VD>V
D

How does VGS influence Id in the above curve ?

MOS Behavior Is A Function of Vgs and Vds

Overall I-V Characteristic

ID
Pinch-off

Saturation

See page 15-23 of Razavi

Triode
V

Increasing Vgs

VDS

M.H. Perrott

MOS Current Equations in Triode and Saturation Regions

Triode

ID

VGS
G
S

VDS=0

ID = nCox W (VGS - VTH - VDS/2)VDS

L
for VDS << VGS - VTH

ID

Cchannel = Cox(VGS-VTH)

Pinch-off

ID
V = VGS-VTH

VGS
G
S

VD=V

2IDL
nCoxW

ID

VGS
G
S

V =

Saturation

M.H. Perrott

nCox W (VGS - VTH)VDS

L

VD>V
D

ID =

1 C W
2
(VGS-VTH) (1+VDS)
n ox
2
L
(where corresponds to
channel length modulation)
9

Example: Current Versus Voltage for 0.18 Device

Id

Vgs
M1

1.8
W
=
L
0.18

Id versus Vgs
1.4

1.2

Id (milliAmps)

0.8

0.6

0.4

0.2

0
0.4

0.6

0.8

1.2

gs

M.H. Perrott

1.4

1.6

1.8

(Volts)

11

The Tricky Issue of Modeling MOS Devices

The device characteristics of modern CMOS devices

lead to complicated analytical models

- This creates challenges for achieving accurate hand

calculations with reasonable effort

Hand calculations are essential in achieving deeper

understanding and intuition of circuit and device
behavior

- Simple hand calculations lack accuracy

- Detailed hand calculations often do not yield the desired
insight and understanding to make them worthwhile

A typical compromise

- Assume simple models for hand calculations

- Use SPICE to get a more accurate picture of the actual
circuit and device characteristics and performance

M.H. Perrott

12

What is the Key Role of Large Signal Calculations?

In analog circuits, we are often focused on amplifiers in

which the small signal behavior is of high importance

- Large signal calculations lead to the operating point

information of the circuit which is used to determine the

small signal model of the device

Example amplifier circuit:

Small Signal Analysis Steps
ID

RD

1) Solve for bias current Id

RG

vout

vin
Vbias

M.H. Perrott

RS

2) Calculate small signal

parameters (such as gm, ro)
3) Solve for small signal response
using transistor hybrid- small
signal model

13

A Key Small Signal Parameter: Transconductance

Id

Id

Vds > V

M1

Vgs

NMOS

Id
gm =
Vgs
Vgs_op
Vgs

Id_op

VTH Vgs_op
V

Transconductance from input gate voltage, Vgs, to

channel current, Id, is very important for amplifier circuits

- Assuming device is in saturation:

M.H. Perrott

14

A Key Small-Signal Nonideality: Output Resistance

ID
Pinch-off

Saturation

Id
gds =
Vds

Triode

Vds_op
Vds

Vds_op

Ideally, Id would not change with Vds when the device is

in saturation

- Practical CMOS transistors exhibit I dependence on V

due to channel length modulation
- The parameter is often used to characterize this effect
d

M.H. Perrott

ds

15

Another Non-Ideality: Back-Gate Effect

NMOS
(Bulk) (Source)

Gnd

p+

n+

(Gate)

p-

PMOS
(Drain)

n+

Vdd

(Bulk) (Source)

n+

p+

(Bulk)

(Gate)

n(Bulk)

(Drain)

p+
p-

The threshold voltage of the device, VTH, is dependent on

the potential between the source and bulk

- This implies that changes in the source node voltage, V ,

s

lead to changes in the channel current, Id

We model this effect as backgate transconductance, gmb

- MIC503 will provide details (also see pages 34-36 of Razavi)

M.H. Perrott

16

MOS DC Small Signal Model

Assuming transistor is in saturation:

- Note that designers often determine g

ID

mb

impact from SPICE

RD

RD
RG

RG
vgs

gmvgs

ro

-gmbvs

RS

vs

See Chapter 2 of Razavi

for more discussion of
these formulas

RS

gm = nCox(W/L)(VGS - VTH)(1 + VDS)

= 2nCox(W/L)ID (assuming VDS << 1)
gmb =

2 2|F| + VSB

where =

2qsNA
Cox

In practice: gmb = gm/5 to gm/3

ro =

M.H. Perrott

gm

1
ID

17

MOS DC Small Signal Model

Assuming transistor is in triode region:

- The channel of the device can be approximated as a

resistor whose value depends on the DC operating point
of Vgs

ID

RD

RD
RG

RG
vgs

rds

RS

vs

M.H. Perrott

RS

rds =

1
nCox(W/L)(VGS - VTH)

18

Example: Determine V and Operating Region (NMOS)

Assume VTHn = 0.5V

1V

0.2V

0.2V

1V

0.7V

V =

V =

V =

Region =

Region =

Region =

1V

0.2V

0.2V

1V

0.4V

M.H. Perrott

1V

1V

0.7V

0.4V

0.4V

V =

V =

V =

Region =

Region =

Region =
19

Example: Determine V and Operating Region (PMOS)

Assume VTHp = -0.5V

1.3V
0.5V

0.5V

0.9V
0.7V

0.7V

1.1V

V =

V =

V =

Region =

Region =

Region =

1.2V

0.8V

1.3V

0.5V

0.9V
1.3V

M.H. Perrott

1.3V

1.3V

0.7V

1.1V

V =

V =

V =

Region =

Region =

Region =
20

Example: Determine Operating Region of M1 and M2

Assume VTHn = 0.5V, VTHp = -0.5V, nCox = 50A/V2,

pCox = 20A/V2, = 0, and M1 and M2 have the same
value of W and L
1.3V
M2

vout
Vbias
M1

Determine operating region for M1 and M2 assuming:

-V
-V
-V

M.H. Perrott

= 1.2
bias = 0.2
bias = 0.65
bias

21

Example: Determine V and Operating Region

Assume Vbiasp = 0.7V, VTHn = 0.5V, VTHp = -0.5V,

nCox = 50A/V2, pCox = 20A/V2, = 0

Vbiasp

Vbiasn

M2

1.3V
3.25u
0.13u

vout
1.3u
0.13u

M1

Determine Vbiasn such that Vout = 0.5V

- Note that with = 0, a variety of V

solutions will exist for

the same Vbiasn Im just trying to keep calculations simple
out

Determine the resulting operating region of M1 and M2

M.H. Perrott

22

Lecture 3 Discussed Large Signal Calculations

In analog circuits, we are often focused on amplifiers in

which the small signal behavior is of high importance

- Large signal calculations lead to the operating point

information of the circuit which is used to determine the

small signal model of the device

Example amplifier circuit:

Small Signal Analysis Steps
ID

RD

1) Solve for bias current Id

RG

vout

vin
Vbias

M.H. Perrott

RS

2) Calculate small signal

parameters (such as gm, ro)
3) Solve for small signal response
using transistor hybrid- small
signal model

A Key Design Parameter is the Sizing of Devices

M1

W
W
L

The designer is generally free to choose the width (W)

and length (L) of the device

- Wider width is often chosen to achieve higher channel

current for a given gate bias voltage
- Longer length is often avoided since it lowers the channel
current and decreases the operating speed of the device
The minimum length for the gate is often used to define the
process name (i.e., 0.18u CMOS or 0.13u CMOS)
Longer length is used in cases where better matching or
high resistance is desired

M.H. Perrott

MOS DC Small Signal Model (Saturation Assumed)

ID

RD

RD
RG

RG
vgs

gmvgs

ro

-gmbvs

RS

vs

RS

gm = nCox(W/L)(VGS - VTH)(1 + VDS)

= 2nCox(W/L)ID (assuming VDS << 1)
gmb =

gm
2 2|F| + VSB

where =

2qsNA
Cox

In practice: gmb = gm/5 to gm/3

ro =

1
ID

How do we model if device is in the triode region?

M.H. Perrott

CMOS Devices Also Have Capacitance

Top View

Side View
ID
E

VGS

G
Cov

Cov
Cgc
Ccb

W
Cjsb

LD
B
E

D
Cjdb
LD

E
junction bottom wall
cap (per area)

source to bulk cap: Cjsb =

drain to bulk cap: Cjsd =

Cj(0)
B

1 + VSB
Cj(0)
1 + VDB

overlap cap: Cov = WLDCox + WCfringe

WE +

junction sidewall
cap (per length)

Cjsw(0)
B

1 + VSB
WE +

Cjsw(0)
1 + VDB

(W + 2E)
(make 2W for "4 sided"
perimeter in some cases)

(W + 2E)

gate to channel cap: Cgc =

channel to bulk cap: Ccb - ignore in this class

M.H. Perrott

VD>V

2
C W(L-2LD)
3 ox
5

MOS AC Small Signal Model (Device in Saturation)

RD
RG
ID

RD

Cgd
vgs

RG

Cgs

gmvgs

-gmbvs

ro

Cdb

Csb

RS

vs

Cgs = Cgc + Cov =

RS

2
C W(L-2LD) + Cov
3 ox

Cgd = Cov

M.H. Perrott

Csb = Cjsb

(area + perimeter junction capacitance)

Cdb = Cjdb

(area + perimeter junction capacitance)

6

Small Signal Modeling Strategy

We will focus on the DC Small Signal Model first

- This will allow us to calculate the gain of amplifiers

- This will also allow us to derive Thevenin resistances
We will later combine this information with the capacitors
within the AC Small Signal Model to estimate frequency
response information

Homework 1 should have revealed to you how clumsy

the DC Small Signal Model can be in calculations

- We need a more streamlined approach

Strategy: give up general approach, and focus on

achieving a simpler model that fits a large number of
circuit topologies that we will encounter

M.H. Perrott

Thevenin Modeling of CMOS Transistors

Hybrid- Model
Rthd
RG

Key Small-Signal Parameters

RD
d

Parameter
gm

Rthg

vgs

gmvgs

-gmbvs

s
vs

RS

2nCox(W/L)ID

ro
gmb

Rths

Strong Inversion

ro

gm

Weak Inversion
qID
nkT

2 2|F| + VSB

(n-1)qID
nkT

1
ID

1
ID

We will discuss weak inversion

(i.e., subthreshold region) later

Use the Hybrid- model of transistor to calculate

Thevenin resistances at each transistor node
Use these Thevenin resistance calculations for many
circuit topologies that we encounter

M.H. Perrott

Thevenin Resistance Expressions

Hybrid- Model
Rthd
RG

Key Small-Signal Parameters

RD

Parameter
gm

Rthg

vgs

gmvgs

-gmbvs

s
vs

Note: gmb = 0
if RS=0 or Vsb=0

RS

Thevenin Resistances

Exact
Rth = ro (1+(gm+gmb)RS)+RS
d

ID
RG

g
Rthg

Rthd

Rth = (1+RD /ro ) (ro

s

1
)
gm+gmb

Approximation
(gmb << gm, gmro >> 1)

s
Rths
RS

M.H. Perrott

Rthg= infinite

RD

Rthd= ro (1+gmRS)
Rthg= infinite
1 + RD /ro
Rth =
gm
s

2nCox(W/L)ID

ro
gmb

Rths

Strong Inversion

1
(RD<< ro )
gm

ro

Weak Inversion
qID
nkT

gm

(n-1)qID

2 2|F| + VSB

nkT

1
ID

1
ID

Thevenin resistances
useful for many
calculations
It would be nice to
replace Hybrid-
model with a simpler
alternative
9

Replace Hybrid- Model with Proposed Thevenin Model

Hybrid- Model
Rthd
RG

Key Small-Signal Parameters

RD

Parameter
gm

Rthg

vgs

gmvgs

-gmbvs

ro

s
vs

RS

Thevenin Resistances

Note: gmb = 0
if RS=0 or Vsb=0

RD

RG

g
Rthg

Rthd

2 2|F| + VSB

nkT

1
ID

1
ID

s
Rths

is

Rths
1
)
gm+gmb

Rthg vg

Avvg

Approximation
(gmb << gm, gmro >> 1)
RS

M.H. Perrott

Rths= (1+RD /ro ) (ro

(n-1)qID

Proposed Small Signal Transistor Model

Rthd= ro (1+(gm+gmb)RS)+RS
ID

gm

ro

Exact
Rthg= infinite

Weak Inversion
qID
nkT

2nCox(W/L)ID

gmb
Rths

Strong Inversion

Rthd= ro (1+gmRS)

Exact

Rth = infinite
g
1 + RD /ro
Rth =
gm
s

Av = gmro
1
(RD<< ro )
gm

is

Rthd

s
Approximation
gm
gm+gmb

= 1+RD /Rthd

Av = 1 (gmb<<gm, gmro>>1)
= 1 (RD<<Rthd)

10

Key Things to Know About the Proposed Thevenin Model

Thevenin Resistances

Proposed Small Signal Transistor Model

Exact
Rth = ro (1+(gm+gmb)RS)+RS
d

RD

ID
RG

g
Rthg

Rthg= infinite
Rthd

s
Rths

is

Rths
1
)
gm+gmb

Rthg vg

Avvg

Approximation
(gmb << gm, gmro >> 1)
RS

Rths= (1+RD /ro ) (ro

Rthd= ro (1+gmRS)

Exact

Rthg= infinite
1 + RD /ro
Rths=
gm

Av = gmro
1
(RD<< ro )
gm

is

Rthd

s
Approximation
gm
gm+gmb

= 1+RD /Rthd

Av = 1 (gmb<<gm, gmro>>1)
= 1 (RD<<Rthd)

This model may be generally applied in cases where the

transistor is in saturation and where there is not strong
interaction between the transistor terminals

- Works well for open loop amplifier stages which will be our
initial focus

Proposed model is not commonly taught I developed it

M.H. Perrott

11

A General View of Signal Flow in an Open Loop Device

Vin,d

ID

RG

RD
d

Vd

M1

M1
Vs

gate signal impacts

source and drain

RS

Vin,g

RG

Vin,s

is

Rths

Rthg

source signal impacts

drain

vg

is

Avvg

Rthd

RD
vd

s
vin,g

vin,d

RS
vs
vin,s

To first order, influence of signals go from gate to

source or from gate and/or source to drain

- This is only true when the device is in saturation

M.H. Perrott

12

Example: Small Signal Analysis of Amplifier Circuit

RD
Vout

RG
Vin

Key device characteristics

that must be known:

M1

For gm, ro: W, L, nCox,

RS

For gmb: gm, , F, VSB

First step: determine the operating region of transistor

For triode region, approximate channel as a resistance
Id will usually be set primarily by drain and source network
For subthreshold region, approximate channel as open
Later on, we will take a more accurate view of this
For saturation region, use proposed Thevenin model
Id will usually be set by gate voltage and source network
(i.e., resistance and voltage)
Small signal parameters (gm, ro, etc.) can be calculated
once Id is known

M.H. Perrott

13

Substitute Proposed Thevenin Model (Assumes Saturation)

RD
Vout

RG
M1
Vin

RS

M1
RG

vin

Rthg

is

Rths

vg

is

Avvg

Rthd

RD

vout

s
RS

Notice that all voltages and currents can be calculated

without requiring simultaneous equations!

M.H. Perrott

14

Reduce to Two-Port
RG

RD
Vout

RG
M1
Vin

vin

vg

Rthg

Rthd

Gmvg

RD

vout

RS

M1
RG

vin

Rthg

is

Rths

vg

is

Avvg

Rthd

RD

vout

s
RS

Calculation of Gm:

M.H. Perrott

15

Detailed Example
1.3V

100
Vin
Vbias= 0.65V

M1

10k
Vout
13u
0.13u

Assumptions:
nCox = 50A/V2, VTHn = 0.5V
= 1/(10V), = 0

100

Determine operating point conditions

- Transistor operating region, I

Determine small signal parameters of transistor model

- If transistor is in saturation, this is g , r , etc.

m

Determine gain of amplifier

M.H. Perrott

16

From Lecture 5: Basic Single-Stage CMOS Amplifiers

Common Source

Common Gate

Source

ZL

ZL

Source

M1

id

id

W1
L

W1
L
iin

M1

Common Source
with Source Degeneration

Vin

W1
L

M1

Vout

Vout
Vin

Source Follower

Vout
ZL

Source

ZL
Vout
id
Source

Vin
M1

Source

W1
L

Zsrc
Vsrc

Isrc

Zsrc

ZS

M.H. Perrott

A Closer Look at Load Impedance

Common Source

Common Gate

Source

ZL

ZL

Vout

Vout

Source

Vin
M1

id

id

W1
L

W1
L
iin

M1

Vout
id

Source

Vin
M1

W1
L
ZS

M.H. Perrott

Vin

W1
L

M1

Vout
ZL

Source

Common Source
with Source Degeneration
ZL

Source Follower

To achieve high gain (or low

attenuation in the case of a source
follower), it is very desirable to
achieve high load impedance, ZL

- Unfortunately, using a simple resistor

of high value has issues
What are these issues?
3

Issue #1: Headroom Limitations

Common Source
Vdd
RL
Vout
Id
Source

Vin

Want Vds > V

M1

The bias current of the device is a direct function of RL

-V
-V
M.H. Perrott

Vdd Vds
Id =
RL
is < 3.6V for most modern CMOS processes
ds must be greater than V to maintain device saturation
dd

Large RL implies small Id

(implies small gm, poor frequency response, etc.)

Issue #2: Area of Circuit

Common Source
Vdd
RL
Vout
Id
Source

Vin

Want Vds > V

M1

The most common resistors for precision analog

circuits are often based on unsilicided polysilicon
layers

- The sheet resistance of unsilicided polysilicon is often

< 1k/square

Large polysilicon RL implies relatively large circuit area

(implies high relative cost)
M.H. Perrott

An Elegant Approach to Achieving High Gain

Common Source
Vdd
Ibias
Vout
Id
Source

Vin

Vds1 > V1

M1

Replacement of resistor load with a current source

yields the highest possible DC gain out of the amplifier

- Current source determines I

of device

We can make current sources out of transistors

- Generally smaller area than polysilicon resistors

What is the small signal gain of the above circuit?

M.H. Perrott

A Simple Transistor Based Current Source

Vdd
Vbias

Vsd2 > V2
M2
Vout
Id

Source

Vin

Vds1 > V1

M1

Simply use a PMOS load that is properly biased

- If we keep the PMOS in saturation, its current is

relatively constant despite Vsd variations
This is the desired behavior of a current source

What are the nonideal issues of the above approach?

M.H. Perrott

Issue #1: Impedance of PMOS Device

Vdd
Vbias

Vsd2 > V2
M2
Vout

ZL
Id
Source

Vin

Vds1 > V1

M1

An ideal current source has infinite impedance

PMOS devices have finite impedance

- What is Z in the above circuit?

- How does finite Z impact the gain of the circuit?
L

We will later examine techniques to increase ZL

M.H. Perrott

Issue #1: High Bias Sensitivity

Vdd
Vbias

W2
L
M2
Vout
Id

Source

Vin

Vds1 > V1

M1

The PMOS device current, Id, is very sensitive to the

value of Vbias

- We want I

to be relatively constant across temperature

and process variations
d

How can we achieve tighter control over Id across

temperature and process variations?
M.H. Perrott

Key Technique: Use Current Mirror

Vdd
Vbias

W3
L

W2
L

M3

Vsd2 > V2

M2
Vout

Ibias

Id
Source

Vin

Vds1 > V1

M1

Key idea: use a different PMOS device, M3, to transform a

bias current, Ibias, into bias voltage, Vbias

- V now yields a consistent current, I , in M (assumed to

be in saturation) across temperature and process variations
- Note that layout of M and M must be done properly to
bias

achieve good device matching

How does Id relate to Ibias?

M.H. Perrott

10

NMOS Devices Can Also Be Used for Current Mirrors

Ibias
Zo
W2
L

Vbias
M2

M1

Id
W1
L

Vds1 > V1

We often use both NMOS and PMOS versions in

designs

- Well explore this issue further later in the semester

General issue: current mirrors involve direct

feedback between drain and gate
Can we apply proposed Thevenin modeling
approach to current mirrors?

M.H. Perrott

11

Issue: Thevenin Impedances Are Not Adequate

Zo

M1
RS

Looking as purely Thevenin impedances

But, in reality

Issue: coupling between source, drain, or gate

- Do we have to abandon the Thevenin method?

M.H. Perrott

12

Try Proposed Thevenin Model

Zo
g

vtest

is

Rths
Rthg vg

itest

Avvg

is

Rthd

s
Rs

Key Calculations (ignore Rthd for now):

M.H. Perrott

13

Proposed Thevenin Model Works!

Zo
g

vtest

is

Rths
Rthg vg

itest

Avvg

is

Rthd

s
Rs

Now include Rthd:

M.H. Perrott

14

Check Thevenin Resistance Calculation

Derive Zo Using
Hybrid- Model

Diode-Connected
Device

Resulting
One-Port Model

Zo
Zo

Zo

vgs

gmvgs

M1

RS

vs

-gmbvs

ro

(gm+gmb)

gm

gm

RS

RS

Plug in Hybrid- to do the analysis

Easiest to just memorize this result:

- Answer agrees with proposed Thevenin model approach

Diode connected MOS looks like a resistor of value 1/gm

M.H. Perrott

15

Now Apply Thevenin Approach to the Current Mirror

Zo

Ibias
node1

Iref

node2

M2

M1
Zo

M2

M1

node1
g1

1
gm2

Diode-Connected

Rthg1

node2

Zo
node2

d1

g m1vg1

vg1

Rthd1

Rthd1= ro1

Common Source

Key parameter of current source: output resistance

- Corresponds to r

M.H. Perrott

of device
16

Cascoded Current Source

Zo
Vbias

Ibias

M3

M2

M1

Iref
Vds3 > V3

Zo
Vbias

Vds1 > V1

M3

ro1

Offers increased output resistance

- Calculate using Thevenin resistance method

- How does I compare to I ?
ref

M.H. Perrott

bias

17

Double Cascode Current Source

I1

I2
Vbias2

M3

Vbias1

M2

M4

M1

Zo
Vds3 > V3

Vds2 > V2

Vds1 > V1

Offers further increased output resistance

- Calculate using Thevenin resistance method

- How does I compare to I ?
2

M.H. Perrott

18