CHAPTER I

INTRODUNCTION

1.1 Overview

Oscillators are integral components of any communication systems for carrier

generation. Frequency and Phase offsets exist between the transmitter and receiver
oscillators. It is not possible to build to oscillators with exactly same frequency and
phase because of analog component impairments. So that we need to compensate for
these carrier offsets and that is the purpose of using carrier recovery.

Phase Locked Loop is a device that does the carrier recovery. Many
researchers have been done on the PLL and still going on, because there are some
challenges including compensation between high loop bandwidth and noise this
means a larger bandwidth leads us to lesser locking time but we are allowing amount
of noise to exist in the recovered signal.

The first PLL Integrated Circuits (ICs) emerged around 1965 and were purely
analog devices. The phase detector was an analog multiplier, the loop filter was
active or passive RC filter, while voltage controlled oscillator (VCO) was used to
generate the output signal of the Loop (PLL). Today, this type of PLL is known as
Analog PLL (APLL) or "linear PLL"(LPLL). Afterwards a digital PLL (DPLL)
was invented around 1970s; which contained both digital and analog components; it

was analog PLL with digital phase detector. Then few years later, the "all-digital"
PLL (ADPLL) was invented, phase detector, loop filter and the VCO all are digital.

1.2 Problem statement

Usually Communications receivers are different from the transmitting

systems and have their own signal generators with frequency and phase. Frequency
and Phase offsets exists between the transmitter and receiver oscillators Several
things can cause frequency and phase change like Doppler shift in mobile RF
communication systems.

An important task for a digital communications receiver is to remove any

frequency/phase offsets that might exist between the transmitter and receiver
oscillators. Designers typically implement a carrier-recovery system, which enables
the receiver to adaptively track and remove frequency/phase offsets.

1.3 Objectives of the project

The objective of our project as follows:

I

To examine how PLLs can be used to obtain carrier synchronization in digital

II
III

communication systems.
To implement Carrier recovery system using Costas loop in MATLAB.
To evaluating the performance of the digital receiver with the presence of
noise and different carrier offsets.

3
1.4 Scope of the Project

This project is about modeling and simulating of Carrier Recovery of Binary

Phase Shift Keying (BPSK) .Two methods are commonly used for carrier recovery
(open loop estimation and closed loop or phase-locked loop estimation); in this work,
closed loop estimation, which is Costas loop, will be used.

There are two sets of techniques for carrier recovery in Closed Loop systems
(Data Aided known as Pilot Aided and Non-Data aided which also known as blind
techniques). Blind technique will be used for this project.

CHAPTER II

LITERATURE REVIEW

2.1

Overview of modulation

Modulation is the process by which some characteristics of

a carrier are

varied in accordance with a modulating signal to facilitate the transfer of information

over a medium. Sound transmission in air has limited range for power your lungs can
generate [1]. In other words, Modulation converts symbols into a waveform that
makes it compatible with the channel. Thus, it helps to receive the signals on the
small size antennas and can provide other important benefits in signals transmission.
Modulation can also be used of minimize the effect of ISI (Inter Symbol
Interference).

4
In digital communications, the modulating signal consists of binary data. This
data is used to modulate a carrier wave (usually sinusoidal) with fixed frequency.
Therefore, the modulation process involves switching or keying the amplitude,
frequency or phase of the carrier in accordance with the input data [2].

There are three basic types of digital modulation techniques:

Amplitude-Shift Keying (ASK)

Frequency-Shift Keying (FSK)

Phase-Shift Keying (PSK)

All of these techniques vary a parameter of a sinusoid to represent the

information, which we wish to send. Each sinusoid has three characteristics that
differentiate it from the other sinusoids, which are amplitude, Frequency and phase .
In our project, we will focus on Phase-Shift Keying (PSK) technique especially
binary Phase shift keying (BPSK).

2.2

Phase shift keying (PSK)

Developed during the early days of the deep space programs, phase-shift
keying now finds widespread use in both military and commercial communication
systems. For telemetry applications, PSK is considered an efficient form of data
modulation because it provides the lowest probability of error for a given received
signal level, when measured over one symbol period. Terrestrial microwave radio
links and satellite communication systems also frequently employ PSK as their
modulation format [3].

Phase-shift keying (PSK) is digital modulation scheme that conveys data by

changing, or modulating the phase of the carrier wave accordance in input data. A
binary phase-shift keying (BPSK) signal can be defined by:

s (

t
(
)
A d t cos 2 f c t 0<t <T (2.1)

t
f
Where A is a constant, d ( +11 , c is the carrier frequency, and T is the bit
duration.
2

The signal has a power P= A /2 , so that A =

2 p . Thus, equation (2.1) can be

written as:
t
s ( = 2 p cos 2 f c t= PT

2
2
cos 2 f c t = E
cos 2 fct (2.2)
T
T

Where E = P T is the energy contained in bit duration.

2.2.1

BINARY PSK (BPSK)

Binary phase shift keying (BPSK) Binary data are represented by two signals
with different phases in BPSK. Typically, these two phases are 0 and , the signals
t

are: s 1 ( = 2 E cos 2 f c t , 0 t T , for 1(2.3)

T
t
2E
2E
s 2 ( =
cos ( 2 f c t + ) =
cos 2 f c t , 0 t T , for 0(2.4)
T
T

For this signal set, there is a single basis function

t
1 ( =

2
cos 2 t f c , 0 t T ,(2.5)
T

Figure 2.1 BPSK signal constellation diagram [4]

The signal constellation diagram is pictorial diagram, which represents the

symbols of the PSK thus; you see in the Figure 2.1 the two symbols s 1 (t)

and

s 2 (t) are represented by two points on the horizontal axis, respectively.

The modulator showing in figure 2.2, which generates the BPSK signal, is

quite simple. First, a bipolar data stream

t
d (

is formed from the binary data

stream and then applied in to the modulator .so the input of the modulator are two
symbols
t
s 1 ( = E and

t
s 2 ( = E

t
or E d (t) where d ( =(+11) .

Figure 2.2 shows the block diagram of BPSK [5]

t
Then modulated signal is s ( = E d (t )1 (t)
t
s ( = E d ( t )

2
2E
cos 2 f c t =
d ( t ) cos 2 f c t (2.6)
T
T

The waveform of a BPSK signal generated by the modulator in Figure 2.2 for
a data stream {0 1 0 1 0 0 1} is shown in Figure2.3. The waveform has a constant
envelope like FSK. Its frequency is constant too. In general, the phase is not
continuous at bit boundaries.

Figure 2.3 (a) Binary modulating signal, and (b) BPSK signal [6].

The transmitted BPSK signal is given as

t
s ( = 2 p cos 2 f c t

this signal

undergoes the phase change depending upon the time delay from transmitting end to
receiver end. Let us consider that this phase shift is . Because of this, the signal

at the input of the receiver can be written as

t
s ( =d ( t ) 2 p cos [ 2 f c t+ ] (2.7 ) .

The demodulation process can be divided into two major subsections, as shown by
Figure 2.4. First, since the incoming waveform is suppressed carrier in nature,
coherent Detection is required. The methods by which a phase-coherent carrier is
derived from the incoming signal are termed, carrier recovery and will be covered
first. Next, the raw data are obtained by coherent multiplication, and used to derive
other parts of the modulator.

Figure 2.4 coherent detection of BPSK [7].

The coherent demodulator multiplies the input signal and the recover carrier.
Hence, the output of the multiplier, we get
t
t
d ( 2 p cos ( 2 f c t+ ) cos ( 2 f c t+ )=d ( 2 p cos 2 ( 2 f c t+ )

t
2(2 f c t +)
t
p
1+cos =d (
[ 1+ cos 2 ( 2 f c t+ ) ] (2.8)
2
1
d ( 2 p
2

Then equation (2.8) applied by the integrator so we can write the above equation us
:under

t
t
t

p
p
r ( =d (
[1+cos 2(2 f c t+)]. dt =d (

1dt + cos 2 ( 2 + ) (2.9)

2 0
2 0
0

10
T

cos 2( 2 f c t+) dt=0

Where

since average value of sinusoidal wave. Then

Tb
s ( =d (t)
we get.

p
T
2 b
Tb where

Tb
is bit duration thus the last equation

shows that the output of the receiver dependents on input data. Since we get the
t
. d ( original data

2 . 4phase locked loop (PLL)

The history of phase locked loop (PLL) goes back 1932 when alternative to
Armstrongs super heterodyne receiver was investigated which required fewer tuned
circuits. In 1940s, major use of phase locked loop started in horizontal and vertical
sweep of oscillators in the television receiver. In the early 1950s a good phase
locked loop would adjust television colors with a seconds [11].

The phase locked (PLL) is a feedback loop which locks two wave forms to
track the phase and frequency of the carrier component of incoming signal [12]. The
term phase locking means the task of aligning the output phase of oscillator voltage
with the phase of the reference voltage , so it is achieving changing the frequency of
the oscillator momentarily and comparing the phase of the oscillator and reference
signal. In communication system, PLL can be used for carrier synchronization,

11
carrier recovery, frequency demodulation, phase demodulation, clock recovery and
frequency synthesis etc.

The phase locked loop consist of three major component: phase detector or
multiplayer, loop filter (LF), and voltage controller oscillator (VCO) connected to
gather in form of a feedback loop as in figure 2.6. The purpose of the phase detector
is to generate an error signal that drives the PLL. It measures the difference between
phase of the local oscillator and input carrier. The error signal generated by the phase
detector is consist of an error term and noise term. Thus, the loop filter processes the
error signal in order to generate a useful error while suppressing the effect of the
noise as much as possible .it applied the VCO, which produces an oscillation whose
frequency is controlled by a lower frequency input voltage.

Figure 2.6 general PLL block diagram [13].

The first PLL ICs appeared around 1965 and where pure analog devices. This
type of PLL is referred to as the linear PLL (LPLL).in the flowing years the PLL
drifted gradually but suddenly into digital area. The very fast digital PLL (DPLL),
appeared around 1970, was in result a hybrid device only the phase detector was built
from digital circuit. A few years later, the all digital PLL (ADPLL) was invented,
the ADPLL is wholly build from digital function blocks. Analogous to filters PLLs
be able to also implement by software. In this case, the function is no longer
performed by part of specialized hardware, but rather than by computer program. The
last type of PLL is referred to software PLL (SPLL) [14].

12

CHAPTER III

3.1

Methodology overview

The aim of this project is about modeling and simulating of a carrierrecovery system, which enables the receiver to trace and remove frequency/phase
offsets, and reducing BER by comparing when there is no carrier recovery system.
This chapter describes mathematical analysing of the phase locked loop (PLL) and
the design methodology that will be used thought out this study to achieve the aims and
objectives of the project.

3.2

flow chart of the methodology

The implementation of this project is software. The simulation was divided into
three parts simulation with AWGN using simple BPSK modulator and matched receiver
demodulator, simulation with AWGN and frequency/phase offsets using BPSK
modulator and matched receiver and simulation with AWGN and frequency/phase

offsets using BPSK modulator and Costas loop demodulator then the performance is
evaluated. As showing the flow-chart in figure 3.1. All Simulations will be done in math
lab software.

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Figure 3.1 flowchart of the methodology

14

CHAPTER V

CONCLUSION

The transmitted PSK signal undergoes the phase

change depending upon the time delay from transmitting
end to receiver end, the phase \ instability in oscillators,
and thermal noise (AWGBN). An important task for a
digital communications receiver is to remove any
frequency/phase offsets that might exist between the
transmitter and receiver oscillators. a key component of
carrier recovery loop is phase locked loop (PLL). we
implement Carrier recovery system using costas loop in
MATLAB. Then we evaluate the performance of the digital
receiver with the presence of noise and different carrier
offsets.

REFERENCES

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[1]

Sanjay Sharma, analog and digital communication engineering, kiet

Ghaziabad, January2007

Humar Saeed and Fareena Shamimadaptive equalization of QPSK signals

.over a fading channels, Iraq university, Islamabad company July 2011
.MArk steper, PSKdemodulation part -1, communication, Inc, 2007
[4]

[2]

[3]

M.Schwartz, information transmission, modulation and noise, McGraw Hill

1990.

[5]
[6]

Haykin, S., digital communications, New York: John Wiley 2988.

Smith, D.R., digital transmission system, 2nd ed., New York: Van Nostrand
Renhold, 1993.

[7]

D.K. Sharma, A. Mishra and Rajiv Saxena, analog and digital modulation
techniques, international journal of computing science and communication
techniques, July 2010.

[8]

Simon, K.M., M. Hinedi, and W.C. Lindsey, digital communication

techniques: signal design and detection, Englewood Cliffs, New Jersey:
prentice Hall, 1995.

[9]

[10]

Communication system 5th ed john Wiley, Sons inc. 2010

Krishna Sankar on August 5, 2007