Lots of Watts and Plenty of MHz:

An Overview of P ow er Am plifier
Research at UCSD

Peter Asbeck

Power Amplifier Faculty & Researchers

Center for Wireless
Communications

Center for Wireless

Communications

California Insitute for

Telecommunications
& Information Technology

Prof. Larry Larson

RF Integrated Circuit
Group

Prof. James Buckwalter

High Speed Integrated
Circuits Group

Prof. Gabriel Rebeiz

Applied Electromagnetics
Group

Don Kimball
Cal IT2

Prof. Peter Asbeck

High Speed Device Group

Center for Wireless

Communications

Center for Wireless

Communications

Advancement of Wireless Communications

Wireless
systems

Critical Factors for Future Wireless Systems

Shannon limit R<B(log2(1+S/N))
Complex modulation
High peak to average ratio

High bandwidth
Future: higher frequency

High power
Low interference

Tyranny of free-space propagation

Precvd ~ Ptrans * Gtrans*Grecvr* (do/d)n

n~4

Transmitter power >> receiver power

PA dissipation is critical
Perversity of amplifier circuits
PAR and bandwidth are the enemies of efficiency!

Challenges for
Power
Amplifiers

Efficiency
Bandwidth
Integrability, low cost
Multiband, adaptivity
Low noise / interference

Agenda
Path to high efficiency & bandwidth
in Base-station PAs
Handset PA development
Future technology opportunities

Critical problem for power efficiency:

Varying signal power level
1

Average power

Efficiency

0.8

Maximum power

EER/ET

0.6
0.4

Class B

0.2

Class A

0
0

0.2
0.4
0.6
0.8
Pout (normalized)

Probability

5.0%

Probability

4.0%
3.0%
2.0%
1.0%
0.0%
-60

-50

-40

-30

-20

-10

10

20

30

P out (dBm)

Power Control Variation

Power/Pave (dB scale)

~8 dB peak to
average
power ratio

Envelope Tracking (ET) Technique

Envelope Amplifier provides dynamic drain voltage
Maximizes PA efficiency by keeping RF transistor
closer to saturation for all envelope amplitudes

Envelope
Detector

Drain voltage Dynamic Drain Voltage

tracks envelope
of RF signal
Voltage

DC
Supply

Envelope
Amplifier

Time
RF
Signal
In

RF
Amplifier

RF
Signal Out

In Envelope Tracking, PA is quasi-linear.

Input signal contains envelope and phase information.

Efficiency

Schematic Dependence of Efficiency on Output Power

Efficiency
For ET system

Vcc3

Vcc4

Vcc5

Vcc2
Vcc1
Pout (dBm)
ET System Maximizes Efficiency Vs Power
By Adjusting Output Bias (Vcc or Vdd)

Experimental Envelope Tracking Amplifier

Complex system including
RF stage, analog/digital dynamic power
supply, digital predistortion, up and downconverters

Drain Modulator
DC/DC
DSP

I
Q

ET/EER and
Predistortion

DC
Envelope

DAC

Upcon
DAC

WCDMA

Downcon

PA
Drivers Final stage

ADC

F= 2.1 GHz

RF
Output
High Power
RF Stage

Harmonic Load Tuning

Simulated Efficiency vs Harmonic Load Reactance
Class F-1

X1=0

Class F

Class F
Class B

Class F-1

Envelope Amplifier Design

VDC
Envelope
Signal

Voltage Source
High BW
Eff = 50%

Current Source
Low BW
Eff > 90%
VDC

Current
Sense

Switcher
Stage

Linear
Stage

RF Power Transistor Drain Bias

Envelope Amplifier: Overall Efficiency >70%

BW = 50 MHz
Kimball

Improved Envelope Amplifier Design

DSP-driven Main switcher provides high slew rate current
Aux switcher compensates DC error between Linear stage and Main switcher

DSP

Main Switcher

isw2

VDC

Current Source
Medium BW

Vsw2
Signal generation
Switcher control
Time alignment

VS

Envelope
Signal

iL2

VDC

L2

L2 < L1
D2

VDC

Current
Sense

Linear
Stage
Voltage Source
High BW

Vsw1
iLN

VR
iR

Aux
Switcher

L1
iL1

D1

Current Source
Low BW

RF Power Transistor Drain/Collector Bias

isw1

ET PA with Dual Switcher / HVHBT PA

Before DPD

Efficiency

After DPD
After
Memory
Mitigation*

Probability
PDF

WCDMA
6.6 dB PAPR
Pout=67W
Record

[dBc]

ACPR1

ACPR2

NRMSE

Before DPD

-35.4

-45.5

6.8%

After ML DPD

-45.3

-50.7

2.4%

After Memory
mitigation

-55.5

-60.2

0.7%

CE

Gain

PAE

RF PA

Envelope Amplifier

65.6%

12.3dB

61.7%

82%

80%

ET System: Path to Wider Bandwidth

Trade-off
Efficiency vs Bandwidth
Amplitude

DC
Supply

Doesnt need to be exact

replica of input envelope as
long as it does not clip
output envelope

Envelope
Amplifier

Vdd
RF
Power
Amplifier

RF Signal In
(WiMAX, 3GPP LTE)

RF Signal Out

Enough Bandwidth
New envelope: Power spectrum

New envelope: time domain

time

frequency

Mark-II PA Digital Predistortion Testbench

100 MHz Instantaneous Bandwidth
Tunable Carrier: 100 MHz to 4.0 GHz
Can be extended to mm-waves using
additional up/down converters

210 MSamples/s 14-bits DACs & ADCs

52 MHz Digital IF (no I/Q impairments)
Up to 220 data vectors (5-ms sequence
length)
Can operate in EER,
ET, or linear mode
Memory effect
compensation
available
Fully coded in Matlab,
to allow development
of new DPD
algorithms

Digital Correction of Amplifier Output

Nonlinearity and "memory effect" must be mitigated in order to achieve
signal accuracy needed for complex signal constellations

|Vout| vs |Vin|
No correction

Input voltage (normalized)

Memoryless correction

Input voltage (normalized)

Full correction
(with memory effect)

Input voltage (normalized)

Measurements for
commercial WLAN
amplifier

Agenda
Path to high efficiency & bandwidth in
Base-station PAs
Handset PA development
How to make a CMOS PA
How to make a mostly digital PA
Future technology opportunities

Stacked-FET Structure

Vds and Vgs swing of each FET

4.0
3.5

Vds, i

Vds3
Vgs3
Vds2
Vgs2
Vds1, V
Vgs1, V

3.0
2.5
2.0
1.5

Vgs, i

1.0
0.5
0.0
0.0

0.2

0.4

0.6

0.8

1.0

time, nsec

All FETs are operating in the safe

region

34-dBm 4-Stacked PA in SOI CMOS

TL5

Cm3

VDD
TL3

0.28-m SOI CMOS process

(S T Microelectronics)
Total device width = 5 mm x (4 devices)
Chip size (include pads) = 0.43 x 1.56 mm2
Rload=11 ohms

TL4

VG4
C4

TL6
m4
Cm4

VG3
C3

TL8

m3

TL7

In
VG2

Cm5
m2

Cm1
C2

Rf
Cf

RL

TL1
TL2

m1

GND

Cm2
VG1

VG2

In

GND

In

GND

In

GND

In

GND

Gate capacitors

VG3

VG4

CWC Project with

S T Micro

GND
GND Out GND

Out

GND

Out

GND

Out

GND

4-Stacked CMOS PA
Performance with 1.9GHz WCDMA signal

VDD=6.5V

High power
Good efficiency
Good linearity

Meets spec (-33dBc ACLR1)

29.4 dBm output power
PAE=41.4 %
Comparable to GaAs HBT PAs

On-Going Research in CMOS Envelope Amplifier

for LTE Handset Applications
A combined class-AB and switch-mode regulator based supply modulator with
a master-slave architecture is used to achieve wide bandwidth and high efficiency
VDD
M5
Anti-shoot
Through &
Gate
Drivers

c
M6

Linear Stage
M3

M2

Rsen

Env_in

OTA

ia

M4

R1

R2
To PA

id

M1

OP AMP

Switching Stage

Sense & Control

Digital Envelope-Tracking CMOS Handset Switching

Mode Power Amplifier
Multi-mode, Multi-band
-30

Q3
Q4

-60

ACPR
improve
-70
-80
-90

-110
1.9

Q1
PM

-50

-100

Buck
Converter
w/ PWM
DSP

Power/frequency (dB/Hz)

RL

Q2

Switched
Resonator
(res)

Digital PA Techniques
- RF pulse modulation
- Unit-cell switching
- Charge sampling regulator

CWC Project with Panasonic

1.91

1.92

1.93

1.94
1.95 1.96
Frequency (GHz)

1.97

1.98

1.99

100

x2.4
Total Efficiency (%)

AM

Slew Impairment
No Phase Correction
Slew Impairment
Phase PDM Correction
No Slew Impairment
No Phase Correction

-40

10

15dB back-off

All Cell, PWM

1/10 Cell, PWM
1/10 Cell, CM
Reference

0.1

850MHz
0.01
-10

10

20

Output Power (dBm)

30

40

Digitally-Modulated CMOS PA
Power controlled by number of
"on" transistors
Amplitude
Control Word

Bin.-to-Therm.
Decoder

1x

Decoder
Vdd

Tunable
Matching
Circuit

Input

Modulated
Signal

DPA core Output

Decoder

1x

80

127 Unit Cells

1/2 x

Pout/Pdc [%]

1x
Phase-modulated
Signal

Vdd = 2.1 V, through

Vdd = 1.5 V, through
Vdd = 1.0 V, through
Vdd = 0.5 V, through
Vdd = 2.1 V, input attenuation
Vdd = 1.5 V, input attenuation
Vdd = 1.0 V, input attenuation
Vdd = 0.5 V, input attenuation

70
60
50
40
30
20
10

1/8 x
3 Binary Cells

CWC Project with S T Micro

0
-20

-10

10

Output Power [dBm]

20

30

DPD Application to Skyworks GaAs HBT

WCDMA PA Module
3.4 V Current
(nominal) reading
WCDMA
3.3 dB
PAPR
20 6
dBm
1.95 GHz

Input
DA
match

Inter
stage PA
match

Output
match

bias and gain control

MMIC

50
load
(nomi
nal)

Module

4mm x 4mm handset PA module, experimental variant of SKY77174 optimized for

operation at 1.95GHz
Features high linearity (better than 40 dB ACPR) up to 29 dBm in WCDMA mode
|Vo,sat|

WCDMA Performance Using Digital Predistortion

Average power
consumption assuming
CDMA power usage
profiles

Average Power Consumption (mW)

Average
Performance

High Power
Performance

Performance at high power

Urban

600

400

Sub-urban

454

500

371

Power Savings
~ 180mW
269

300

189

200
100
0

Original PA Module

Retuned PA w/ DPD

Agenda
Path to high efficiency & bandwidth
in Base-station PAs
Handset PA development
Future technology opportunities
Adaptive PAs
Broadband PAs
High frequency PAs

High Q High Voltage Varactors for Adaptive PAs

+
-

Wmax

GaN cap layer

InGaN layer

Ni contact
n-GaN layer
Ti/Au/Pd/Au
n+GaN layer
GaN buffer layer

c-Sapphire

GaN is 40x better than Si

for high voltage varactor

UCSD Varactor Objectives

High voltage (>100V)
Low Rseries
=> High Q for basestations (>150)
& design for high linearity

GaN Single-Chip Broadband Amplifier

CF

Stack GaN for higher Zout, higher power

>12W out single chip!
Efficiency ~60% 400MHz to 1.8GHz

C1
RF
Ranges from 54.4% to
76.6%
Measured Drain Eff.
Simulated Drain Eff.
Simulated Pout
Measured Pout

Ranges from 41 dBm to

41.7 dBm

What's Coming in GaN:

On-going Research in Scaled Devices

HRL Laboratories

Lg=40nm
Fmax=400GHz
BV~42V

Digital
Baseband
Modulator

DSP

Digital
Predistorter
LUT

Upcon
DAC verter

Signal Generator

DSP
Adaptation
Vin
Mem

Vout ADC
Mem

amplifier/antenna array

Data in

UCSD mm-Wave Power Amplifier Arrays

Quartz antenna
bonded
on a SiGe chip

downconverter

SiGe HBT &

45nm CMOS SOI

Program goals: 4W at 45GHz

1W at 94 GHz
0.25W at 138GHz

All Si technology
40-60% efficiency

Measured 33 W-Band Power Amplifier

Quartz
edge
RF
Input
EIRP > 34 dBm at 90 99 GHz (@ 2.0 V)
Dramatic increase in radiated power density
Array can be scaled to entire wafer, achieving EIRP in the MW range
Scanning phased arrays possible with incremental modifications

Summary
UCSD has a wide variety of projects for handset and
basestation PAs
multiple technologies, frequencies & power levels
CMOS / HBT / GaN
UCSD has expertise in Digital Predistortion Techniques
along with state-of-the-art test benches
State-of-art research is on-going in Envelope Tracking for
both Basestation and Handset PAs
=> critical to the future of high performance PAs
for signals with high PAR (eg LTE!)

Hear more details at this afternoon's sessions!