6.

002

CIRCUITS AND
ELECTRONICS

Energy, CMOS

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Review

VS
RL

VS
P=
RL + RON

vO

vI

RON

T1: closed
T2: open R

open
closed

S1

S2

VS +

R2

1
T = T1 + T2 =
f
2

P = CVS f

Reading: Section 11.5 of A & L.

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Review

VS

Inverter

RL

vO
vI

RON

1
Square wave input
T=
f
2
V
2
P = S + CVS f
2 RL

Demo

P STATIC
independent of f.
MOSFET ON half
the time.

P DYNAMIC

RL >> RON
T
>>" RC"
2
time constant

related to switching
capacitor.
In standby mode,
f0,
so dynamic power is 0

In standby mode, half

the gates in a chip can
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Review

P=

VS
2
+ CVS f
2 RL

Chip with 106 gates clocking at 100 MHz

C = 1 f F, RL = 10 K , f = 100 10 6 , VS = 5 V
2

5
6
15
2
6
P = 10
+ 10 5 100 10
3
gates 2 10 10

= 10 6 [1.25 milliwatts + 2.5 watts ]

1.25KWatts
problem !
independent of f
also standby power
(assume MOSFETs
ON if f 0)
must get rid of this!

2.5Watts
not bad

f
VS2

reduce VS
5V1V
2.5V150mW

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

How to get rid of static power

Intuition:
VS
i

VS
RL

RL

vO high

vI high

vO low

vI low

RON

MOSFET
off

idea !

VS

vI high

vO low

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

New Device PFET

N-channel MOSFET (NFET)

on when vGS VTN

off when vGS < VTN
e.g. VTN = 1V

G
S

P-channel MOSFET (PFET)

S
G

on when vGS VTP

off when vGS > VTP
e.g. VTP = -1V

5V
ON when
less than 4V

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Consider this circuit:

VS

vI

G
+

S
D
D
S

PU = pull up

vO
PD = pull down

works like an inverter!

IN

OUT

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Consider this circuit:

works like an inverter!

OUT

IN

vI = 5V (input high)

vI = 0V (input low)

VS = 5V

VS = 5V
RON p

+
vI = 5V

vO
RON n

= 0V

+
vI = 0V

vO
= 5V

Complementary
MOS
(our previous logic was called NMOS)

Called CMOS logic

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

Key: no path from VS to GND!

no static power!
Lets compute P DYNAMIC
VS
vI
T

vI

vO

closed for
vI low

closed for
vI high

RON p

VS +

From

1
f =
T

RON n

P = CVS f

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

For our previous example

C = 1 f F, VS = 5 V , f = 100 MHz , 1
2

P = CV S f
= 10

15

5 2 100 10 6

= 2 . 5 watts per gate

P = 2 . 5 watts for 10 6 gate chip
Gates

106

100 ~2.5
MHz watts

Pentium?

2x106

300
~15
MHz watts

PII?

2x106

600
~30
MHz watts

PII?

8x106

~240
1.2 GHz watts

25x106

~1875
3 GHz watts

PIII?

keep
all
else
same

!
p
s
ga

PIV?

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

How to reduce power

A VS
5V 3V 1.8V 1.5V
~PIV 170 watts better, but high

and use big heatsink

B Turn off clock when not in use.
C Change VS depending on need.
next time:
power supply
Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

CMOS Logic
NAND:
VS

A B
0 0
0 1
1 0
1 1

Z
1
1
1
0

Z
A
B

5V
0V
G

S
on
D

5V
5V
G

S
off
D

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23

In general, if we want to implement F

e.g. F = A B = A + B

VS

short when
A = 0 or B = 0,
open otherwise

short
when F
is true,
else open

A
B

Z
short
when F
is true,
else open

short when
A B is true,
else open

r
e
b
m
reme gans law
r
o
M
e
D

Cite as: Anant Agarwal and Jeffrey Lang, course materials for 6.002 Circuits and Electronics, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

6.002 Fall 2000

Lecture

23