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Abstract
Region concept helps to accommodate cores larger
than the tile size in mesh topology NoC architectures.
In addition, it offers many new opportunities for NoC
design, as well as provides new design issues and
challenges. The most important among these is the
design of a deadlock free routing algorithm. In this
paper, we present and compare two routing algorithms
for mesh topology NoC with regions. The first
algorithm is borrowed from the area of fault tolerant
networks and is adapted for the NoC context. We
compare this with an algorithm designed using a
methodology for design of application specific routing
algorithms for communication networks. Our study
shows that the application specific routing algorithm
not only provides much higher adaptivity, but also
superior performance as compared to the other
algorithm in all traffic cases.
Keywords: Routing Algorithms, Networks on Chip,
Deadlock, Wormhole Switching, Application Specific
Routing
1. Introduction
Network on Chip (NoC) is slowly being accepted
as an important paradigm for implementing
communication among various cores in a SoC.
Network topology and routing algorithms are the two
most important aspects which distinguish various
proposed NoC architectures [1,2,3,4]. Fixed tile size
based two dimensional mesh topology is favored by
many research groups because of its layout efficiency,
good electrical properties and simplicity in addressing
on-chip resources. Such a physically homogeneous
network is not efficient for incorporating cores of
different sizes in the network. In such a network, the
tile size should be able accommodate the physically
largest core, such as a shared memory. It will also be
hard to reuse earlier designed multi-core sub-systems
within a fixed tile size based NoC. To overcome these
problems the concept of a region was proposed in [1].
This concept allows a rectangular area, larger than a
tile, in the mesh to be declared as a region. The region
Region
Wrapper
Region
Normal
Sized
NoC Tile
Bolotin et al. [3] have also proposed nonhomogeneous mesh topology NoC allowing
rectangular cores larger than the mesh tile. Their
solution to deadlock free routing is to use X-Y routing
extended with hard coded paths for region affected
traffic.
A problem similar to regions occurs when
designing fault-tolerant routing algorithms for mesh
networks. Several of these algorithms consider faults to
be contained in rectangular blocks similar to regions.
2.1.
2.2.
3.1.
CF
CF
RF
CF
RO
Network Topology
T2
T1
T4
T3
P1
P2
P3
P4
Mapping
Mapping
Function
Function
P5
Tn
P7
P6
D3
P8
P9
Comm. Concurrency
P10
C1
C2
Cm
S1
P11
P12
P13
APSRA
APSRA
Active Nodes
D1
Faulty Nodes
Memory
Memory
budget
budget
Route
Routing
Tables
Non S-Chain
S-Chain
S3
Compression
Compression
Fault-Ring
Compressed
Routing
Tables
S2
D2
3.2.
Topology Graph
T2
l12
l23
P1
T6
l41
T3
P2
l14
l21
l45
l52
P4
T5
P3
l25
l32
l56
l63
P5
l54
T4
(a)
l36
P6
l65
(b)
T1T5
T2T4
l 41
l12
l23
l 12
l23
l21
l32
l 21
l32
l14
l52
l25
l63
l 36
l41
l14
l52
l 25
l12
l21
l63
l36
l41
l 14
l52
l45
l56
l 45
l56
l45
l54
l65
l 54
l65
l54
(c)
(d)
l25
(e)
4. Evaluation of Algorithms
4.1.
Adaptivity Analysis
0,25
Chiu
0,2
0,15
0,1
0,05
0
1x1
2x1
2x2
3x2
3x3
(a)
0,9
0,8
0,7
0,6
0,5
APSRA
0,4
Chiu
0,3
0,2
0,1
0
1x1
2x2
3x2
3x3
4x3
4x4
(b)
Fig. 6. Relative adaptiveness vs. size of region: (a)
region in centre and (b) region in bottom left corner
Fig. 6(a) shows the relative adaptivity for different
region size located at the center of the NoC, whereas
Latency (cycles)
4.2.
apsra_bl_ap3
chiu_bl_ap3
48
apsra_c_ap4
chiu_c_ap4
43
38
33
1
apsra_bl_ap3
Latency (cycles)
42
chiu_bl_ap3
41
apsra_c_ap4
40
chiu_c_ap4
39
38
37
36
35
1
(a)
Latency (cycles)
58
apsra_bl_ap3
chiu_bl_ap3
53
apsra_c_ap4
chiu_c_ap4
48
43
(b)
38
33
1
5. Conclusions
In this paper we have highlighted the importance of
the region concept in mesh topology NoC architecture.
We have also listed new issues which a designer will
encounter while designing a heterogeneous mesh
topology NoC system using multi-port or multi-access
point cores. We presented and compared two deadlock
free routing algorithms for mesh NoC with regions.
Our analysis and simulation based evaluation
demonstrate that minimal distance deadlock free
algorithms designed using APSRA methodology outperforms the other algorithm borrowed from fault
tolerant area in terms of adaptivity and latency.
However, the area of a NoC router required by the
APSRA based algorithm is expected to be larger than
the router for the other algorithm. This is because
APSRA requires tables within each router to store
routing information, whereas the other algorithm can
be implemented as an optimized FSM. The table based
implementation of the APSRA based algorithms could
also be a blessing because it allows configurability
(and even dynamic re-configurability) of routing
algorithms to efficiently handle modifications in
communication requirements in the running
applications. Future developments will mainly address
the definition of design space exploration strategies to
optimally determine region placement, shape, and
number of access points.
6. References
[1] Kumar, S., Jantsch, A., Soininen, J-P., Forsell, M.,
Millberg, M., berg, J., Tiensyrj, K., Hemani, A.: A
network on chip architecture and design methodology.
In IEEE Annual Symposium on VLSI (April 2002)
[2] Dally, W.J., Towles, B.: Route Packets, Not Wires: OnChip Interconnection Networks. Design Automation
Conference (DAC), Las Vegas, NV (June 2001)
[3] Bolotin, E., Morgenshtein, A., Cidon, I., Ginosar, R.,
Kolodny, A.: Automatic Hardware-Efficient SoC
Integration by QoS Network on Chip. ICECS (2004)
[4] Pande, P.P., Grecu, C., Ivanov, A., Saleh, R.: Design of
a Switch for Network on Chip Applications, Proc. Int.
Symp. Circuits and Systems (ISCAS), vol. 5, pp. 217220, May 2003.
[5] Glass, C. J., Ni, L. M.: The turn model for adaptive
routing, Journal of the Association for Computing
Machinery, vol. 41, no. 5, pp. 874-902, 1994.
[6] Dally, W.J., Aoki, H.: Deadlock-free adaptive routing in
multicomputer networks using virtual channels. IEEE
Transactions on Parallel and Distributed Systems,
4(4):466--475, (April 1993)
[7] Boppana, R. V., Chalasani, S.: Fault-tolerant wormhole
routing algorithms for mesh networks. IEEE
Transactions on Computer, Vol. 44, No. 7, (1995)
[8] Wu, J.: A Fault-Tolerant and Deadlock-Free Routing
Protocol in 2D Meshes Based on Odd-Even Turn
Model. IEEE Trans. Computers 52(9):1154-1169 (2003)
[9] Chen, K-H., Chiu, G-M.: Fault-Tolerant Routing
Algorithm for Meshes without Using Virtual Channels.
Journal of Information Science and Engineering, Vol.14
No.4, pp.765-783 (December 1998).
[10] Duato, J.: A New Theory of Deadlock-Free Adaptive
Routing in Wormhole Networks. IEEE Trans. on
Parallel and Distributed Systems, 4(12): 1320-1331
(December 2003).
[11] Palesi, M., Holsmark, R., Kumar, S., Catania, V.:
APSRA: A methodology for design of application
specific routing algorithms for NoC systems. Technical
Report DIIT-TR-01-060406, Dip. di Ingegneria
Informatica e delle Telecomunicazioni, Univ. di Catania
(2006)
[12] Chiu, G.-M.: The Odd-Even Turn Model for Adaptive
Routing, IEEE Trans. on Parallel Distribuited Systems,
vol. 11, no. 7, pp. 729-738, 2000.
Acknowledgements