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By
Rohit Singh
Amit Kumar Singh
(M.Tech (VST))
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
Contents
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Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
The difference in speed can be substantial, especially for long data sets where N
may be in the thousands or millionsin practice, the computation time can be reduced by
several orders of magnitude in such cases, and the improvement is roughly proportional
to N /log (N). This huge improvement made many DFT-based algorithms practical. FFTs
are of great importance to a wide variety of applications, from digital signal processing
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
4
and solving partial differential equations to algorithms for quick multiplication of large
integers.
The most well known FFT algorithms depend upon the factorization of N, but
there are FFT with O (N log N) complexity for all N, even for prime N. Many FFT
algorithms only depend on the fact that is an N th primitive root of unity, and thus can be
applied to analogous transforms over any finite field, such as number-theoretic
transforms.
The Fast Fourier Transform algorithm exploit the two basic properties of the
twiddle factor - the symmetry property and periodicity property which reduces the
number of complex multiplications required to perform DFT.
FFT algorithms are based on the fundamental principle of decomposing the
computation of discrete Fourier Transform of a sequence of length N into successively
smaller discrete Fourier transforms. There are basically two classes of FFT algorithms.
A) Decimation In Time (DIT) algorithm
B) Decimation In Frequency (DIF) algorithm.
In decimation-in-time, the sequence for which we need the DFT is successively
divided into smaller sequences and the DFTs of these subsequences are combined in a
certain pattern to obtain the required DFT of the entire sequence. In the decimation-infrequency approach, the frequency samples of the DFT are decomposed into smaller and
smaller subsequences in a similar manner.
The number of complex multiplication and addition operations required by the
simple forms both the Discrete Fourier Transform (DFT) and Inverse Discrete Fourier
Transform (IDFT) is of order N2 as there are N data points to calculate, each of which
requires N complex arithmetic operations.
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
5
N 1
X (K ) x(n) e
n0
j 2nK
N
;
The algorithmic complexity of DFT will O(N2) and hence is not a very efficient
method. If we can't do any better than this then the DFT will not be very useful for the
majority of practical DSP application. However, there are a number of different 'Fast
Fourier Transform' (FFT) algorithms that enable the calculation the Fourier transform of
a signal much faster than a DFT. As the name suggests, FFTs are algorithms for quick
calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm
which reduces the number of computations needed for N points from O(N2) to O(N log N)
where log is the base-2 logarithm. If the function to be transformed is not harmonically
related to the sampling frequency, the response of an FFT looks like a sinc function (sin
x) / x.
The Radix-2 DIT algorithm rearranges the DFT of the function xn into two parts:
a sum over the even-numbered indices n = 2m and a sum over the odd-numbered indices
n = 2m + 1:
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
6
One can factor a common multiplier
equation. It is the two sums are the DFT of the even-indexed part x2m and the DFT of
odd-indexed part x2m + 1 of the function xn. Denote the DFT of the Even-indexed inputs
x2m by Ek and the DFT of the Odd-indexed inputs x2m + 1 by Ok and we obtain:
However, these smaller DFTs have a length of N/2, so we need compute only N/2
outputs: thanks to the periodicity properties of the DFT, the outputs for N/2 < k < N from
a DFT of length N/2 are identical to the outputs for 0< k < N/2. That is, Ek + N / 2 = Ek
and Ok + N / 2 = Ok. The phase factor exp[ 2ik / N] called a twiddle factor which
obeys the relation: exp[ 2i(k + N / 2) / N] = e iexp[ 2ik / N] = exp[ 2ik / N],
flipping the sign of the Ok + N / 2 terms. Thus, the whole DFT can be calculated as
follows:
This result, expressing the DFT of length N recursively in terms of two DFTs of
size N/2, is the core of the radix-2 DIT fast Fourier transform. The algorithm gains its
speed by re-using the results of intermediate computations to compute multiple DFT
outputs. Note that final outputs are obtained by a +/ combination of Ek and Okexp(
2ik / N), which is simply a size-2 DFT; when this is generalized to larger radices below,
the size-2 DFT is replaced by a larger DFT (which itself can be evaluated with an FFT).
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
7
This process is an example of the general technique of divide and conquers algorithms. In
many traditional implementations, however, the explicit recursion is avoided, and instead
one traverses the computational tree in breadth-first fashion.
stage.
assume that algorithmic complexity provides a direct measure of execution time and that
the relevant logarithm base is 2 then as shown in table 1.1, ratio of execution times for
the (DFT) vs. (Radix 2 FFT) increases tremendously with increase in N.
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
8
The term 'FFT' is actually slightly ambiguous, because there are several
commonly used 'FFT' algorithms. There are two different Radix 2 algorithms, the socalled 'Decimation in Time' (DIT) and 'Decimation in Frequency' (DIF) algorithms. Both
of these rely on the recursive decomposition of an N point transform into 2 (N/2) point
transforms.
Number
Complex Multiplications
Complex Multiplication
Speed
of Points,
in Direct computations,
improvement
log2 N
Factor
16
4.0
64
12
5.3
16
256
32
8.0
32
1024
80
12.8
64
4096
192
21.3
128
16384
448
36.6
W nK e
N
..
j 2nK
N
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
9
The radix-2 decimation-in-frequency FFT is an important algorithm obtained by
the divide and conquers approach. The Fig. 1.3 below shows the first stage of the 8-point
DIF algorithm.
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
10
Here
W nk e
j 2nk
N
Consequently, the computation of N-point DFT via this algorithm requires (N/2)
log2 N complex multiplications. For illustrative purposes, the eight-point decimation-in
frequency algorithm is shown in the Figure below. We observe, as previously stated, that
the output sequence occurs in bit-reversed order with respect to the input. Furthermore, if
we abandon the requirement that the computations occur in place, it is also possible to
have both the input and output in normal order. The 8 point Decimation In frequency
algorithm is shown in Fig 1.5.
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
11
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
12
value before being processed into the next stage. This operation is done concurrently and
is known as butterfly process.
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
13
5. Matlab Code for 8 point FFT
% program to calculate 8 point FFT
clear all;
clc;
x=input (' enter the sequence of length 8 ');
tic
s0=zeros(1,8);
s1=zeros(1,8);
s2=zeros(1,8);
s3=zeros(1,8);
N=size(x,2);
if (N < 8 || N > 8)
disp(' sequence is of not proper length ');
else
stage1=[1 1 1 0-1j 1 1 1 0-1j];
stage2=[1 1 1 1 1 0.707-0.707j 0-1j -0.707-0.707j];
p=[0:7]';
t=bitrevorder(p);
% calculation of stage zero
for i=1:N
s0(i)=x(t(i)+1);
end
% calculation of stage one
for i=1:2:N
s1(i)=s0(i)+s0(i+1);
s1(i+1)=s0(i)-s0(i+1);
end
for a=1:N
s1(a)=s1(a)*stage1(a);
end
% calculation of stage two
for i=1:4:N
s2(i)=s1(i)+s1(i+2);
s2(i+1)=s1(i+1)+s1(i+3);
s2(i+2)=s1(i)-s1(i+2);
s2(i+3)=s1(i+1)-s1(i+3);
end
for a=1:N
s2(a)=s2(a)*stage2(a);
end
% calculation of stage three
s3(1)=s2(1)+s2(5);
s3(2)=s2(2)+s2(6);
s3(3)=s2(3)+s2(7);
s3(4)=s2(4)+s2(8);
s3(5)=s2(1)-s2(5);
s3(6)=s2(2)-s2(6);
s3(7)=s2(3)-s2(7);
s3(8)=s2(4)-s2(8);
end
disp(' FFT result ');
s3
toc
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
14
6. VHDL CODE FOR 16 POINT FFT PROCESSOR
FFT MAIN PROGRAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.fft_package.all;
entity Parallel_FFT is
Port ( x : in signed_vector;
y : out
comp_array);
end Parallel_FFT;
component real_input_to_complex is
Port ( input_real : in
signed_vector;
input_comp : out
comp_array);
end component;
component butterfly is
port(
c1,c2 : in complex;
w :in complex;
g1,g2 :out complex
..
--inputs
-- phase factor
-- outputs
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
15
);
end component;
constant w : comp_array := (
("0100000000000000", "0000000000000000"),
("0011101100100001", "1110011110000010"),
("0010110101000001", "1101001010111111"),
("0001100001111110", "1100010011011111"),
("0000000000000000", "1100000000000000"),
("1110011110000010", "1100010011011111"),
("1101001010111111", "1101001010111111"),
("1100010011011111", "1110011110000010"),
("1100000000000000", "0000000000000000"),
("1100010011011111", "0001100001111110"),
("1101001010111111", "0010110101000001"),
("1110011110000010", "0011101100100001"),
("0000000000000000", "0100000000000000"),
("0001100001111110", "0011101100100001"),
("0010110101000001", "0010110101000001"),
("0011101100100001", "0001100001111110")
);
signal s, g1, g2, g3 : comp_array := (others =>
("0000000000000000","0000000000000000"));
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
16
begin
--Real Input value transformed in complex value
sixteen_bits_complex_transform : real_input_to_complex port
map(x, s);
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
17
bf27 : butterfly port
map(g1(10),g1(14),w(4),g2(10),g2(14));
bf28 : butterfly port
map(g1(11),g1(15),w(6),g2(11),g2(15));
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
18
bf48 : butterfly port map(g3(14),g3(15),w(0),y(7),y(15));
end Behavioral;
BUTTERFLY.VHD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.fft_package.all;
entity butterfly is
port(
c1,c2 : in complex;
w :in complex;
g1,g2 :out complex
--inputs
-- phase factor
-- outputs
);
end butterfly;
architecture Behavioral of butterfly is
begin
--butterfly equations.
g1 <= add(c1,c2);
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
19
g2 <= mult(sub(c1,c2),w);
end Behavioral;
FFT PACKAGE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
package fft_package is
type complex is
record
r : signed(15 downto 0);
i : signed(15 downto 0);
end record;
type signed_vector is array (0 to 15) of signed(7 downto
0);
type comp_array is array (0 to 15) of complex;
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
20
end fft_package;
package body fft_package is
--addition of complex numbers
function add (n1,n2 : complex) return complex is
variable sum : complex;
begin
sum.r:=n1.r + n2.r;
sum.i:=n1.i + n2.i;
return sum;
end add;
--subtraction of complex numbers.
function sub (n1,n2 : complex) return complex is
variable diff : complex;
begin
diff.r:=n1.r - n2.r;
diff.i:=n1.i - n2.i;
return diff;
end sub;
--multiplication of complex numbers.
function mult (n1,n2 : complex) return complex is
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
21
begin
prod_aux_r := (n1.r * n2.r) - (n1.i * n2.i);
prod.r:= prod_aux_r(29 downto 14);
prod_aux_i := (n1.r * n2.i) + (n1.i * n2.r);
prod.i:= prod_aux_i(29 downto 14);
return prod;
end mult;
end fft_package;
REAL TO COMPLEX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.fft_package.all;
entity real_input_to_complex is
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
22
Port ( input_real : in
signed_vector;
input_comp : out
comp_array);
end real_input_to_complex;
architecture Behavioral of real_input_to_complex is
component sig_ext_8_to_16_bits is
Port ( sig_in : in
sig_out : out
complex);
end component;
begin
input0 : sig_ext_8_to_16_bits port map (input_real(0),
input_comp(0));
input1 : sig_ext_8_to_16_bits port map (input_real(1),
input_comp(1));
input2 : sig_ext_8_to_16_bits port map (input_real(2),
input_comp(2));
input3 : sig_ext_8_to_16_bits port map (input_real(3),
input_comp(3));
input4 : sig_ext_8_to_16_bits port map (input_real(4),
input_comp(4));
input5 : sig_ext_8_to_16_bits port map (input_real(5),
input_comp(5));
input6 : sig_ext_8_to_16_bits port map (input_real(6),
input_comp(6));
input7 : sig_ext_8_to_16_bits port map (input_real(7),
input_comp(7));
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
23
input8 : sig_ext_8_to_16_bits port map (input_real(8),
input_comp(8));
input9 : sig_ext_8_to_16_bits port map (input_real(9),
input_comp(9));
input10 : sig_ext_8_to_16_bits port map (input_real(10),
input_comp(10));
input11 : sig_ext_8_to_16_bits port map (input_real(11),
input_comp(11));
input12 : sig_ext_8_to_16_bits port map (input_real(12),
input_comp(12));
input13 : sig_ext_8_to_16_bits port map (input_real(13),
input_comp(13));
input14 : sig_ext_8_to_16_bits port map (input_real(14),
input_comp(14));
input15 : sig_ext_8_to_16_bits port map (input_real(15),
input_comp(15));
end Behavioral;
EIGHT TO SIXTEEN
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
24
use work.fft_package.all;
entity sig_ext_8_to_16_bits is
Port ( sig_in : in
sig_out : out
complex);
end sig_ext_8_to_16_bits;
architecture Behavioral of sig_ext_8_to_16_bits is
signal sig_out_real : signed(15 downto 0);
begin
sig_out_real <=
X"ff" & sig_in ;
TEST BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.fft_package.all;
ENTITY fft_cooley_tukey_tb IS
END fft_cooley_tukey_tb;
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
25
comp_array);
END COMPONENT;
--Inputs
signal x : signed_vector:= (others => "00000000");
--Outputs
signal y : comp_array;
BEGIN
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
26
begin
-- hold reset state for 100 ns.
wait for 100 ns;
---
x<=("00000001",
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001"
--
);
--
x<=("00000000",
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
27
--
"00000000",
--
"00000000",
--
"00000000",
--
"00000000",
--
"00000000",
--
"00000000",
--
"00000000",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001",
--
"00000001"
--
);
x<=("00000101",
"00001010",
"00001111",
"00010100",
"00011001",
"00011110",
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University
28
"00100011",
"00101000",
"00101101",
"00110010",
"00110111",
"00111100",
"01000001",
"01000110",
"01001011",
"01010000"
);
wait;
end process;
END;
..
Report by Rohit Singh and Amit Kumar Singh for Self Study-Course, M.Tech. (VST),
Deptt. Of EE,SOE, Shiv Nadar University