CS151B/EE M116C

Computer Systems Architecture

Virtual Memory

Instructor: Prof. Lei He

<LHE@ee.ucla.edu>

Some notes adopted from Reinman at UCLA

Virtual Memory
Goal: every process thinks it has a huge memory
entirely to itself.
Virtual address space: addresses 0 to 2321
- (or 0 to 2641 on machines with 64-bit addressing).
- even if there is much less physical memory.
Virtual memory also provides protection
-
-

One process can t corrupt the data of another

Another user, running on the same machine, can t see your
data

Virtual Memory
Can be seen as another level in the memory hierarchy
Main memory is a cache of a larger memory space.
Disk holds data in VM that doesn t fit in cache
VM may be bigger than disk
cpu
cache

If a process doesn t use the

entire virtual memory, there
will be addresses that have
no storage assigned.

memory

virtual memory
disk

There can be many virtual address spaces

virtual addresses
physical addresses

virtual addresses

disk

Virtual Memory
For historical reasons, it uses different terminology
Cache

VM

Block (line)

page

Cache miss

Page fault

address

Virtual address

How VM differs from memory caches

MUCH higher miss penalty (millions of cycles)!

Therefore:
large pages [analogous to cache line] (4 KB to MBs)
associative mapping of pages (typically fully associative)
software handling of misses (but HW handles hits!!)

write-through never used, only write-back

Many pages
With 64 MByte memory, 4KBytes/page, have 16K pages
- It s not practical to have 16K comparators
- Nor to have software do many comparisons
How can we get virtual memory with full associativity???

Implementation: Page Table

Page table maps
virtual memory
addresses to
physical memory Virntuuamlbpearge
locations
Page may be in
main memory or
may be on disk
Valid bit says
which.

Virtual page number

(high order bits of virtual address)

Page table
Physical page or
disk address
Valid
1
1
1
1
0
1
1
0
1
1
0
1

Physical memory

Disk storage

Address Translation

Virtual address
31 30 29 28 27

15 14 13 12

11 10 9 8

V irtual page number

3210

Page offset

T ranslat ion
2 9 2 8 27

15 14 13 12

11 10 9 8

P hysical page number

3210

Page offset

Physical address
8

Address translation via the page table

Page table register

Virtual address
31 30 29 28 27

1 5 1 4 1 3 12 1 1 1 0 9 8
Vir tual page number

Page offset

20
Valid

3 2 1 0

12
P hysical page number

Page table

18
If 0 then page is not
present in memory
29 2 8 27

15 1 4 13 1 2 11 10 9 8
P hysical page number
Physical address

3 2 1 0

Page offset

How big is the page table?

Answer
Example: 512 MB virtual addresses space, 4 KB pages.
- Then we need 229 / 212 = 217 entries in the page table.
Suppose each entry is 4 Bytes.
- Then page table takes 219 Bytes (a half megabyte)
... and each process needs its own page table.
So part of page table may not even be in cache.
Page table manager is part of Operating System, but ...

We care about performance; can you avoid loading a

page table entry on every memory reference?
Otherwise, VM would slow out-of-cache memory references down
by a factor of two.

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Making Address Translation Fast

Translation lookaside buffer (TLB)
A hardware cache for the page table
Typical size: 256 entries,
1- to 4-way set associative
TLB
V i r tu a l p a g e
nu m b er

V a l id

Ta g

1
1
1
1
0
1

P hy sica l pa ge
a dd res s

P h y s ic a l m e m o r y

P a g e ta b l e
P h y si ca l p a g e
V a li d o r d is k a d d r e s s
1
1
1
1
0
1
1
0
1
1
0
1

D is k s t o r a g e

11

How do cache and VM fit together?

Cache can be virtually addressed ...
the virtual address is broken into tag-index-offset to look up data in
cache

... or physically addressed

the virtual address is first converted to a physical address (using
the page table)
the physical address is used to find data in cache

Virtually addressed caches are faster, but make

sharing data between processes complicated.
One compromise is to use virtual address for the
index and physical address for the tag.

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TLB and Physically Addressed Cache

Virtu a l a dd ress
31 3 0 2 9

15 14 1 3 1 2 11 1 0 9 8
Virtua l p ag e nu mb er

3210

Pa ge o ffset

20

Va lid Dirty

12

P hysic al pa ge n um be r

Ta g

T LB
T L B h it

20

Ph ysica l p a ge nu m be r
Page o ffset
P hy sical ad dre ss
Ph ysica l ad dre ss tag
C ac he in de x
14

16

Va lid

Ta g

B y te
offse t
2

D a ta

Ca ch e

32
Cache hit

D a ta

13

Virtual Memory Key Points

Virtual memory provides:

protection
sharing
performance
illusion of large main memory

Virtual Memory requires twice as many memory

accesses, so we cache page table entries in the TLB.
Four things can go wrong on a memory access:
cache miss, TLB miss (but page table in cache), TLB
miss and page table not in cache, page fault.
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Key Terms

Locality, cache, set-associative cache (direct

mapped, full associative), least recently used (LRU),
block (cache line), tag, index, offset
Cache miss/hit, compulsory (cold start) miss,
capacity miss, conflict miss, miss rate, miss penalty
Cache store: write-through, write-back; write
allocate, write around
Cache valid bit

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Key Terms

Virtual memory, virtual address, physical address

Page, address translation or mapping, page table,
page fault, translation-lookaside buffer (TLB)

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