CS151B/EE116C Solutions to Homework #2

Problem (1) B.24

If there is no overflow, the circuitry shown in Figure B.5.10 is sufficient the Set output from bit 31
(the sign bit) can be used as the Less input for bit 0. However, if there is an overflow, the inverse of
the sign bit must be used as the Less input for bit 0. Both cases are handled correctly by the
following circuitry (replacing the bottom part bit 31 of Figure B.5.10):
Ainvert
Binvert

Operation
CarryIn

1
1
Result
b

1
Less

3
Set

Overflow
detection

Overflow

Less input of bit 0

Problem (2) B.25

Given that a number that is greater than or equal to zero is termed positive and a number that is less than
zero is negative, inspection reveals that the last two rows of Figure 3.2 restate the information of the first
two rows. Because A B = A + (B), the operation A B when A is positive and B negative is the same
as operation A + B when A is positive and B is positive. Thus the third row restates the conditions of the
first. The second and fourth rows refer also to the same condition.
Because subtraction of twos complement numbers is performed by addition, a complete examination of
overflow conditions for addition suffices to show also when overflow will occur for subtraction. Begin
with the first two rows of Figure 3.2, and add rows for A and B with opposite signs. Build a table that
shows all possible combinations of Sign and CarryIn to the sign bit position and derive the CarryOut,
Overflow, and related information. Thus,
Sign
A

Sign
B

Carry
In

Carry
Out

Sign of
Result

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

Correct
Sign of
Result
0
0
1
0
1
0
1
1

Overflow
?
No
Yes
No
No
No
No
Yes
No

Carry In
XOR
Carry Out
0
1
0
0
0
0
1
0

Notes

Carries differ
|A| < |B|
|A| > |B|
|A| > |B|
|A| < |B|
Carries differ

From this table an Exclusive OR (XOR) of the CarryIn and CarryOut of the sign bit serves to detect
overflow. When the signs of A and B differ, the correct sign of result is determined by the relative
magnitudes of A and B, as listed in the Notes column.

Problem (3)
When operating normally, the ALU does subtraction based on the equation:
A B = A + (B)
In those cases, the CarryIn is set to 1 as part of the computation of B. Since the malfunction causes
CarryIn to be 0, the result for subtraction will always be one less than it should be. Specifically, instead of
computing A B, the ALU will compute A B 1.
A user/programmer will observe incorrect results for all instructions that require the ALU to perform
subtraction. Specifically:
A) The sub instruction will compute Rs Rt 1 instead of Rs Rt.
B) The beq instruction will branch whenever Rs = = Rt + 1 instead of whenever Rs = = Rt.
C) The slt instruction will set Rd to 1 whenever Rs < Rt + 1 instead of whenever Rs < Rt.

Solutions to Homework #2
Problem (4)
A OR B
With control lines set to 0101, the Binvert input to the ALU would be set and the output of the OR
gates is selected as the result.

Problem (5)
The only change will be on the result from the slt instruction. Specifically, instead of generating
00000000 or 00000001 as the comparison result, the instruction will generate 00001000 or
00001001, respectively.

Solutions to Homework #2
Problem (6)
A modular 1-bit adder:

Cin

Cout

Truth table for the 1-bit adder:

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Cin
0
1
0
1
0
1
0
1

S
0
1
1
0
1
0
0
1

Cout
0
0
0
1
0
1
1
1

Karnaugh map for S:

S
X

0
1

YCin
00
0
1

01
1
0

11
0
1

10
1
0

S = X YCin + XY Cin + X Y Cin + XYCin

Karnaugh map for Cout:

Cout
X

YCin
00
0
0

0
1

01
0
1

11
1
1

10
0
1

Cout = YCin + XY + XCin

Y
Cin
X
Y

Cout

X
Cin

X
Y
Cin
X
Y
Cin

X
Y
Cin
X
Y
Cin

4-bit adder:

X3

Y3

X2

Y2

X1

Y1

X0

Y0

Cout

Cin

S3

S2

S1

S0

Problem (7)
1 1 1 1

Y
4-bit Adder

Cin

CLK

OUTPUT

Problem (8)
In binary numbers multiplication by 2 can be accomplished by a left shift of 1 bit if ignoring any
overflow. Multiplication by 5 is the same as a multiplication by 4 (left shift of 2 bits) followed
by an addition of the multiplicand itself. In MIPS:
sll
add

Address
10000000
10000100

$17, $16, 2
$17, $16, $17

Op
000000
000000

Rs
00000
10000

# $17 = 4 * $16
# $17 = $17 + $16

Rt
10000
10001

Rd
10001
10001

Shamt
00010
00000

Func
000000
100000

Inst
sll
add