BulkCMOSScaling

totheEndoftheRoadmap
Prof.TsuJaeKingLiu
ElectricalEngineeringandComputerSciencesDepartment
UniversityofCaliforniaatBerkeley

June13,2012
SymposiumonVLSICircuitsShortCourse

TheCMOSPowerCrisis
Astransistordensityhasincreased,thesupplyvoltage(VDD)
hasnotdecreasedproportionately.
PowerdensitynowconstrainsCMOSchipdesign!
PowerDensityvs.GateLength
Power Density (W/cm2)

CMOSVoltageScaling

1E+03

Active Power Density

1E+02
1E+01
1E+00
1E-01
1E-02
1E-03

Passive Power Density

1E-04
1E-05
0.01

0.1

Gate Length (m)

Source:P.Packan(Intel),
2007IEDMShortCourse

Source:B.Meyerson(IBM)
SemicoConf.,January2004
2

SourcesofVariability
Subwavelengthlithography:
Resolutionenhancement
techniquesarecostlyandincrease
processsensitivity

Layoutdependenttransistorperformance:

courtesyMikeRieger (Synopsys,Inc.)

Processinducedstressisdependentonlayout

Randomdopant fluctuations(RDF):
Atomisticeffectsbecomesignificant
innanoscale FETs

SiO2
Source

A.Brownetal.,
IEEETrans.
Nanotechnology,
p.195,2002

Gate
Drain

photoresist

A.Asenov,Symp.VLSITech.Dig.,p.86,2007
3

6-T SRAM Cell

ImpactofMisalignment
Desiredlayout
(6TSRAMcell)
PD

PU

Actuallayoutw/lateralmisalignment
(gatelengthvariations)

PG
Lg reduced

PG

PU

Lg increased

PD

Actuallayout
(cornerrounding)

Actuallayoutw/verticalmisalignment
(channelwidthvariationsduetoactivejogs)

W reduced

W increased

ImpactofVariabilityonSRAM
VTH mismatchresultsin reducedstaticnoisemargin.
lowerscellyield,andlimitsVDD scaling
ButterflyCurves

Y.Tsukamoto(Renesas)etal.,Proc.IEEE/ACMICCAD,p.398,2005

Immunitytoshortchanneleffects(SCE)andnarrowwidtheffects
aswellasRDFeffectsisneededtoachievehighSRAMcellyield.
5

6-T SRAM Cell

DoublePatterningofGate
Desiredlayout
(6TSRAMcell)
PD

PG

PU

Actuallayoutafter1st gatepatterning

PG

PU

PD

Actuallayoutafteractivepatterning Actuallayoutafter2nd gatepatterning

(nogatelengthvariation)

Outline
Review:MOSFETBasics
TheRoadBehind:CMOSTechnologyAdvancement
TheNarrowRoadAhead:ThinBodyMOSFETs
AnAlternativeRoute:PlanarBulkMOSFETEvolution
Summary

MOSFETOperation:GateControl
SchematicCrossSection
Gate
gateoxide

Leff
P

N+
Source

N+

CurrentflowingbetweenSourceandDrain
iscontrolledbytheGatevoltage.
Desiredcharacteristics:
HighONcurrent
LowOFFcurrent

Drain

log ID

ElectronEnergyBandProfile

ION

increasingE

n(E) exp(E/kT)

Source

increasing
VGS
distance

IOFF
Drain

Inverse slope is
subthreshold swing, S
[mV/dec]
GATEVOLTAGE

VTH

VDD
8

ImprovingION/IOFF
Gate

logID

Cox
Cdep
Body

Source

ION

Ctotal
Cox

Drain

VDD

VGS

ThegreaterthecapacitivecouplingbetweenGateandchannel,the
bettercontroltheGatehasoverthechannelpotential.
higherION/IOFF forfixedVDD,orlowerVDD toachievetargetION/IOFF
reducedshortchanneleffectanddraininducedbarrierlowering:
logID
Source
decreasingLg,
orincreasingVDS

Drain

decreasingLg
or
increasingVDS

IOFF
VGS

MOSFETinONState(VGS >VTH)
I D W v Qinv

DRAINCURRENT,ID

v eff

Qinv Cox (VGS VTH )

Gate
Source

Drain

Substrate

DRAINVOLTAGE,VDS

10

EffectiveDriveCurrent(IEFF)
M.H.Naetal.,IEDMTechnicalDigest,pp.121124,2002

CMOSinverterchain:
V1

V2

V3

VDD

VDD

S
D

VIN

D
GND

VOUT

NMOSDRAINCURRENT

VDD/2

V2 t
V3
pLH
V1 tpHL

IH +IL
IEFF = 2

TIME

IDSAT

IH (DIBL=0)

VIN=VDD

IH

VIN=0.83VDD
VIN=0.75VDD

IL

0.5VDD

NMOSDRAINVOLTAGE=VOUT

VIN=0.5VDD

VDD
11

Outline
Review:MOSFETBasics
TheRoadBehind:CMOSTechnologyAdvancement
TheNarrowRoadAhead:ThinBodyMOSFETs
AnAlternativeRoute:PlanarBulkMOSFETEvolution
Summary

OptimizingBulkMOSFETPerformance
TomaximizeION ,heavydopingnearthesurfaceofthe
channelregionshouldbeavoided.
UseasteepretrogradechanneldopingprofiletosuppressIOFF
R.H.Yanetal.,
IEEETrans.ElectronDevices,
Vol.39,pp.17041710,1992.

EnergyBandProfile:
(OFFState)
longer

Structure:

Double-Gate FET

Scale length:

Si
tSitox
2 ox

Ground-Plane FET

Si
t Sitox
2 ox 1 Sitox / oxt Si

Source
Drain

13

0.05

Forward VSUB

0.00
-0.05
-0.10

VSUB =+0.4 V
VSUB = 0.0 V
VSUB = -0.4 V
VSUB =-1.0 V

-0.15
-0.20
0

Vth (Vth-Vth(LG=long)) (V)

(a) nMOS

-0.05

20

40

60
80 100 120 140 160
Gate Length, L G (nm)

Forward VSUB

Forwardbodybiasingreduces
depletiondepthandthereby
improvesMOSFETscalability
Bodyeffectfactorisimproved
withsteepretrogradedoping:
0.40

Simulation result
(10nm nMOS with VF=0.4V)

0.35

(b) pMOS

0.00

Experimental results

0.30

0.05
0.10

VSUB = -0.4 V
VSUB = 0.0 V
VSUB =+0.4 V
VSUB =+1.0 V

0.15
0.20
0

20

40

60
80 100 120 140 160
Gate Length, L G (nm)

A.Hokazono etal.,IEEETrans.ElectronDevices,
Vol.55,pp.26572664,2008

Body bias effect,

Vth (Vth-Vth(LG=long)) (V)

ReducedSCEwithBodyBiasing

45-nm node
0.25
0.20
0.15
0.10

120-nm node

0.05

65-nm node
0.00
0

20 40 60 80 100 120 140 160 180 200

Gate Length, L gate (nm)

14

CMOSTechnologyScaling
XTEMimageswiththesamescale
courtesyV.Moroz(Synopsys,Inc.)

90nmnode

T.Ghanietal.,
IEDM 2003

65nmnode

(afterS.Tyagietal.,IEDM 2005)

45nmnode

32nmnode

K.Mistryetal.,
IEDM 2007

P.Packanetal.,
IEDM 2009

Gatelengthhasnotscaledproportionatelywithdevicepitch
(0.7xpergeneration)inrecentgenerations.
Transistorperformancehasbeenboostedbyothermeans.
15

MOSFETPerformanceBoosters
Strainedchannelregions eff
Highkgatedielectricandmetalgateelectrodes Cox
CrosssectionalTEMviewsofIntels32nmCMOSdevices

P.Packanetal.,IEDMTechnicalDigest,pp.659662,2009

16

CarrierConfinementw/oDoping
R.J.Mearsetal.(MearsTechnologies),2012SiliconNanoelectronicsWorkshop(Paper35)

Inversionchargeisconfinedtobenearthesurface,by
insertingOpartialmonolayerswithinthechannelregion
relaxesrequirementforthintSi
Separationofcarriersubbandsreducesinterbandscattering
carriermobilityisenhanced
Inversionchargedensityprofile

Effectiveelectronmobility

17

Outline
Review:MOSFETBasics
TheRoadBehind:CMOSTechnologyAdvancement
TheNarrowRoadAhead:ThinBodyMOSFETs
AnAlternativeRoute:PlanarBulkMOSFETEvolution
Summary

WhyNewTransistorStructures?
Offstateleakage(IOFF)mustbesuppressedasLg isscaleddown
allowsforreductionsinVTH andhenceVDD

Leakageoccursintheregionawayfromthechannelsurface
Letsgetridofit!
L
g

UltraThinBody
MOSFET:
Gate
Gate
Drain
Drain

Source
Source
BuriedOxide
Substrate

SilicononInsulator
(SOI)
Wafer

19

ThinBodyMOSFETs
IOFF issuppressedbyusinganadequatelythinbodyregion.
Channel/bodydopingcanbeeliminated
higherdrivecurrent(ION)duetohighercarriermobility
Reducedimpactofrandomdopant fluctuations(RDF)
UltraThinBody(UTB)

DoubleGate(DG)

Lg
Gate
Gate
Source

Drain

BuriedOxide

tSi

Drain

Source

tSi

Gate

Substrate

tSi <(1/4) Lg

tSi <(2/3)Lg
20

RelaxingtheBodyThinnessRequirement
AdaptedfromX.Sunetal.,IEEEElectronDeviceLetters,Vol.29,pp.491493,2008

ThinnerBOX reduceddraininducedbarrierlowering
Reversebackbiasing furtherreductionofSCE
2.0 Curves for constant DIBL=100mV/V
LG=28nm, EOT=1.1nm, VDD=1V
ground-plane tri-gate SOI
tri-gate SOI

1.5

Drain
Source
Buried Oxide
Substrate

tSiSi/ /L/L
Leffeff
H
tSi
eff

J.G.Fossumetal.,2004IEDM

1.0

tSi

TBOX =5nm,Vb =1V(NMOS)

0.5
0.0

Gate

WSi

TBOX =10nm
TBOX =

0.5

1.0
1.5
WSi /Leff

2.0

ThickerSOIcanbeusedfor
backgatedFDSOIMOSFETs
21

ThresholdVoltageAdjustment
VTH canbeadjustedviasubstratedoping,forreducedVTH:
TBOX = 10nm

T.Ohtouetal.,IEEEEDL28,p.740,2007

VTH canbedynamicallyadjustedviabackbiasing.

Reversebackbiasing(toincreaseVTH)isbeneficialforloweringSCE.
S.Mukhopadhyayetal.,IEEEEDL27,p.284,2006
22

UTBBSOIFETTechnologyChallenges
C.FenouilletBeranger
etal.,IEDM2009

Highersubstratecost
cannotbeoffsetbysimplerprocess,ifthinBOXandRBBareused

Mobilityenhancement
EmbeddedS/DstressorsarenotaseffectiveasforbulkMOSFETs
Integrationofadvancedchannelmaterials?

Systemonchip(SoC)requirements
Implementationofmultiplegateoxidethicknesses STIrecess
practicallowerlimitforTBOX
23

DoubleGateFinFET
PlanarDGFET

FinFET

Lg

Lg

Gate

Drain
D.Hisamotoetal.,IEDM
TechnicalDigest,1998

Gate
Source

Drain

tSi Source
Gate

N.Lindertetal.,IEEEElectron
DeviceLetters,p.487,2001

FinHeight
HFIN =W/2

FinWidth=tSi

GATE

20nm

DRAIN

15nmLg FinFET:

10nm

Y.K.Choi etal.,
IEDMTechnicalDigest,2001

SOURCE

24

DoubleGatevs.TriGateFET
TheDoubleGateFETdoesnotrequireahighlyselective
gateetch,duetotheprotectivedielectrichardmask.
Additionalgatefringingcapacitanceislessofanissuefor
theTriGateFET,sincethetopfinsurfacecontributesto
currentconductionintheONstate.
DoubleGateFET

TriGateFET

channel
afterM.Khare,2010IEDMShortCourse

25

IndependentGateOperation
ThegateelectrodesofadoublegateFETcanbeisolated
byamaskedetch,toallowforseparatebiasing.
Drain
Onegateisusedforswitching.
Gate1
Gate2
TheothergateisusedforVTH control.

Back
Gated
FET

Source

D.M.Friedetal.(CornellU.),
IEEEElectronDeviceLetters,
Vol.25,pp.199201,2004

L.Mathewetal.(FreescaleSemiconductor),
2004 IEEEInternationalSOIConference
26

FinFETLayout
LayoutissimilartothatofconventionalMOSFET,except
Pfin
thatthechannelwidthisquantized:
Source
Gate

Source
Gate

Drain

Drain

Source

Source

BulkSiMOSFET

FinFET

TheS/Dfinscanbemergedbyselectiveepitaxy:

Intel
Corp.
M.Guillornetal.(IBM),Symp.VLSITechnology2008

27

FinDesignConsiderations
FinWidth

Gate Length

Limitedbyetchtechnology
Tradeoff:layoutefficiency
vs. designflexibility

FinPitch
Determineslayoutarea
LimitsS/Dimplanttiltangle
Pfin
Tradeoff:performancevs.layoutefficiency

Drain

FinHeight

Source

DeterminesSCE

Fin Height
Fin Width

28

ImpactofFinLayoutOrientation
L.Changetal.(IBM),SISPAD 2004

(Seriesresistanceismore
significantatshorterLg.)

Ifthefinisoriented||or to
thewaferflat,thechannel
surfacesliealong(110)planes.
Lowerelectronmobility
Higherholemobility
Ifthefinisoriented45 tothe
waferflat,thechannelsurfaces
liealong(100)planes.
29

BulkFinFET
FinFETs canbemade
onbulkSiwafers
lowercost
improvedthermal
conduction

withsupersteep
retrogradewell
(SSRW)orpunch
throughstopperat
thebaseofthefins
90nmLg FinFETs
demonstrated
Wfin =80nm
Hfin =100nm
DIBL=25mV
C.H.Leeetal. (Samsung),SymposiumonVLSITechnologyDigest, pp.130131,2004

30

Bulkvs. SOIFinFET
(comparedtoSOIFinFET)

H.Bu (IBM),2011IEEEInternationalSOIConference

31

22nmFinFETs

C.C.Wuetal.(TSMC),IEEEInternationalElectronDevicesMeeting,2010

22nm/20nmhighperformance
CMOStechnology
Lg =25nm
XTEMImagesofFin

32

FinFETvs.UTBBSOIMOSFET
CrosssectionalTEMviews
of25nmUTBSOIdevices
NFET

TSi =5nm

PFET

TSi =5nm

K.Chengetal.(IBM),Symposiumon
VLSITechnologyDigest,pp.128129,2011

B.Doris(IBM),2011
IEEEInternationalSOI
Conference

*C.C.Wuetal.
(TSMC),IEDM 2010

33

RemainingFinFETChallenges
VTH adjustment
Requiresgateworkfunction(WF)orLeff tuning
DynamicVTH controlisnotpossibleforhighaspectratiomultifindevices

Fringingcapacitancebetweengateandtop/bottomofS/D
Mitigatedbyminimizingfinpitchand
usingviacontacted,mergedS/D
M.Guillorn,Symp.VLSITechnology2008

Parasiticresistance
UniformS/Ddopingis
difficulttoachievewith
conventionalimplantation

Conformaldopingisneeded
e.g.Y.Sasaki,IEDM2008

H.Kawasaki,IEDM2008

Variability
Performanceisverysensitivetofinwidth
WFvariationdominantforundopedchannel
T.Matsukawa,Symp.VLSITechnology2008

34

ImpactofRDFonFinFETs
V.Varadarajan etal.,Proc.IEEESiliconNanoelectronics Workshop,pp.137138,2006

Channel/bodydopingcanbeeliminatedinthinbodyFETs
suchasthedoublegateFinFET,tomitigateRDFeffects.
However,duetosource/draindoping,atradeoffexists
betweenperformance&RDFtoleranceforLg<10nm:
IONvs.TSi

IOFF andVT vs.TSi

1E-4

SD = 3nm

75
VT (mV)

IOFF (A / m)

1E-6

50

1E-8

Lg =9nm,EOT=0.7nm

1E-10

25
4.5

SD = 3nm

100

5.5

TSi (nm)

6.5

ION (mA / m)

FinFETwithatomistic
S/Dgradientregions:

0.8

0.4

4.5

5.5

TSi (nm)

6.5

35

Outline
Review:MOSFETBasics
TheRoadBehind:CMOSTechnologyAdvancement
TheNarrowRoadAhead:ThinBodyMOSFETs
AnAlternativeRoute:PlanarBulkMOSFETEvolution
Summary

QuasiPlanar(QP)BulkMOSFET
M.Kito etal.(ToshibaCorp.),2005Symp.VLSITechnology

ThequasiplanarbulkFETstructureis
easilyachievedbyslightlyrecessingthe
isolationoxide,orbyselectiveepitaxial
growth,priortogatestackformation
Retrogradedopinghelpstosuppress
SCE,sothatWSi canbegreaterLg
Bodybiaseffectcanberetained

XTEMimages
polySi
gate

polySi
gate

Si

Si

Incontrasttothe
FinFET/MuGFET
MeasuredIVCharacteristics

Superiorelectrostaticintegrityis
achievedwithquasiplanarstructure
reducedimpactofprocessinduced
variations
facilitatesvoltagescaling
37

QuasiPlanar28nmCMOSTechnology
C.Shinetal.,2010ESSDERC

ExperimentperformedatUMCinearly28nmCMOStechnology
Individuallogictransistorsand6TSRAMarraysfabricated
~2500cellperdeviceundertest(DUT)
Dualstresslinersforperformanceenhancement
CMOSfrontendoflinesteps
SRAMcellplanviewSEM
STI Formation
Well & VT Implants
STI Oxide Recess 0or15nm
Gate Ox./Poly Deposition
Gate Patterning
LDD & Pocket Implants
Spacer & S/D Formation
Activation Process
Salicidation

XTEMalonggateelectrode

cellarea=0.149um2

PKTdosesplit:StandardorLight
38

MeasuredQPBulkCMOSResults
C.Shinetal.,2010ESSDERC

IOFF statistics

SaturationVT statistics

PMOSPullUp

NMOSPullDown

ION statistics

QuasiplanarION ishigher,forcomparableIOFF
2xincreaseforNMOS,4xincreaseforPMOS

QuasiplanarVTH
variationislower

39

BodyBiasEffectandCompactModel
C.Shinetal.,2010ESSDERC

ThestandardbulkMOSFETcompactmodelcanwellpredict
quasiplanarMOSFETperformance includingbodybiaseffect
NMOS
1.4E-05

Control Vbs=0
Control Vbs=0.2

3.6E-05

PU Drian Current Id (A)

PG Drain Current Id (A)

4.2E-05

PMOS

RECESS=15nm Vbs=0

3.0E-05

RECESS=15nm Vbs=0.2

2.4E-05
QuasiPlanar

1.8E-05
1.2E-05

Planar

6.0E-06

Control Vbs=0

1.2E-05

Control Vbs=-0.2
RECESS=15nm Vbs=0

1.0E-05

RECESS=15nm Vbs=-0.2

8.0E-06
6.0E-06

QuasiPlanar

4.0E-06
Planar

2.0E-06
0.0E+00

0.0E+00
0

0.2

0.4

0.6

0.8

Drain Voltage Vd (V)

-1

-0.8

-0.6

-0.4

-0.2

Drain Voltage Vd (V)

40

Bulkvs.SOIMultiGateFETDesigns
X.Sunetal.,IEEEElectronDeviceLettersVol.29,pp.491493,2008

QuasiPlanarBulkMOSFETStructure

tSi /Leff

EOT=1.1nm

BulkMuGFET

tSi relaxed
SOIMuGFET

Wsi /Leff
Thin/narrowbodyrequirementisrelaxedwithretrogradedoping
The bulkMOSFETstructureachievesbetterlayoutefficiency!
41

SimulatedImpactofHSTRIPE Variation
3Ddevicesimulationresults,tobepublishedbyX.Sunetal.

LG =20nm,EOT=0.9nm,WSTRIPE =20nm
0.42

TSi = XJ,EXT = HSTRIPE

TSi = XJ,EXT = 14nm

VT_LIN (V)

0.39
0.36
0.33
0.30
0.27

12

13
14
15
HHSTRIPE
STRIPE (nm)

16

IftSi isfixed,VT isnotsensitivetoHSTRIPE variation.

42

PerformanceComparisonwithFinFET
3DdevicesimulationswereperformedforMOSFETsdesigned
toachieveminimumintrinsicdelayatagivenIOFF specification:
ForLG=25nm,IOFF=8nA/m
ForLG=20nm,IOFF=18nA/m

Theintrinsicdelayadvantageof
theQPFETincreaseswithscaling.

2.0

15

Planar bulk

1.5

FinFET SOI

37%reduction

1.0
0.5
0.0 W

Si

Leff

25nm 25nm 15nm

20nm 20nm 12nm

21nm 27nm 34nm

18nm 22nm 28nm

LG=25nm

81%reduction

QP
Bulk bulk
Tri-Gate

LG=20nm

86%reduction

|dVT/dWSi| (mV/nm)

34%reduction

Intrinsic Delay (ps)

TheQPFETislesssensitiveto
WSTRIPE variationthantheFinFET.

10

0W

Si

Leff

Xin SunPh.D.thesis,UCBerkeley,2010

25nm 15nm

20nm 12nm

27nm 34nm

22nm 28nm

LG=25nm

LG=20nm

43

VTH AdjustmentApproaches
C.Shinetal.,IEEE2008SiliconNanoelectronicsWorkshop

VTH ofaquasiplanarbulkMOSFETcanbeadjustedbytuning
eitherthedose (Npeak)orthedepth (tSi)oftheretrogradedoping.
200atomisticsimulationswererunforeachnominaldesign.

VTH adjustmentviatSi tuningprovidesforlessvariation,and

eliminatesthetradeoffwithshortchannelcontrol.

Lg =20nm
EOT=0.9nm
WSTRIPE=20nm
HSTRIPE =14nm
Weff =44nm
tSi =14nm
XJ =14nm

DIBLvaluesfor
eachdesignare
indicated

44

SegmentedChannelMOSFET(SegFET)
Thechannelisdigitizedintostripesofequalwidth,
isolatedbyveryshallowtrenchisolation (VSTI)oxide
TheVSTIoxideisdeeperthanthesource/drainextensions.
Devicewidthisadjustedbyadjustingthenumberofstripes.
Eachstripeisa(quasiplanar)bulkMOSFET.

Thedeepsource/drainregionsremaincontiguous.
CrossSectionalViews

PlanView

activedevice
gate
region
electrode
very
shallow
trench
isolatio
n
regions

Lg

fieldregion(STI)

A A

B B

WSTRIPE
B

A
C

C C
HSTRIPE

C
XJ

n+

TSi n+
p

XVSTI

gateelectrode

SiO2

WSTRIPE

WVSTI
pSi

pSi

pSi

T.J.KingLiuandL.Chang,TransistorScalingtotheLimit,inIntotheNanoEra,H.Huffed.(Springer),2008.
45

SegmentedChannelMOSFETFabrication
T.J.KingandV.Moroz,U.S.Patent7,265,008

1. Start with corrugated

substrate

VSTI
dielectric

2. Define active 3. Fill trenches to form

areas
STI; Implant wells

STI oxide

Si

5. Implant channels;
Form gate stack
Gate
electrode

4. Slightly recess the

isolation oxide (optional)

6. Form S/D extensions,

then sidewall spacers

7. Embed/grow epitaxial
material in S/D regions
(optional)

8. Dope S/D regions;

Form silicide

LG

WSTRIPE

Precisecontrolofchannelwidthisachieved
(Layoutdependencies,sensitivitytomisalignmentarereduced)

variationinMOSFETperformanceisreduced

46

FirstDemonstrationofSegFET
B.Hoetal., InternationalSemiconductorDeviceResearchConference2012

PlanViewSEMImage

XTEMalongAA

MeasuredIVCharacteristics

(Currentsarenormalizedtolayoutwidth)

SegFETshavereducedSCEand
comparableareaefficiencyas
conventionalplanarMOSFETs. 47

ImpactofChannelWidthonStrainProfile
Cappinglayerinducedstrainalongthechannel
Wide Channel

Narrow Channel

SegmentedFET
(bulktrigate)

Planar

Contactetchstoplineris
assumedtobea30nm
thicksiliconnitridewith
2GPatensilestress

SegFETparameters:
WSTRIPE=20nm
WSPACING=20nm
HSTRIPE=10nm

LG=20nm
EOT=0.9nm
TGATE =40nm
LSPACER =20nm

MorestressisinducedinSegFET More mobilityenhancement

ReducedvariationwithWeff forSegFET Reducedeff variation
Xin SunPh.D.thesis,UCBerkeley,2010

48

Si1xGex PChannelSegFET
B.Hoetal., Symp.VLSITechnology 2012(Paper19.4 )

XTEMalongGate

HoleMobility

ShortChannelEffect

MeasuredIVCharacteristics

TheSegFET exhibits
higherlinearVT (dueto
reducedbiaxialstrain)
largerdrivecurrentper
unitlayoutwidth
(Currentsarenormalizedtolayoutwidth)

49

LayoutWidthDependence
B.Hoetal., Symp.VLSITechnology 2012

SaturationThresholdVoltage

LinearDriveCurrent

SegFETsshowdramaticallyreducednarrowwidtheffects.
50

Outline
Review:MOSFETBasics
TheRoadBehind:CMOSTechnologyAdvancement
TheNarrowRoadAhead:ThinBodyMOSFETs
AnAlternativeRoute:PlanarBulkMOSFETEvolution
Summary

MOSFETEvolution
32nm
planar

22nm
multigate
segmentedchannel

beyond10nm
stackednanowires?

3D:

IntelCorp.

quasiplanar:

P.Packanetal.(Intel),
IEDM2009

B.Ho(UCB),ISDRS 2011

C.Dupretal.(CEALETI)
IEDM2008

Stackedgateallaround
(GAA)FETsachievethe
highestlayoutefficiency.
52

Summary
Powerdensityandvariabilitynowlimittransistorscaling.
Designswhichachieveimprovedgatecontrolareneeded!

ThinbodyMOSFETsolutionsarerevolutionary,and
introducechallengesfordesignand/ormanufacturing.
QuasiplanarbulkMOSFET(SegFET)technologyoffersan
evolutionary (lowcost)pathwaytolowerVDD andVTH.
utilizesconventional(established)ICfabricationtechniques
iscompatiblewithalltechnologiesdevelopedforbulkCMOS

Segmentedchanneldesignswillbeadoptedat22nm
forlowerpowerconsumptionand/orimprovedperformance

toenablebulkCMOStechnologyscalingtotheend.
53

SegFETataGlance
SegFET isaproventransistordesignbasedonsegmentingonly
thechannelregionofastandardplanarMOSFET.
NotaFinFET:nearlyplanar, i.e.nohighaspectratiofins
UsessameretrogradechanneldopingasaplanarMOSFETtosuppressthe
shortchanneleffect;allowsbodybiasingtobeused.

ImprovesCMOSpowervs. performanceatpresentnode;
issuperiortothinbodyMOSFETstructuresforfuturenodes.
EasiestandhighestperformanceapproachtoextendMoores
Lawtotheendofthetechnologyroadmap(sub10nmCMOS)
Inexpensivebarriertoadoption
Requiresoneadditionalmask whichcanbeusedformultipledesigns
UsesexistingdevicefootprintsandEDAtools
Requiresnoprocesstoolchangesornewmaterials
54

Acknowledgments
Collaborators:
X.Sun(nowwithIBMMicroelectronics),C.Shin(nowwithU.
Seoul),B.Ho(UCB)
V.Moroz andQ.Lu(Synopsys)
M.Tomoyasu,Y.Akasaka,K.Maekawa,T.Sako (TEL)
C.P.Chang,S.Kuppurao,Y.Kim,S.Chopra,V.Tran,B.Wood
(AppliedMaterials)
C.H.Tsai,S.H.Tsai,C.F.Chang,Y.M.Tseng,R.Liao,R.M.Huang,
P.W.Liu,C.T.Tsai,C.W.Liang(UMC)
B.Y.Nguyen,C.Mazure,O.Bonnin (Soitec)

Funding/Support:
Synopsys,Inc.,TokyoElectronLtd.,AppliedMaterials
UnitedMicroelectronicsCorporation
SemiconductorResearchCorporation
55