Advanced in The VLSI Design Flow PDF

Advances in the Nanometer VLSI
Design Flow
By Venkatesh Prasad
02/26/09
Nanochip Offering: RV-VLSI

Established in 2006
Conceived, implemented and managed by
Nanochip under its ECS business line in

collaboration with RV group of educational
institutions
8000 sq ft talent incubation center
Located in the center of the city
Company Confidential
www.nanochipsolutons.com
ECS Offerings
Educational Consultancy Services (ECS)
Academics
VLSI,
Embedded TTP course material
oIndustry Approved
Setting
up and managing finishing schools
Product Companies
Domain
specific advanced and on-boarding
Corporate Training
Educational Consulting
Service
Manages RV-VLSI Design Center on behalf of RV
Group of Educational Institutions
RV-VLSI Class Rooms

Experiential Learning
Shrama -I
RV-VLSI Design Center

Imparting Experience
Abhyas
TALENT INCUBATION CENTER
RV-VLSI Datacenter
Multi CPU machines
Access through SUNRAY
Linux 64 bit architecture
Industry Standard EDA tool access
Access to latest processes and
technology
RV-VLSI Team
Dedicated fulltime Faculty with domain expertise
B. K. Srinath
25 yrs, Ex- BEL, Ex-TI
Fullcustom, PD and CAD
Dr. Preetham Lakshmikanthan Phd.
10 yrs, Ex-Intel
RTL Verification, SV, FPGA
Vibhav T
Gold Medalist IIT-B
25 Yrs Ex- TEL
RTL Design, FPGA, System Design
RV-VLSI: Enrollment Statistics

Total No. of students enrolled till date
1512
Students from different Colleges

nationwide
> 300 Colleges
Students from no. of States
18 -- (Highest AP, Second highest is

Delhi NCR
No. of Countries
6 -- (USA, UK, Germany, Dubai,

Singapore, Australia)
No. of Product Companies for

Placement
Around 25 Product Companies
No. of Service Companies for

placement
More than 42 Service Companies
A bit of history
info@nanochipsolutions.com
www.nanochipsolutions.com
10
It all started in 1947
11
Picture Of First IC
Jack Kilby with his notes

Today a Billion Transistor are packed in one chip
ever wondered how this is designed, fabricated
and what challenges come along the way ?
Source: http://www.ti.com/corp/docs/kilbyctr/downloadphotos.shtml
12
Layout of an IC say a
decade ago
I/O Ring
Analog
I/O Ring
Analog
Digital Block
Memories
FPS: State Of The Art Flows, Proven IP And Efficient

Communications With Global Teams
13
Layout of an IC just a few

years ago
I/O Ring
Memories
Digital Block
Analog
I/O Ring
14
Layout of a Typical IC -Today

I/O Ring
Memories
Digital Block
Analog
M2
I/O Ring

15
Sample Layouts
11460 x 8000
10580 x 7840
8 layer metal
6 layer metal
16
Sample Layouts
Die size is 4609.6 x 6410.6
15,887,555 devices
18,757,178 devices
17
Yesterdays Chip Todays Block

-- SOC
18
Basic Design Flow

Specifications
Arch & Circuit Design
Question:
Simulation
Have these BASIC steps

changed ?
Layout, checks &

fabrication
Post Silicon Validation
19
ASIC AMS VLSI Design Flow

Concept
Design (FE)
Implementation
Physical Design (BE)
MRD
Micro
Architectural
RTL
Analysis
P&R
CTS
Specification
RTL
Synthesis &
STA analysis
PEX and
BA
Architectural
Specification
Verification
DFT
DRC &LVS
TO
20
Design Challenges
Market Pressures
Designs must work at a high frequency
Must consume less power
Must be cheap (small die size or area and yield)
Improving one will make the other two worst do you

Know why ??
21
The Power Optimization Landscape

n
System architecture level

SW-HW partitioning
Single core vs Multi cores
Bus and memory architecture
Micro-architecture level
Frequency and voltage scaling

Memory/register file banking
Auto-inferencing of appropriate FIFOs
Opportunity to Influence Power

System Design/Architecture
Algorithms, Pipelining, Sharing, Power Domains
RTL
Clock gating, Power gating
RTL
Physical
Clock tree, multi-Vth
Combinational, sequential clock gating

Memory, data gating
Power gating
Mfg
Gate/Physical implementation
Multi-Vdd, Multi-Vth technology mapping

Clock network optimization
2013 Mentor Graphics Corp.
22
Low Power Session - Verification Seminar
www.mentor.com
Low Power Design and Verification Flow
RTL can remain untouched and reused; UPF adds power intent
n RTL + UPF verification

Ensures that the power architecture
is complete and consistent with
expected power states of the design
Ensures that the design will work
correctly under power management
with this power architecture
n RTL + UPF implementation
Synthesis, test insertion, place &
route, etc.
UPF may be updated by the user or
the tool
n NL + UPF verification
Power aware equivalence checking,
static analysis, simulation, emulation,
etc.
23
IEEE Std 1801-2009
UPF
UPF
RTL
Synthesis
UPF
Netlist
Place & Route
Simulation, Power Analysis/Optimization,

Logical Equivalence Checking,
n RTL is augmented with UPF

To define the power architecture for
a given implementation
UPF
Netlist
www.mentor.com
Questa PASim Native Simulation of RTL+UPF

Just a switch on normal RTL or GLS simulation
Test
Bench
HDL
User PA
Models
UPF
Compile
n
Compile as usual
No change in source code
Optimize with PA options

Process UPF power intent
Read Liberty libraries as needed
Run static PA checks
Liberty
Optimize
Simulate
---------------------------------------------------------------- QuestaSim Power Aware Design Element Report File --------------------------------------------------------------------------------------------------------------------------PD_top: {Path1} = scope /testbench/axi_dut <>
PD_top: {Path337} = scope /testbench/axi_dut/fpu_inst

PD_top: {Path338} = scope /testbench/axi_dut/pcu_inst
PD_top: {Path339} = scope /testbench/axi_dut/pcu_inst/sys_pcu/pcu1
PD_top: {Path340} = scope /testbench/axi_dut/pcu_inst/sys_pcu/pcu2
PD_top: {Path341} = scope /testbench/axi_dut/mem_inst
-------------------------------------------------------------- QuestaSim Power Aware Architecture Report File -------------------------------------------------------------PD_fpu: {Path342} = scope /testbench/axi_dut/fpu_inst/fpu_dut <>
PD_fpu: {Path343} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_post_norm_sqrt

---------------------------------------------------------PD_fpu: {Path344} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_sqrt
Power Domain: PD_fpu, File: /home/work/dpframe/upf/subsys.upf(10).
PD_fpu: {Path345} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_pre_norm_sqrt
Creation Scope: /testbench/axi_dut
PD_fpu: {Path346} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_post_norm_div
Primary Supplies:
PD_fpu: {Path347} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_serial_div
power : /testbench/axi_dut/IVDD_0d81
PD_fpu: {Path348} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_pre_norm_div
ground : /testbench/axi_dut/VSS
Power Switch: fpu_sw, File: /home/work/dpframe/upf/subsys.upf(64).
Output Supply port:
vout_p(/testbench/axi_dut/IVDD_0d81)
Input Supply ports:
1. vin_p(/testbench/axi_dut/VDD_0d81)
Control Ports:
1. ctrl_p(/testbench/axi_dut/pcu_inst/pd1_pwr_on)
Switch States:
1. normal_working(ON) : (ctrl_p)
2. off_state(OFF) : (!ctrl_p)
Simulate with PA options

Generate reports/Testplan
Visualize/debug power-managed
behavior
24
www.mentor.com
Questa Power Aware Verification
Automatic checks and UPF/Power Aware Reports

Power Architecture Checks:
Power Control Sequence Checks:
Isolation cells
Isolation cells are inserted

where required by power state
definitions
Isolation cells correctly handle
dynamic signal behavior
n
n
n
Level shifters are inserted

where required by power state
definitions
Inputs do not toggle during power down

Retention/Isolation power is on and
stable during power down
Retention registers are saved before

power down
Latch enable is correctly set when

retention occurs
Primary power is on and stable during

power up
Non-retention registers are reset at
power up
Power control signals do not glitch
Level shifters
n
Clock is disabled during power down

Isolation is enabled during power down
Level shifters shift in correct

direction
Level shifters correctly handle

dynamic signal behavior
25
www.mentor.com
Evolution of Verification
Process
Increasing number of features, hence increasing complexity of verification process
Verification by forcing all combinations

of test vectors in a simulator
Verification by writing
sophisticated test benches
Verification done by
design engineer
Verification done by a
verification engineer
Verification methodology which incorporates

a complex suite of test benches
Verification done by teams of

verification engineers
26
Major factors for bugs in

chips
Reasons
Percentage of designs going for respin
27
Functional testing of a
mobile phone
Phone calls
Messages
Games
Call + Games+Message
Message + Games
Corner cases
Call + Games
Functional
Testing
Call + Message
Games
Basic cases
Message
Call
0
10
20
30
40
Y-Axis: features
50
60
70
X-Axis: % usage of a feature

28
Bug rate as the design

matures
As the design
matures number of
bugs detected will
reduce
Initially lots
of Bugs are B u g S t a t u s
found in the
design
180
160
140
Inc rem ent

s
120
C rea ted
Assig ned
100
S ta tu s
F ix ed
C losed
80
Mov ed
Tota l
60
40
20
0
41
0.
0
40
39
6.
0
40
38
2.
0
40
36
8.
0
40
35
4.
0
40
34
0.
0
40
32
6.
0
40
31
2.
0
40
29
8.
0
40
28
4.
0
40
27
0.
0
40
25
6.
0
40
24
2.
0
40
22
8.
0
40
40
21
4.
0
0.
20
40
40
18
6.
RTL
Freeze
point
D a te
29
Verification Gap
The big challenge confron/ng the industry
30
SV/UVM to the rescue

The big challenge confron/ng the industry
Verilog used to Verify designs
System Verilog and UVM used to reduce

Verification gap
31
Cell-Aware Test in a Nutshell

n
Traditional ATPG uses fault models that rely on fortuitous detection of

cell-internal defects
Cell-Aware ATPG improves detection by deterministically targeting

defects internal to standard cells
Defect type & location is derived from the layout of the cell
2. Extract
4. Model
S0
S1
D0
D1
D2
D0
D1
5. ATPG
1. Layout
D2
S0
S1
3. SPICE SIM
32
www.mentor.com
Hierarchical DFT Capabilities

n
Ability to wrap/isolate individual cores/blocks
Core level ATPG patterns reused at top level

Patterns automatically retargeted to
top level and merged with other cores
Patterns for duplicate cores only
generated once and retargeted to
all instantiations
Gray box generation for cores

enables top level ATPG without
need for complete gate level
netlist
core 2
Cores with DFT and test patterns completely reusable in

any SoC
33
core 1b
core 1a
www.mentor.com
Timing Closure: Need for

CRPR
l
Stands for Clk Reconvergence Pessimism Removal

l
If launching and capturing clocks share a common path,

the delay difference in common path due to usage of
different derates will add additional pessimism to both
setup and hold analysis.
CRPR is used to remove this pessimism
D
1.85
A
FF1
1.67
A Y
B2
CK Q
1.5
B1
Common path
1.77
A Y
B3
D
FF2
Setup = 0.3
Numbers beside the

gates show delays for
the respective cell.
Timing derates:
Launch path: 1.1
Capure path: 0.9
34
34
Timing Closure: Need for

Path-Based Analysis
l
Path-based analysis on the other hand, propagates slew belonging to

the timing path under analysis
-
For timing paths between A1 and A5, slew at pin A of A5 is used
For timing paths between A2 and A5, slew at pin B of A5 is used
A1
A4
A
B
A
A
B
A2
A3
A5
35
35
Timing Closure: Advanced

OCV (AOCV)
l
OCV applies a constant derate to the timing paths.

l
Timing Path spanning larger physical distance tends

to have larger systemic variations. Example: variation
in gate length of transistors
Timing Path with large logic depth (or large number of
gates) have more number of gates which tend to
cancel out variations resulting in reduced overall
variation.
AOCV reduces this pessimism by using the location and

logic depth of each path analyzed
36
36
Need for Composite Current

Source (CCS)
l
Until 90nm process node, timing libraries used NLDM (NonLinear Delay Modeling).
l
Some of the advantages of CCS (Composite Current

Source) delay model are
-
-
-
-
Accurate modeling of high impedance interconnect

Accurate slew calculation
Supports Temperature scaling
Supports timing calculation in designs using
multiple supply voltages
CCS is the default timing library model used in 90nm and

below process nodes
37
37
Continuously Increasing Physical Verification,

Circuit Verification, and DFM Complexity
2.5D / 3D-IC
Pattern Match
Pattern Match
RDR /On-grid / Onpitch checks
RDR /On-grid / Onpitch checks
Dummy / SmartFill
SmartFill (DP)
Litho checks:
IP
Litho checks:
IP / full chip
Litho checks:
IP / full chip (DP)
PEX
PEX
ADP
ADP (DP)
LVS
LVS
LVS
LVS
LVS / Hyper Compare
Single-dimension PV
Single-dimension PV
Single-dimension PV
Multi-dimension PV
Multi-dimension PV
2002
130 nm
2006
90 nm
2008
65 nm
2010
40/28nm
2012
20/16/14 nm
Dummy Fill
Critical Area
Critical Area
Recommended Rule /
CFA / MAS
Recommended Rule /
CFA / MAS
Comprehensive
Reliability
checks
Spot Reliability checks
www.mentor.com
Recommended
2.5D / 3D-IC
Required
FinFET:
PV, CV, DFM
Double Patterning
(DP)
Delta-Voltage DRC/
PERC checks
Do I Have To? How Bad Could It Be?

Single Pattern
Double Pattern
www.mentor.com
Performs: coloring, checking, &

decomposition
Why Calibre?
Original Drawn Layer
Calibre MP is the golden in TSMC, ISDA

R&D, Samsung, etc
Golden sign-off in combined nmDRC/MP
deck
Faster debug with patented warning rings
Calibre RealTime debug
Two Mask Layers & Error Rings
Two Mask Layers w/Cuts & Error Rings
Calibre InRoute & Calibre AutoFix
AMD TRM
www.mentor.com
Pattern Match with Calibre in 3 steps
1.
2.
3.
Specify layout path and type

Specify output result database
Input layer map
///*Pattern Matching Steps*///
Include pattern matching library
Call pattern matching with
associated input layers
Output pattern matches to the
results database
Use pattern matches as input to
another operation
Output modified pattern matches
to the result database
Capture and export a

pattern with a Calibre
layout viewer
Add pattern match

checks to a Calibre SVRF
rule file
Execute pattern
matching and view
results with Calibre RVE
www.mentor.com
IR Drop distribution in a typical

chip Wire-bond Package
42
Current Trend-- Flip-chip

Die
Solder bumps
Substrate
BGA
Bumps attached to the die
43
Design Specs-- Present

Specifications:
complex to very complex
Operating Voltage :
600mv to 900mv
Transistor Feature Size: 15nm

Number of Transistors : Up-to 7 Billion say
I/Os:
A few hundred
Team Size:
Sixty Engineers
Design Cycle Time:
6 to 8 months
Post silicon Validation:
DFT
44
We have come a
long way
A Typical DSM Fab must meet
Class 2 20
Generally has the capability of
handling 12 wafers
Costs about USD 6 Billion!!!
45
Summary
In this Field the only thing constant is change
New tools, new flows, new products
RTL design and Verification takes 60% of the total design time
and most of the job openings are in this area
System Verilog and UVM expertise is in demand
Low power design methodologies
DFT, Implementation and timing analysis
Physical design with PEX and DFM
Choose your projects wisely !! Know the differences between

FPGA, ASIC and Full-custom design flows.
46
Thank You
nkamath@nanochipsolutions.com
47

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Advances in the Nanometer VLSI

Nanochip Offering: RV-VLSI

Nanochip under its ECS business line in

Embedded TTP course material

up and managing finishing schools

specific advanced and on-boarding

RV-VLSI Class Rooms

RV-VLSI Design Center

RV-VLSI: Enrollment Statistics

Students from different Colleges

> 300 Colleges

Students from no. of States

18 -- (Highest AP, Second highest is

6 -- (USA, UK, Germany, Dubai,

No. of Product Companies for

Around 25 Product Companies

No. of Service Companies for

More than 42 Service Companies

It all started in 1947

Jack Kilby with his notes

FPS: State Of The Art Flows, Proven IP And Efficient

Layout of an IC just a few

Layout of a Typical IC -Today

FPS: State Of The Art Flows, Proven IP And Efficient

Yesterdays Chip Todays Block

Basic Design Flow

Arch & Circuit Design

Have these BASIC steps

Layout, checks &

Post Silicon Validation

ASIC AMS VLSI Design Flow

Physical Design (BE)

Improving one will make the other two worst do you

The Power Optimization Landscape

System architecture level

Frequency and voltage scaling

Opportunity to Influence Power

Combinational, sequential clock gating

Multi-Vdd, Multi-Vth technology mapping

Low Power Session - Verification Seminar

Low Power Design and Verification Flow

n RTL + UPF verification

Low Power Session - Verification Seminar

IEEE Std 1801-2009

Place & Route

Simulation, Power Analysis/Optimization,

n RTL is augmented with UPF

Questa PASim Native Simulation of RTL+UPF

Optimize with PA options

PD_top: {Path337} = scope /testbench/axi_dut/fpu_inst

PD_fpu: {Path343} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_post_norm_sqrt

Simulate with PA options

Low Power Session - Verification Seminar

Questa Power Aware Verification

Automatic checks and UPF/Power Aware Reports

Power Control Sequence Checks:

Isolation cells are inserted

Level shifters are inserted

Inputs do not toggle during power down

Retention registers are saved before

Latch enable is correctly set when

Primary power is on and stable during