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8, AUGUST 2013
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I. INTRODUCTION
Manuscript received November 29, 2012; revised March 28, 2013; accepted
March 28, 2013. Date of publication May 13, 2013; date of current version July
19, 2013. This paper was approved by Guest Editor Ken Suyama.
Y. Nakase, Y. Ido, and T. Kumamoto are with the Core Technology Business
Division, Renesas Electronics Corporation, Hyogo 664-0005, Japan (e-mail:
yasunobu.nakase.yg@renesas.com).
T. Oishi and Y. Shimizu are with Fundamental Technology Unit, Renesas
Design Corporation, Hyogo 664-0005, Japan.
S. Hirose and H. Onoda are with Renesas Design Corporation, Hyogo 6640005, Japan.
T. Shimizu is with Global Business Innovation and Strategy Marketing Division, 1st Solution Business Unit, Renesas Electronics Corporation, Tokyo 1000004, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2013.2258826
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the outputs for charging up. The Ton/Toff ratio needs to be determined immediately when the output changes, so feed back
control is not suitable for SIDO architecture. The other problem
of feed back control can be explained simply by using a single
output boost converter as shown in Fig. 2. The transfer function
is given by [5]
voltage
is lower than that of the triangle waveform, the clock is set low and the Ton/Toff ratio is determined
as
(1)
(2)
(3)
(4)
The Ton/Toff duty ratio is set to
in an ideal
case [11]. From (4), the desired ratio can be obtained by setting
VREF as
. There are a few problems with this scheme in
terms of practical use. For example, to obtain a precise ratio, the
capacitor needs to have linear characteristics, but such a capacitor requires a large area size or expensive additional processes
such as a polysilicon process. When is set to 0.2 and the input
voltage range is assumed to range from 0.5 V to 3 V, the value
of
varies from 0.1 V to 0.6 V. For the lower Vin, the
offset voltage of the comparator creates a larger impact.
When sensor nodes are placed outdoors, a solar cell is used
for power in order to reduce or eliminate battery maintenance
issues. In this case, a maximum power point tracking (MPPT)
control is used to extract the maximum power from a solar cell
by modulating the clock pulsewidth [12][14]. Since the output
of a solar cell is unstable, a super capacitor is used to store the
electric power generated by the solar cell [15], [16]. The super
capacitor then supplies power to the sensor node through a low
drop-out regulator (LDO) as shown in Fig. 5. In the case of a
single output converter, the output must supply the power to
both a super capacitor and its control circuits. It takes a very
long time for the control circuits to operate properly because
the output voltage rises very slowly due to the super capacitor.
The SIDO architecture also has an advantage in that one output
charges the super capacitor while the other simultaneously supplies the power to the control circuits.
A boost converter is required to start up from a single cell
voltage of 0.5 V [13]. It has been realized by using low threshold
voltage process technology [17], by supplying a clock signal
from outside [14], or by using a dedicated start-up IC [18]. Selfcontained systems do not employ these methods.
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Fig. 5. SIDO DC-DC converter for solar cell operating sensor node.
Fig. 7. Control circuits (Cntrl CKT) from Fig. 6 composed of two parts: FF
and CLK Gen.
the signals SCTY and NOP. When SCTY is at a high level, the
VCCY is selected to be charged. The NOP signal indicates that
both VCCX and VCCY have reached their expected voltages.
When NOP becomes a high level, the FF-PWM block stops.
The SIDO operation is shown in Fig. 9. For each cycle, the inductor stores a current and delivers it to either one of the outputs.
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Fig. 10. Feed-forward pulsewidth modulation (FF-PWM). OSP refers to oneshot pulse generator.
Fig. 11. Simple model for analyzing effect of parasitic resistances.
(7)
(8)
Each output is alternately charged for several cycles in continuous conduction mode (CCM). When VCCY is lower than the
expected voltage of 3 V, the SCTY is set to high as shown in
Fig. 8. The signal CLKY then becomes active. DVCCY and
VCCY are charged before VCCX, and as a result, the control
circuits (Cntrl CKT) are always stable. After VCCY reaches 3 V,
DVCCX and VCCX are selected. When both outputs of VCCX
and VCCY have reached the expected voltages, operation stops
by setting the NOP signal to high.
Fig. 10 shows the circuit configuration of the feed forward
pulsewidth modulator (FF-PWM). It consists of three parts:
a standard current generator
, a Ton period generator
, and a Toff period generator
. OSP refers to a
one-shot pulse generator. The
block generates a current
that is proportional to VBAT. At the end of the Toff period,
the
block is activated. The Ton period is determined
as the interval until the capacitor voltage reaches the reference
voltage VREF. Ton and Toff periods are given as
(5)
(6)
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Fig. 13. Control circuits for constant voltage maximum power point tracking
(MPPT).
Fig. 12. Electrical characteristics of solar cell.
current. From (9) and (10), the sustainable load current can be
calculated for a given M value.
(11)
As the M value is set larger than its ideal value of Vout/Vin,
the sustainable load current increases. However, the power loss
increases because the inductor current increases. We therefore
set the M value to 7% larger than its ideal value. The sustainable
load current of VCCX is given as follows. When the VBAT is
0.5 V, the M value is
. VCCX
can supply a load current of 3.7 mA. When VBAT is 1.5 V, the
sustainable load current increases up to 30 mA.
As shown in (11), the sustainable load current is not determined from the Ton and Toff periods themselves but rather their
ratio. Equations (7) and (8) mean that the ratio is independent of
the value of the capacitors. Therefore, capacitor linearity is not
required in this proposed control. In practice, varactors are used
as non-linear capacitors. Furthermore, a precise ratio is obtained
even at low VBAT. Since the comparator operates at the input
range around VREF (0.8 V in this case), the offset voltage has
only minimal impact compared with the conventional control.
III. OPERATION WITH SOLAR CELL
In the case of solar cell operation, an MPPT control is used instead of the feed forward control. Fig. 12 shows electrical characteristics of a solar cell. Open voltage is defined as the voltage
when no current flows and short current is defined as the current
when the voltage is zero. For each point, the power is zero. As
the Ton period increases, the solar cell current increases and its
voltage decreases. Various methods have been proposed to operate a converter at the maximum power point, most of them requiring complicated calculation algorithms. An exception is the
constant voltage or fractional open-circuit voltage method. This
method takes advantage of the fact that the maximum power
is obtained at some fixed fraction (around 80%) of the open
voltage as shown in Fig. 12. The proposed converter employs
this simple method.
Fig. 13 shows the main part of the control circuits for the
MPPT function. The VMON signal is asserted every 20 ms from
an external controller. When VMON is high, the main clock
MCLK stops and the solar cell voltage is sampled. This is an
open voltage because the converter does not drive a load. A
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(12)
considering the
We selected a four times larger CCP of 4.5
variation of transistor performance and possible different external inductor values.
A waiting time of VRNG to reach 1.2 V occupies almost all
of the start-up time. This wait time
can be expressed by
(13)
,
, and
Substituting
A, we obtain
.
Here, we develop an expression for the DVCCY rising time.
Fig. 15 shows the inductor current at start-up. The converter
operates in the DCM. Since the sub-clock SCLK oscillates at
330 KHz, the cycle time Tcyc is 3 s. An nMOS switch is turned
on during the Ton period, which is equal to a half of the Tcyc.
The inductor current reaches its peak value Ip at the end of the
Ton period and decreases to zero during the
period. Ip and
are given as
(14)
(15)
,
,
By substituting the parameters of
, and
s, we obtain the time of 20 ms
for DVCCY to reach 2.5 V.
Fig. 16 shows the circuit configuration of a charge pump and
its back gate voltage controller. The charge pump is composed
of nMOS transistors. When the VBAT is below 1.5 V, the
detector outputs at a high level. In addition, when the VBAT is
higher than 0.5 V, nMOS transistor N1 and pMOS transistors P1
and P2 are turned on. Since the voltage of VP is equal to VBAT,
VBAT is supplied to both the local oscillator and the charge
pump. Voltages VB1 and VB2 are then set as (VBAT-VF). VF
is a forward voltage drop of parasitic PN diodes between the
source and the back gate of transistors P1 and P2. Therefore, all
pMOS transistors in the local oscillator are deeply forward biased. Fig. 17 shows the relationship between the forward back
bias voltages VB2 and VBAT. When the VBAT is lower than
VF, which is around 0.7 V, the forward bias is equal to the
VBAT. In contrast, when the VBAT is higher than VF, the forward bias voltage is fixed to VF. The charge pump supplies
a current to the capacitor CCP, and the capacitor supplies the
power to the ring oscillator through VRNG by pMOS transistor
P3.
When the VBAT is in the range between 1.5 V and 3 V, the
voltages between any nodes of thin oxide transistors must be
lower than the breakdown voltage of 2 V. In this case, transistors P1 and P2 are turned off. The local oscillator and the charge
pump are isolated from the VBAT. The VBAT directly supplies the power to the ring oscillator via VRNG. The back gate
voltage VB1 is set equal to the VBAT. The back gate voltage
VB2 is equal to a half of the VBAT due to the resistors R2.
Since the transistors N1 and N3 are off and N2 is on, the gate
and source voltages of the transistor P2 are also equal to a half
of the VBAT due to the resistors R1. As a result, the voltages
between any nodes in the thin oxide transistors never exceed a
half of the VBAT.
V. IMPLEMENTATION AND EXPERIMENTAL RESULTS
We fabricated a test chip by 190 nm CMOS process technology as shown in Fig. 18. The threshold voltage is 0.7 V and
the active area size is 1.7 mm 0.44 mm.
Fig. 19 shows the measurement and simulation results of the
charge pump supply current. A current of 0.28 A was obtained
at a VBAT of 0.5 V.
Fig. 20 shows the start-up waveforms at the VBAT of 0.5 V.
The charge pump supplied a current to the capacitor CCP. When
its voltage VCP reached 1.2 V, the ring oscillator started to oscillate. The ring oscillator operation time was of the order of ten
milliseconds. This result indicates that the DVCCY is charged
up first. It takes 13 s for the outputs to reach their expected voltages of 3 V and 5 V. This rising interval is almost identical to
the calculated result. After DVCCY reached 2.5 V, the feed forward control (FF-PWM) began to operate.
Fig. 21 shows the waveforms of the feed forward control with
battery operation at a VBAT of 1.5 V. The waveform of the
terminal INDCNT shown in Fig. 6 can be considered an inverse
of the main clock MCLK. When charging VCCX or VCCY, the
amplitude of the waveform of INDCNT is equal to 5 V or 3 V,
respectively. This result shows that VCCY can be charged when
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Fig. 16. Circuit configuration of charge pump and back gate controller.
Fig. 20. Start-up waveforms at VBAT of 0.5 V. VCP refers to the voltage of
capacitor CCP.
period is small. From (5) and (6), the clock cycle time Tcyc is
given as
(19)
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Fig. 22. Comparison of Ton/Toff ratio for each output. Expected VCCX is 5 V.
Fig. 24. Experimental results of efficiency and output voltage dependence on
VCCY load current IloadY.
This indicates that the proposed feed forward control sets the
cycle time longer as the input voltage becomes lower. Therefore, the Toff period also becomes longer compared with the
conventional control.
Figs. 23 and 24 show the measured results of the efficiency
dependence of the VCCX and VCCY on load currents IloadX
and IloadY, respectively. The IloadY is kept at 4 mA (Fig. 23).
The voltage VCCX maintains within 10% of the 5 V target while
supplying 10 mA, 20 mA, and 40 mA of IloadX at VBAT of
1 V, 1.5 V, and 2 V, respectively. The IloadX is kept at 6 mA
(Fig. 24). The voltage VCCY maintains within 10% of the 3 V
target while supplying 15 mA, 40 mA, and more than 50 mA
of IloadY at VBAT of 1 V, 1.5 V, and 2 V, respectively. An
efficiency of 87% was achieved at a VBAT of 2 V and IloadY of
15 mA. The power consumption with zero load current, 0.5 mW,
was measured at the input node.
Fig. 25 shows the line transient results. The VBAT changed
from 1 V to 2 V every 800 s. The rise and fall times of the
VBAT were 17 s. The response is stable even without any compensation. There are no overshoot or undershoot phenomena
when VBAT changed.
Fig. 26 shows the measured results of charging a super capacitor from a solar cell. The solar cell had an open voltage of
1.03 V and a short current of 83 mA under an indoor light condition as shown in Fig. 12. A super capacitor of 0.4 F was attached
to a VCCX and charged from 0 V to 5 V within 80 s. The solar
Fig. 26. Experimental results of charging super capacitor with MPPT control.
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Yoshiaki Shimizu received the B.E. degree in Faculty of Engineering from Kansai University, Japan,
in 1982.
He joined Mitsubishi Electric Corp. in 1982.
He worked for research and development of SoC.
He moved to Renesas Electronics Corp., Hyogo,
Japan, in 2010. Since then, he has been working for
development of several kinds of analog IPs.