Académique Documents
Professionnel Documents
Culture Documents
1
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
1 of 2
Code No: RR210203 Set No. 1
4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]
6. (a) Draw the circuit diagram of 4-bit ring counter using D-flip flops and explain
its operation with the help of bit pattern.
(b) Draw the circuit diagram of 4-bit Johnson counter using D-flip flop and explain
its operation with the help of bit pattern. [8+8]
7. (a) Convert the following Mealy machine into a corresponding Moore machine:
PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0
8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]
⋆⋆⋆⋆⋆
2 of 2
Code No: RR210203 Set No. 2
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
2. (a) i. Obtain the simplified sum of products expression for the function
F (k, l, m, n) = klm + k mn + klm n + lmn
ii. Simplify A + AB + BC + CD
P
(b) Find
P the minimal sum of products expression for f(w,x,y,z) = (0,2,4,9,12,15)
+ φ(1,5,7,10) using Karnaughs- map [8+8]
3. Use the tabulation procedure to generate the set of prime implicants and to obtain
all the minimal
P expressions for the following
P function :
F(w,x,y,z) = m(1,5,6,12,13,14) + d(2,4) ) [16]
1 of 2
Code No: RR210203 Set No. 2
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]
PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1
8. Construct an ASM block that has 3 input variables (A,B,C), 4 output (W,X,Y,Z)
and 2 exit paths. For this block, output Z is always 1, and W is 1 if A & B are
both 1. If C=1 & A=0, Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and
exit path 2 is taken.
Realize the above using the One flip flop per state. [16]
⋆⋆⋆⋆⋆
2 of 2
Code No: RR210203 Set No. 3
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
1. (a) i. Express decimal digits 0-9 in BCD code and 2-4-2-1 code.
ii. Determine which of the above codes are self complementing.
(b) i. Convert the decimal number 96 into binary and convert it to gray code
number.
ii. Convert the given gray code number to binary: 1001001011. [8+8]
3. (a) Derive Boolean expression for a 2 input Ex-NOR gate to realize with two input
NOR gates, without using complemented variables and draw the circuit.
(b) Redraw the given circuit (figure3b) after simplification. [8+8]
Figure 3b
4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.
(b) Implement Full adder circuit using ROM and Verify the working. [8+8]
1 of 2
Code No: RR210203 Set No. 3
(b) Design a modulo-12 up synchronous counter using T-flip flops and draw the
circuit diagram. [6+10]
PS NS,Z
X-0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
⋆⋆⋆⋆⋆
2 of 2
Code No: RR210203 Set No. 4
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
1 of 3
Code No: RR210203 Set No. 4
i. f (x, y, z) = z + (x + y)(x + y)
ii. f (x, y, z) = x + (x y + xz) [3+3+4+3+3]
3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 input
NAND gates without using complemented variables and draw the circuit.
(b) Redraw the given circuit in (figure3b)after simplification. [8+8]
Figure 3b
4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]
6. Design a counter which could count either in mod 8 straight binary or in mod 8
cyclic code based on a control signal. [16]
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]
PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1
2 of 3
Code No: RR210203 Set No. 4
8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]
⋆⋆⋆⋆⋆
3 of 3