Vous êtes sur la page 1sur 9

Code No: RR210203 Set No.

1
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Give the Gray-code equivalent of the Hex number 3A7.


(b) Find the Gray-code equivalent of the octal number 527.
(c) When a block of data is stored on magnetic tape, some times parity is com-
puted on both the rows and columns. Create the row and column parity bits
for the data group shown below using odd parity.
DATA
10110
10001
10101
00010
11000
00000
11010
(d) Obtain the 3 bit and 4 bit Gray codes from the 2 bit Gray code by reflection.
[4×4]
2. For the given function P
F(A, B, C, D, E) =P (0,1, 2, 3, 4, 5, 9, 10, 16, 17, 18, 19, 20, 22, 25, 26)
+ d (7, 11, 12, 13, 15, 23, 27, 28, 29, 30)
Obtain minimal sop expression using K-Map. [16]
3. (a) Define the following terms with an example :
i. minterm
ii. maxterm
iii. canonical form of logic expression
iv. implicant
v. prime-implicant
(b) Give the following
P implementations for the given function and its complement
F(x,y,z)= m(0,6)
i. two-level NAND
ii. two-level NOR [10+6]

1 of 2
Code No: RR210203 Set No. 1
4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]

5. (a) Compare combinational Vs sequential logic circuits.


(b) Define the following terms of a flip flop
i. Hold time
ii. Set up time
iii. Propagation delay time.
(c) Draw the circuit diagram of a master slave RS flip flop and explain its opera-
tion with the help of truth table. [4+6+6]

6. (a) Draw the circuit diagram of 4-bit ring counter using D-flip flops and explain
its operation with the help of bit pattern.
(b) Draw the circuit diagram of 4-bit Johnson counter using D-flip flop and explain
its operation with the help of bit pattern. [8+8]

7. (a) Convert the following Mealy machine into a corresponding Moore machine:

PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0

(b) Design the circuit for the above table. [8+8]

8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]

⋆⋆⋆⋆⋆

2 of 2
Code No: RR210203 Set No. 2
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) A person on SATURN possessing 18 fingers has a property worth (1,00,000)18 .


He has 3 daughters and two sons. He wants to distribute half the money
equally to his sons and the remaining half to his daughters equally. How
much his each son and each daughter will get in Indian currency?
(b) An Indian started on an expedition to SATURN with Rs.1,00,000. The expen-
diture on SATURN will be in the ratio of 1:2:7 for food, clothing and traveling.
How much he will be spending on each item in the currency of SATURN.[8+8]

2. (a) i. Obtain the simplified sum of products expression for the function
F (k, l, m, n) = klm + k mn + klm n + lmn
ii. Simplify A + AB + BC + CD
P
(b) Find
P the minimal sum of products expression for f(w,x,y,z) = (0,2,4,9,12,15)
+ φ(1,5,7,10) using Karnaughs- map [8+8]

3. Use the tabulation procedure to generate the set of prime implicants and to obtain
all the minimal
P expressions for the following
P function :
F(w,x,y,z) = m(1,5,6,12,13,14) + d(2,4) ) [16]

4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.


(b) Implement Full adder circuit using ROM and Verify the working. [8+8]

5. (a) Explain the following terms in connection with a flip-flop


i. flip-flop
ii. race condition
iii. race around conductions
(b) Draw the schematic circuit of S-R Flip-Flop with negative edge triggering and
give its Truth-Table. Justify the entries in the Truth-Table. [6+10]

6. (a) Compare merits and demerits of ripple and synchronous counters.


(b) Design a modulo-12 up synchronous counter using T-flip flops and draw the
circuit diagram. [6+10]

1 of 2
Code No: RR210203 Set No. 2
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]

PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1

8. Construct an ASM block that has 3 input variables (A,B,C), 4 output (W,X,Y,Z)
and 2 exit paths. For this block, output Z is always 1, and W is 1 if A & B are
both 1. If C=1 & A=0, Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and
exit path 2 is taken.
Realize the above using the One flip flop per state. [16]

⋆⋆⋆⋆⋆

2 of 2
Code No: RR210203 Set No. 3
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) i. Express decimal digits 0-9 in BCD code and 2-4-2-1 code.
ii. Determine which of the above codes are self complementing.
(b) i. Convert the decimal number 96 into binary and convert it to gray code
number.
ii. Convert the given gray code number to binary: 1001001011. [8+8]

2. (a) Simplify the function


P using Karnaugh
Pmap method
F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

3. (a) Derive Boolean expression for a 2 input Ex-NOR gate to realize with two input
NOR gates, without using complemented variables and draw the circuit.
(b) Redraw the given circuit (figure3b) after simplification. [8+8]

Figure 3b
4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.
(b) Implement Full adder circuit using ROM and Verify the working. [8+8]

5. (a) Give the excitation tables for the following flip-flops


i. R-S flip-flop
ii. J-K flip-flop
(b) Draw the schematic circuit of J-K flip-flop and explain its operation with the
help of truth-table. How race-around conditions is eliminate in this flip-flop-
explain. [6+10]

6. (a) Compare merits and demerits of ripple and synchronous counters.

1 of 2
Code No: RR210203 Set No. 3
(b) Design a modulo-12 up synchronous counter using T-flip flops and draw the
circuit diagram. [6+10]

7. (a) Distinguish between Mealy and Moore machines


(b) Convert the following Mealy machine into a corresponding Moore machine:
[6+10]

PS NS,Z
X-0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0

8. Design a half adder and half subtractor circuit using

(a) multiplexer and registers


(b) one flipflop per state. Draw the state diagram and convert it to ASM block
and tablulate its state table. [8+8]

⋆⋆⋆⋆⋆

2 of 2
Code No: RR210203 Set No. 4
II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Consider the following four codes.


Code A Code B Code C Code D
0001 000 01011 000000
0010 001 01100 001111
0100 2 011 1 10010 3 110011 4
1000 010 10101
110
111
101
100
Which of the following properties is satisfied by each of the above codes?
i. Detects single errors
ii. Detects double errors
iii. Detects triple errors
iv. Corrects single errors
v. Corrects double errors
Corrects singe and detects double errors.
(b) Add the following decimal number 109 and 876 in BCD and Excess-3 forms.
[8+8]
2. (a) Each of the following functions actually represents a set of four functions
corresponding Pto the various assignments
P of the don?t care terms.
f1 (w,x,y,z) = P(1,3,4,5,9,10, 11) P
+ φ(6,8)
f2 (w,x,y,z) = (0,2,4,7,8,15) + φ (9,12)
then
i. Find such that f3 = f1 .f2
ii. Find such that f4 = f1 + f2
iii. Simplify and obtain minimal sop for f3 and f4 .
(b) Determine the canonical sum-of-products representation of the below func-
tions.

1 of 3
Code No: RR210203 Set No. 4
i. f (x, y, z) = z + (x + y)(x + y)
ii. f (x, y, z) = x + (x y + xz) [3+3+4+3+3]

3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 input
NAND gates without using complemented variables and draw the circuit.
(b) Redraw the given circuit in (figure3b)after simplification. [8+8]

Figure 3b
4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]

5. (a) Explain the following terms in connection with a flip-flop


i. preset
ii. clear
iii. race conditions
iv. race-around condition
(b) Draw the schematic circuit of Toggle-flip-flop (T) Give its truth-table. Justify
the entries in the truth-table. (NAND gates only) [8+8]

6. Design a counter which could count either in mod 8 straight binary or in mod 8
cyclic code based on a control signal. [16]

7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]

PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1

2 of 3
Code No: RR210203 Set No. 4
8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]

⋆⋆⋆⋆⋆

3 of 3

Vous aimerez peut-être aussi