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CSC

Unit 1:
1. Addressing Mode
2. Instruction and instruction sequencing
3. Performance and metrics
4. Functional units
5. All algorithm with example
Booth
Restoring and non-restoring
Unit 2:
1.
2.
3.
4.

Hardwired control
Micro programmed control
Multiple bus organization
Execution of complete instruction

Unit 3:
1. data hazard & instruction hazard
2. superscalar operation
Unit 4:
1. cache memory
2. virtual memory
3. secondary memory
Unit 5:
1. standard I/O interface (PCI,SCSI,USB)
2. interface circuits
3. Direct Memory access (DMA

EC2303

Computer Architecture and Organization Important Questions EC2303 EC


2303 subject for NOV/DEC 2011 ANNA UNIVERSITY EXAMINATIONS FOR
III YEAR ECE STUDENTS
UNIT I
1. Define addressing mode. Classify addressing modes and explain each type with
example
2. Explain the architecture of basic computer with neat diagram.

3. Design a combination circuit whose input is a 4-bit number and whose output is a
twos compliment of the input number.
UNIT II
1. Describe in detail booth's multiplication algorithms and its hardware
implementation.
2. With suitable diagram explain how multiplication can be performed using a
multistage carry-save adder circuit and also implementation of a pipelined carry-save
multiplier.
3. Draw non-restoring division algorithm for unsigned integer with suitable example.
UNIT III
1.Describe various factors that reduce the performance of pipelined CPU and
mechanism to overcome it?
2. What are superscalar processors? Explain the typical structure of a typical
superscalar processor?
3 . Describe the organization of a typical micro-programmed control unit with the
help of a neat diagram.
UNIT IV
1.
2.
3.
4.

Draw the neat sketch of memory hierarchy and explain the need of cache memory
Explain the organization of magnetic disk in detail.
Explain optical memories in detail.
Explain the organization of Random access memories
UNIT V

1. Explain the Programmed I/O and DMA mode of data transfer.


2. Define Interrupt. Explain it types in detail
3. Explain the DMA mode of data transfer.

EC2303 Computer Architecture and Organization: Question Bank

QUESTION BANK
UNIT-I
INTRODUCTION
2 Marks
1. Discuss the stored program concept.What are its advantages and
disadvantages?
2. Why data bus is bidirectional and address bus is unidirectional in
most microprocessors? (MAY/JUNE 2007)
3. What is a bus? What are the different buses in a CPU? ( NOV/DEC
2006)
4. Define 3-address,2-address,1-address,0 -address instruction with an
example. (MAY/JUNE 2006)
5. What is the information conveyed by addressing modes? (NOV/DEC
2007)
6. Registers R1 and R2 of a computer contain the decimal values 1200
and 4600. What
is the effective address of the memory operand in each of the following
instructions?
(a) Load 20(R1), R5
(b) Add - (R2), R5 (APRIL/MAY 2008)
7. What is the use of condition code register? (APRIL/MAY 2008)
8. Distinguish between auto increment and auto decrement addressing
mode. (APRIL/MAY 2010)
9. What is meant by ENIAC & EDVAC?
10. Write the general format for the Fixed point & floating numbers .
11. Define addressing mode.
12. What is a bus? What are the different buses in a CPU?
13. Define underflow and overflow.

8 or 16 Marks
1. Describe the different classes of instruction format with example.
2. Describe Von Neumann Architecture (IAS Computer) in detail.
3. Explain in detail about the first generation of computer.
4. Explain the different types of Addressing modes with suitable
examples. (APRIL/MAY 2008)
Explain various instruction formats in detail. (APRIL/MAY 2008) &
(MAY/JUNE 2006)
5. Explain about Addressing modes? (NOV/DEC 2007) & ( NOV/DEC
2006) & (MAY/JUNE 2007)
6. Registers R1 and R2 of a computer contains the decimal values 1200
and 2400respectively. What is the effective address of the memory
operand in each of the following instructions?
i. Load 20(R1), R5
ii. Add (R2) , R5
iii. Move #3000, R5

iv. Sub (R1)+, R5


7. With a neat block diagram explain in detail about typical CPU.
8. With a a neat block diagram explain the Accumulator based CPU.
9. What are the different ways system can be designed? Explain in
detail
10. Write notes on Instruction formats. (NOV/DEC 2007) & ( NOV/DEC
2006)
11.Explain about Instruction & Instruction Sequencing? ( NOV/DEC
2006)

UNIT II
DATAPATH DESIGN
2 Marks
1.Draw the full adder circuit (NOV/DEC 2007)
2.Define Spatial expansion. (APRIL/MAY 2008)
3.Define Temporal expansion. (APRIL/MAY 2008)
4.Define underflow and overflow. (APRIL/MAY 2008)
5.What are the disadvantages in using a ripple carry adder? (NOV/DEC
2006)
6.What is pipelining and what are the advantages of pipelining?
7.What is carry look ahead adder?
8.What is an ALU expansion? List out its types.
9.What is ripple-carry adder?
10.what is coprocessor?
11.What is modified Booth algorithm?

8 or 16 Marks
1. Illustrate Booth Algorithm with an example.
2. Design a 4-bit Carry-Look ahead Adder and explain its operation with
an example. (APRIL/MAY 2008) & (NOV/DEC 2007)
3. Draw the diagram of a carry look ahead adder and explain the carry
look ahead
adder principle. (NOV/DEC 2006)
4. Design a 4-bit binary adder/ subtractor and explain its functions.
(APRIL/MAY 2008)
5. Give the algorithm for multiplication of signed 2s complement
numbers and
illustrate with an example. (APRIL/MAY 2008)
6. Write the algorithm for division of floating point numbers and illustrate
with an
example. (APRIL/MAY 2008)
7. Explain the working of a floating point adder/ subtractor.Explain how
floating point
additional/ subtraction is performed. (MAY/JUNE 2006) & (NOV/DEC 2006)
8. Give the IEEE standard double precision floating point format.
(NOV/DEC 2006)

9. Explain the representation of floating point numbers in detail.(MAY/JUNE


2007)
10. Design a 4-stage instruction pipeline and show how its performance
is improved
over sequential execution.
11. Explain Booth multiplication (2s complement)algorithm and using
this
algorithm perform the multiplication on the following 6-bit unsigned
integer
110011 * 101100.
12. Explain Robertson algorithm and using this algorithm perform the
multiplication on
the following 6-bit unsigned integer 10101010 * 11001110
13. Using Booth algorithm perform the multiplication on the following 6bit unsigned
integer 10110011 * 11010101
14. Using Robertson algorithm perform the multiplication on the
following 6-bit
unsigned integer 10110011 * 11010101
15. Explain non restoring division algorithm and using this algorithm
perform the
division on the following 5-bit unsigned integer 1111 / 0011.
16. With a neat block diagram explain in detail about Combinational,
sequential
ALU and the expansion of ALU.
17. With a neat block diagram explain in detail about the coprocessor.
18. Explain modified Booth algorithm with an example.

UNIT-III
CONTROL DESIGN
2 Marks
1. What are the advantages and disadvantages of hard wired and
micro programmed
control? (NOV/DEC 2007)
2. What is microprogram? (NOV/DEC 2009)
3. State the difference between hardwired control and micro
programmed control
unit. (MAY/JUNE 2007)
4. What is hardwired control?
5. What is micro programmed control?
6. Define Control word (CW) & Control store.
7. Draw the structure of hard wired control unit.
8. Draw the structure of micro programmed control unit.
9. How do we measure the performance of a computer?
10. What is meant by Nano programming?
11. What is the work of Nano control memory?

8 or 16 Marks
1. Explain the Organization of Hardwired control in detail. (NOV/DEC
2006)
2. Explain the Organization of Micro programmed control unit in detail.
(NOV/DEC 2007) & (MAY/JUNE 2006) & ( NOV/DEC 2006)
3. List the differences between hardwired control and micro
programmed control?
(APRIL/MAY 2008)
4. Explain Microprogrammed Control Unit. What are the advantages
and
disadvantages of it? (APRIL/MAY 2008)
5. Explain about Superscalar Operation.
6. Explain the performance of pipelining.
7. Write short notes on Nanoprogramming.
8. Explain about Multiplier control unit.
9. Explain about cpu control unit.

UNIT-IV
MEMORY SYSTEM
2 Marks
1. Give the features of a ROM cell (APRIL/MAY 2008)
2. List the differences between static RAM and dynamic RAM.
(APRIL/MAY 2008)
3. Define Locality of Reference. (NOV/DEC 2009)&(APRIL/ MAY 2008)
4. What is Translation Look aside Buffer? (MAY/JUNE 2006)
5. Define memory access time.
6. Define memory cycle time.
7. Define data transfer rate.
8. Define Cache memory.
9. Define Virtual Memory.
10. What are the advantages of SRAM?
11. Define Asynchronous DRAMS.
12. Define Synchronous DRAMS.
13. Define Memory latency & memory bandwidth.
14. What is Read only memory (ROM)?
15. What is Random Access Memory (RAM)?
16. What is PROM?
17. What is EPROM?
18. What is EEPROM?
19. Draw the structure of Memory hierarchy.
20. What is replacement algorithm?
21. What is write-through protocol?
22. What is write-back (or) copy-back protocol?
23. What is mapping & when do you apply the mapping techniques?
24. What is hit rate & miss rate?

8 or 16 Marks
1. Describe the organization of a typical RAM chip. (MAY/JUNE 2007)
2. Explain about Static & Dynamic memory systems. (NOV/DEC 2007)
3. Write note on:
i. ROM technologies.
ii. Set associative mapping of cache.
4. Explain about Cache memory in detail. (NOV/DEC 2006)
5. What is mapping? Explain its types in detail. (MAY/JUNE 2006)
6. Explain various mechanisms of mapping main memory address into
cache
memory addresses. (APRIL/MAY 2008)
7. Explain the performance factors in memory. (MAY/JUNE 2006)
8. Explain the concept of memory hierarchy(NOV/DEC
2007)&( NOV/DEC 2006)
9. Explain how the virtual address is converted into real address in a
paged virtual
memory system. (APRIL/MAY 2008)
10. Discuss the address translation mechanism and the different page
replacement
policies used in a virtual memory system. (MAY/JUNE 2006)
11. Describe the working principle of a typical magnetic disk.
(APRIL/MAY 2008)
12. Define Cache Mapping Functions. Explain the methods.
13. How a virtual address gets translated into a physical address?
Explain in detail
with a neat diagram. Explain the use of TLB.
(APRIL/MAY 2008)&( NOV/DEC 2006) & (MAY/JUNE 2007)
14. What is virtual memory? How is it implemented? (NOV/DEC 2007)
15. Discuss the various memory types and mention their advantages
(NOV/DEC 2009)
16. Explain the operation of Associative cache memories. (NOV/DEC
2009)
17. Explain virtual memory concept in detail.

UNIT-V
SYSTEM ORGANIZATION
PART-A
1. What is a bus? What are the different buses in a CPU? ( NOV/DEC
2006)
2. Why are interrupt masks provided in any processor? (MAY/JUNE
2006)
3. What is priority interrupt? (APRIL/MAY 2008)
4. What are advantages of using interrupt initiated data transfer over
transfer under
program control without interrupt? (MAY/JUNE 2007)

5. What is the difference between subroutine and interrupt services


routine?
(NOV/DEC 2007)
6. What is Direct Memory Access (DMA)? And state its advantages.
7. 7. Why do we need DMA? (NOV/DEC 2007)
8. Why does DMA have priority over the CPU when both request a
memory
transfer? (MAY/JUNE 2007)
9. How does bus arbitration typically work? (MAY/JUNE 2006)
10. What is the necessity of an interface? (NOV/DEC 2006)
11. Compare CISC v/s RISC
12. What is an operating system? What is necessity of operating
system?
13. What do you mean by fault tolerance?
14. What do you mean by static redundancy?
15. What do you mean by dynamic redundancy?
16. What is n-modular redundancy?
17. Give the difference between static and dynamic redundancies.
18. State any four ways to measure fault tolerance.
19. What is MTTF?
20. What is MTTR?

PART-B
1. Design parallel priority interrupt hardware for a system with eight
interrupt
source. (MAY/JUNE 2007)
2. Explain how DMA transfer is accomplished with a neat diagram.
( NOV/DEC 2006)
3. Draw the typical block diagram of a DMA controller and explain how
it is used
for direct data transfer between memory and peripherals.
(APRIL/MAY 2008) & (MAY/JUNE 2007)
4. Explain the use of vectored interrupts in processors. Why is priority
handling
desired in interrupt controllers? How do the different priority schemes
work?
5. (MAY/JUNE 2006)
6. Write short notes on:
7. DMA.
8. Bus Arbitration (NOV/DEC 2007)
9. Explain different mechanisms used for bus arbitration.
10. Write short notes on IOP.
11. Discuss various techniques used for fault tolerance.
12. What are the different ways in which redundancy can be made use
of provide
fault tolerance?

13. Write short notes on Programmed I/O.