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I.
processor-independent;
INTRODUCTION
SOC ARCHITECTURE
337
IV.
Figure 1: Block diagram of proposed SoC architecture
CPU INTERFACE
PALMBUS CONTROLLER
338
VI.
V.
339
VIII. CONCLUSION
This paper presents the idea behind the architecture of a
low-power, processor-independent and reusable SoC platform.
It describes the overall structure of this SoC, describes how
processor independence and reusability is achieved and
presents the block level diagrams of each module in the chip.
Each module of the chip is designed keeping reusability in
mind so any module can be easily removed from this SoC or
additional modules can be added with minimum effort. The
modules which are implemented in the platform support
different modes of operation, and these various modes are
configurable through programmable registers, thus providing
another level of reusability at the module level.
Implementation of this whole SoC platform on FPGA took
only 0.4084 Million gates. Hence a lot of resources are
available for building future projects using it as a base.
340
[4]
ACKNOWLEDGMENT
This research was supported by National ICT R&D. This
particular platform will be licensable under the National ICT
R&D open source policy.
REFERENCES
[1]
[2]
[3]
341
Kwanghyun Cho, Jaebeom Kim, Euibong Jung, Sik Kim, Zhenmin Li,
Young-Rae Cho, Byeong Min, Kyu-Myung Choi, Reusable Platform
Design Methodology For SoC Integration And Verification, 2008
International SoC Design Conference.
[5] Bill Cordan, An Efficient Bus Architecture for System-On-Chip
Design, IEEE 1999 Custom Integrated Circuits Conference
[6] Palmchip Corp. CoreFrame II Bus Specification
[7] Atmel
Corporation. AT91 ARM
Thumb Microcontrollers
AT91SAM9XE128 AT91SAM9XE256 AT91SAM9XE512 Datasheet.
[Online]
Available:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=605
[8] NXP Semiconductors. I2C bus specification and user manual. [Online]
Available: http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf
[9] Texas Instruments. Asynchronous Communications Element with
Autoflow
Control
(Rev.
E).
[Online]
Available:
http://focus.ti.com/docs/prod/folders/print/tl16c550d.html
[10] Freescale Semiconductor. Serial Peripheral Interface (SPIV3) Block
Description.
[Online]
Available:
http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12SPI
V3.pdf
[11] Xilinx Inc. Spartan 3 FPGA Family Datasheet. [Online] Available:
http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf