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ComputerArchitecture

Computerarchitectureinvolvesthedesignofcomputers.
Processordesigninvolvestheinstructionsetdesignandtheorganisationoftheprocessor.
Instructionsetarchitecture(ISA)describestheprocessorintermsofwhattheassembly
languageprogrammersees,i.e.theinstructionsandregisters.
Organisationisconcernedwiththeinternaldesignoftheprocessor,thedesignofthebus
systemanditsinterfaces,thedesignofmemoryandsoon.Twomachinesmayhavethesame
ISA,butdifferentorganisations.
The organisation is implemented in hardware and in turn, two machines with the same
organisationmayhavedifferenthardwareimplementations,forexample,afasterformof
silicontechnologymaybeusedinthefabricationoftheprocessor.
Introduction
Thefirstpointthatmustbemadeaboutcomputerarchitectureisthatthereisnostandard
computer architecture, in the same way as there is no such thing as a standard house
architectureorstandardmotorcardesign
However,justasallcarshavesomebasicfeaturesincommon,sotoodocomputers.Inthis
section, we take a high level look at the components of computer architecture that are
commontoallcomputers,notingthatanyparticularcomputerwilldifferinvariousdetails
fromthegeneralmodelpresented.
Aswehaveseenearlier,computerprogramsaretranslatedtomachinecodeforexecutionby
theCPU.Onceaprogramhasbeenloadedintothecomputersmemory(carriedoutbythe
operatingsystemonourbehalf),theprogrammaythenbeexecuted.
ThismeansthattheCPUobeystheinstructionsmakinguptheprogramandcarriesthemout
oneatatime.
It is worth noting, at this point, theprimitivenature of the CPU. The CPU does
notunderstandprograms,ratheritobeysindividualinstructions.
6.2InstructionSet
Oneofthecrucialfeaturesofanyprocessorisitsinstructionset,i.e.thesetofmachinecode
instructionsthattheprocessorcancarryout.Eachprocessorhasitsownuniqueinstruction
setspecificallydesignedtomakebestuseofthecapabilitiesofthatprocessor.Theactual
numberofinstructionsprovidedrangesfromafewdozenforasimple8bitmicroprocessorto
severalhundredfora32bitVAXprocessor.However,itshouldbepointedoutthatalarge
instructionsetdoesnotnecessarilyimplyamorepowerfulprocessor.

Many modern processor designs are so calledRISC(Reduced Instruction Set Computer)


designswhichuserelativelysmallinstructionsets,incontrasttosocalledCISC(Complex
InstructionSetComputer)designssuchastheVAXandmachinesbasedontheIntel8086
andMotorola68000microprocessorfamilies.
ClassificationofInstructions
Theactualinstructionsprovidedbyanyprocessorcanbebroadlyclassifiedintothefollowing
groups:
Datamovementinstructions:Theseallowtheprocessormovedatabetweenregistersand
between memory and registers (e.g. 8086mov,push,popinstructions). A move
instructionanditsvariantsisamongthemostfrequentlyusedinstructionsinaninstruction
set.
Transfer of controlinstructions: These are concerned with branching for loops and
conditional control structures as well as for handling subprograms (e.g.
8086je,jg,jmp,call,retinstructions).Thesearealsocommonlyusedinstructions.
Arithmetic/logicalinstructions:Thesecarryouttheusualarithmeticandlogicaloperations
(e.g. 8086cmp,add,sub,inc,and,or,xorinstructions). Surprisingly, these are not
frequentlyusedinstructions,andwhenused,itisofteninconjunctionwithaconditionaljump
instruction rather than for general arithmetic purposes. Note that we have included
thecmpinstructionwiththearithmetic/logicalinstructionsbecauseitactuallybehaveslike
asubinstructionexceptitdoesnotmodifyitsdestinationregister.
Input/outputinstructions: These are used for carrying out I/O (e.g.
8086in,outinstructions)butaverycommonformofI/OcalledmemorymappedI/Ouses
moveinstructionsforI/O.
Miscellaneousinstructions (e.g. 8086int,sti,cti, hlt, nop) for handling
interruptsandsuchactivities.Thehltinstructionhaltstheprocessorandthenopinstruction
doesnothingatall!Theseinstructions areagainnotthatfrequently usedrelativetodata
movementandtransferofcontrolinstructions.Theintinstructioncouldalsobeclassifiedas
atransferofcontrolinstructionandinterruptsaredescribedinmoredetailbelow.
This is not the only way to classify instructions. For example, the arithmetic/logical
instructionsmentionedabovemaybeclassifiedasoperateinstructions.Operateinstructions
alsoincludeinstructionsthatmovedatabetweenregistersandmanipulatestacks.Memory
accessinstructionsrefertothosethattransferdatabetweenregistersandmemory.
FixedandVariablelengthInstructions
Instructions are translated to machine code. In some architectures all machine code
instructionsarethesamelengthi.e.fixedlength.Inotherarchitectures,differentinstructions
maybetranslatedintovariablelengthsinmachinecode.

Thisisthesituationwith8086instructionswhichrangefromonebytetoamaximumof6
bytesinlength.Suchinstructionsarecalledvariablelengthinstructionsandarecommonly
usedonCISCmachines.
Theadvantageofusingsuchinstructions,isthateachinstructioncanuseexactlytheamount
ofspaceitrequires,sothatvariablelengthinstructionsreducetheamountofmemoryspace
requiredforaprogram.
On the other hand, it is possible to havefixed lengthinstructions, where as the name
suggests,eachinstructionhasthesamelength.Fixedlengthinstructionsarecommonlyused
withRISCprocessorssuchasthePowerPCandAlphaprocessors.
Sinceeachinstructionoccupiesthesameamountofspace,everyinstructionmustbelong
enough to specify a memory operand, even if the instruction does not use one. Hence,
memory space is wasted by this form of instruction. The advantage of fixed length
instructions,itisargued,isthattheymakethejoboffetchinganddecodinginstructions
easier and more efficient, which means that they can be executed in less time than the
correspondingvariablelengthinstructions.
Thus the comparison between fixed and variable length instructions comes down to
theclassiccomputingtradeoffofmemoryusageversusexecutiontime.
In general, computer programs that execute very quickly tend to use larger amounts of
storage,whileprogramstocarryoutthesametasks,thatdonotusesomuchstorage,tendto
takelongertoexecute.
FetchExecuteCycle
Thisisthefundamentaloperationoftheprocessor.TheCPUexecutestheinstructionsthatit
finds in the computers memory. In order to execute an instruction, the CPU must
firstfetch(transfer)theinstructionfrommemoryintooneofitsregisters.
Thisisanontrivialtaskrequiringseveralstepsandisdescribedlater.
TheCPUthendecodestheinstruction,i.e.itdecideswhichinstructionhasbeenfetchedand
finallyitexecutes(carriesout)theinstruction.
TheCPUthenrepeatsthisprocedure,i.e.itfetchesaninstruction,decodesandexecutesit.
Thisprocessisrepeatedcontinuouslyandisknownasthefetchexecutecycle.
ThiscyclebeginswhentheprocessorisswitchedonandcontinuesuntiltheCPUishalted
(viaahaltinstruction,e.g.8086hltinstructionorthemachineisswitchedoff).
Insteadoflookingatthedetailsofaparticularmicroprocessor'sarchitectureatthispoint,we
will useasimple hypothetical microprocessor toexplain the basicconcepts ofcomputer
architecture.

WecallthemachineSAM(SimpleArchitecture Machine).Figure1illustrates themajor


componentsofSAM.Itisa16bitmicroprocessorwith4generalpurposeregistersr0tor3,
aprogramcounterregisterPC,astackpointerregisterSPandstatusregisterSR.Thestatus
registerismadeupofsimilarflagstothe8086flagsregister,e.g.azeroflag,anoverflow
flag,acarryflagandsoon.
The fetchexecute cycle operates by first fetching an instruction. The program counter
registerPCalwayscontainstheaddressofthenextinstructiontobeexecuted.
Letusassumethataparticularprogramhasbeenloadedintomemoryandiscurrentlybeing
executed. Program execution has reached a certain point (themoveinstruction is being
executed)andthethreeinstructionsoftheprogramarelistedinExample1.
To illustrate how the fetch execute cycle operates, we will trace the execution of these
instructions.
Weassumethattheseinstructionsarestoredinmemorybeginningatlocation3000H.
Theinstructionsandtheirmachinecodeequivalents(inhexadecimal)arelistedbelow.
We use hexadecimal instead of binary as it is easier to work with but you must
rememberthat it is the binary form of the instructions that are actually stored in
memory.

Example1:ThefollowingisaSALprogramfragmentanditsmachinecodeversion.Italso
showstheaddressesofwheretheinstructionsarestoredinmemory.
Thememoryvariablexisstoredatlocation0100Hinmemorywhichcontainsthevalue6.

ThelabelNextis16(10H)bytesforwardfromthejeinstruction.
SALCodeSAMCodeMemoryAddress
HexDecimal
mover0,60180H3000H4096
0006H3002H4098
loadr1,x0284H3004H4100
0100H3006H4102
cmpr0,r10F01H3008H4104
jeNext2F10H300AH4106
.....300CH4108
.....
This code fragment assigns registerr0the value6, assigns registerr1the value
ofx(also6)andcomparesthevaluesofregistersr0andr1.
Iftheregistersareequal,whichtheyareinthiscase,controltransferstotheinstructionstored
atNextnotshowninthisexample.
The fetchexecute cycle operates by first fetching an instruction. The program counter
registerPCalwayscontainstheaddressofthenextinstructiontobeexecuted.
Forthecodefragmentunderconsideration,themoveinstructioniscurrentlybeingexecuted.
Thus, the program counter contains the value3004Hat the point where we begin tracing
execution of the program i.e. the address of the next instruction, in this case
theloadinstruction.
Havingexecutedthemoveinstruction,theloadinstructionisfetched.,
Afterfetchingtheloadinstruction,thecontrolunitupdatestheprogramcountertopointto
thenextinstructiontobefetched.Thecontrolunitincrementstheprogramcounterbythesize
of the current instruction, in this case thePCregister is incremented by4, giving it the
value3008H.
Theprogramcounternowpointstothecmpinstruction.
TheMDRregister(seelater)containstheinstructionjustfetchedfrommemoryandthisis
transferredtotheinstructionregister,IR.

The instruction register is another of the CPU's hidden registers which we have not
encounteredtodate.Itislogicallypartofthecontrolunitanditsfunctionistostorean
instructionsothatitcanbedecodedforexecution.
Theloadinstructionisnowexecutedandthefetchexecutecyclebeginsagain.

Figure 1 illustrates the state of the SAM registersafterthemoveinstruction has been


fetched.Onlytherelevantportionsofmemoryareshown.
Weassumethatthegeneralpurposeregistershavethevalue0exceptforr2whichhasthe
value1.TheSPregisterisshowntohave"?"asitsvaluetoindicatethatwearenotinterested
initscontents,inthisexample.Thestatusregister,SR,hasvalue0,indicatingthattheflags
areallsetto0.
Note: We show memory to contain text for illustrative purposes. memory willalways
contain binaryand in this example, it will contain the machine code of the given
instructions.
AccessingMemory
In order to execute programs, a microprocessor fetches instructions from memory and
executesthem,fetchingdatafrommemoryifitisrequired.
In Figure 1 we introduced two registers that we have not mentioned before namely
thememoryaddressregister,MARandthememorydataregister,MDR.Thereareanumber
ofsuchCPUregistersthatdonotappearintheprogrammingmodelofaCPU.Weshall
refertotheseregistersashiddenCPUregisterstodistinguishthemfromtheprogramming
modelregistersR0toR4,PC,SRandSPregisters.
TheMARandMDRregisters are used to communicate with memory (and other devices
attachedtothesystembus).
Inaddition,Figure1showsthebusesthatallowthedevicesmakingupaSAMcomputer
systemcommunicatewitheachother.
TheMARregisterisusedtostoretheaddressofthelocationinmemorythatistobeaccessed
forreadingorwriting.
When we retrieve information from memory we refer to the process asreadingfrom
memory.
Whenwestoreaniteminmemory,werefertotheprocessaswritingtomemory.
Ineithercase,beforewecanaccessmemory,wemustspecifythelocationwewishtoaccess,
i.e.theaddressofthelocationinmemory.ThisaddressmustbestoredintheMARregister.

TheMARregisterisconnectedtomemoryviatheaddressbuswhosefunctionistotransfer
theaddressintheMARregistertomemory.Inthiswaythememoryunitisinformedasto
whichlocationistobeaccessed.
Theaddressbusisaunidirectionalbus,i.e.informationcanonlytravelalongitinasingle
direction,fromtheCPUtomemoryandotherdevices.
TheMARregisterisa16bitregisterlikealltheotherSAMregisters.Thismeansthatthe
maximumaddressitcancontainis2161(65,535)bytes,i.e.itcanaddressupto64Kbof
memory.
TheMDRregisterisusedeithertostoreinformationthatistobewrittentomemoryortostore
informationthathasbeenreadfrommemory.TheMDRregisterisconnectedtomemoryvia
thedatabuswhosefunctionistotransferinformation,toorfrommemoryandotherdevices.
Thedatabusisabidirectionalbus,i.e.informationcantravelalongit,both,toandfrom
theCPU.
ThecontrolbusplaysacrucialroleinI/O.Itcarriescontrolsignalsspecifyingwhatoperation
istobecarriedoutandtosynchronisethetransferofinformation.
Forexample,onelineofthecontrolbusistheread/write(R/W)linewhichusedtospecify
whetherareadorwriteoperationistobecarriedout.
Anotherlineisthevalidmemoryaddress(VMA)linewhichindicatesthattheaddressbus
nowcarriesavalidmemoryaddress.Thistellsthememoryunitwhentolookattheaddress
bustofindtheaddressofthelocationtobeaccessed.Athirdlineisthememoryoperation
complete(MOC)linewhichsignalsthattheread/writeoperationhasnowcompleted.We
shouldnoteatthispoint,thattheotherdevicesattachedtothecomputer,suchasI/Oand
storagedevices,usuallycommunicatewiththeCPUinasimilarfashiontothatdescribedfor
communicatingwithmemory
ReadingfromMemory
The following steps are carried out by the SAM microprocessor to read an item from
memory.Theitemmaybeaninstructionoradataoperand.
1.TheaddressoftheiteminmemoryisstoredintheMARregister.
2.Thisaddressistransferredtotheaddressbus.
3.TheVMAlineandR/Wlineofthecontrolbusareusedtoindicateto
memory that there is a valid address on the address bus and that
areadoperationistobecarriedout.
4.Memoryrespondsbyplacingthecontentsofthedesiredaddressonthedatabus.

5.MemoryenablestheMOClinetoindicatethatthememoryoperationis
complete,i.e.thedatabuscontainstherequireddata.
6.TheinformationonthedatabusistransferredtotheMDRregister.
7.TheinformationistransferredfromtheMDRregistertothespecifiedCPUregister.
WritingtoMemory
Thisprocedureissimilartothatforreadingfrommemory:
1.TheaddressoftheiteminmemoryisstoredintheMARregister.
2.Thisaddressistransferredtotheaddressbus.
3.TheitemtobewrittentomemoryistransferredtotheMDRregister.
4.Thisinformationistransferredtothedatabus.
5.TheVMAlineandR/Wlineofthecontrolbusareusedtoindicateto
memory that there is a valid address on the address bus and that
awriteoperationistobecarriedout.
6.Memoryrespondsbyplacingthecontentsofthedatabusinthedesiredmemorylocation.
7. Memory uses the MOC line to indicate that the memory operation is
complete,i.e.thedatahasbeenwrittentomemory.

We can see from the above descriptions (which have been simplified!) that accessing
memoryoranydeviceisquitecomplicatedfromanimplementationviewpoint.So,whenan
instructionsuchas
loadr1,i
toloadaregisterwiththecontentsofamemoryvariableistobeexecuted,alotofworkhas
tobecarriedout.
FirstlytheinstructionmustbefetchedfromRAM,thenthevalueofimustbefetchedfrom
RAMandfinallythetransferofthevalueofitoregisterr1iscarriedout.
Itisimportanttorealisethateveryoperationconcerningmemoryinvolveseitherreadingor
writingmemory.
Memoryisapassivedevice.Itcanonlystoreinformation.Noprocessingcanbecarriedout
oninformationinmemory.Theinformation,storedinmemory,mustbetransferredtoaCPU
registerforprocessingandtheresultwrittenbacktomemory.

So, for example, when an instruction such as the 8086incinstruction is carried out to
incrementamemoryvariable(asinincmemvar),itsexecutioninvolvesbothamemory
readoperationandamemorywriteoperation.
Firstly,thevalueofmemvarmustbetransferredtotheCPUwhereitcanbeincrementedby
theALU.Thistransferiscarriedoutviaamemoryreadoperation.Then,oncethisvaluehas
beenincrementedbytheALU,thenewvalueofmemvarmustbewrittenouttomemvar's
addressinmemory,viaamemorywriteoperation.
EncodingInstructionsinMachineCode
Instructionsarerepresentedinmachinecodeasbinarynumbersinsamewayasallother
informationisrepresentedinacomputersystem.Wenotedearlierthatassemblylanguage
instructionsformostprocessorsarebroadlysimilarandhavetheform:
[label]operation[operand..][;comment]
ThegeneralformofamachinecodeinstructionisillustratedinFigure2withthebitsmaking
uptheinstructionbeinggroupedintoopcodeandoperandfields.

Figure2:Machinecodeinstructionformat
Theopcodefieldcontainsabinarycodethatspecifiestheoperationtobecarriedout(e.g.
add, jmp ). Each operation has its own unique opcode. The operand field specifies the
operandoroperandsthattheoperationistobecarriedouton..
ItshouldbeemphasisedthattheinstructionencodingforSAMisdesignedforillustration
purposes.Theaimistokeepitassimpleaspossiblewhileremainingbasicallysimilartothe
encodingofinstructionsonrealprocessors.Thereaderisencouragedtolookatwaysthe
instructionscouldbemoreefficientlyencoded.
Table1liststheopcodesofthecommonlyusedSAMinstructionsinbinaryandhexadecimal.
Instruction
BinaryCode
Hex
Code
move

00000001

01

load

00000010

02

store

00000011

03

add

00001000

08

sub

00001001

09

cmp

00001111

0F

jmp

00011111

1F

je

00101111

2F

Table1:SAMopcodes
Theoperandfieldofaninstructionmustbeabletospecifytheregisters,memoryaddressesor
constantsthattheinstructionistooperateon.SAMinstructionshaveatmosttwooperands.If
therearetwooperandsthenoneisalwaysaregister.
Ifamemoryaddressisspecified(e.g.inthecaseofamemoryvariableorlabel)thenthe
instructionisencodedusing32bits.
SinceSAMhasfourgeneralpurposeregisterswecanrepresentthemusing2bitcodesas
follows:
00forr0
01forr1
10forr2
11forr3.
Thus,4bitsarerequiredtorepresentthetworegistersthatmaybeusedinaninstruction.Bit
numbers0and1, represent the source register and bit numbers2and3represent the
destinationregister.
Example:Encoding ofload r1, XwhereXrefers to a memory variable stored at
location00FFH(255D)inmemory,
InstructionandbinaryencodingHexencoding
(1)
loadr1,X;r1=X
00000010100001000000000011111111028400ffH
(addressofval)

Bfield>Wfield
Explanation
Thisinstructionisencodedusing32bits.Theopcodeforloadis00000010(02H),the
destinationregisterr1isencodedas01,whilethesourceregisterisencodedas00,butis
notusedbecausetheloadinstructionlooksforitssourceoperandinmemory,hencebit7of
theBfieldissetto1,indicatingamemoryoperand.Finally,theaddressofthememory
variableX(00ffH)isstoredintheWfield.