VALLIAMMAI ENGINEERING COLLEGE Department of Information Technology

CS6303 COMPUTER ARCHITECTURE Question Bank

Year :II year (2014-15) ODD SEMESTER

UNIT-1 OVERVIEW AND INSTRUCTIONS

PART- A
1. What are the eight great ideas in computer architecture?
2. What are the five classic components of a computer?
3. What is the function of data path and control path?
4. What is instruction set Architecture?
An instruction set, or instruction set architecture (ISA), is the part of thecomputer architecture related to
programming, including the native data types, instructions, registers, addressing modes, memory
architecture, interrupt and exception handling, and external I/O.
5. Define application binary interface
In computer software, an application binary interface (ABI) is theinterface between two program
modules, one of which is often a library or operating system, at the level of machine code.
6. Differentiate DRAM and SRAM.
DRAM

SRAM

DRAM is dynamic

SRAM is static

DRAM makes use of capacitors to store bits in the

form of charge.
It is slower
Less expensive per bit
Power consumption is more
More memory per chip

SRAM essentially uses latches to store charge.

It is Faster
More expensive per bit
Power consumption is Less
Less memory per chip

7. Compare Volatile and nonvolatile memory.

VOLATILE MEMORY
NON VOLATILE MEMORY
Memory units that loose the stored information when Memory units that retain the stored information
power is turned off are said to be volatile.
even when the power is turned off are said to be
non-volatile.
Many semiconductor memories are volatile.
Magnetic memories and some semiconductor
memories are non-volatile.
RAM is an example of volatile memory.
ROM is an example of non-volatile memory.
Volatile memory is very fast in data processing
slow in speed.
8.

List the advantages of Network Computer.

Increased Communication Capabilities
Avoid File Duplication and Corruption
All computers in the network can share resources such as printers, fax machines, modems, and
scanners.
Networks offer a quick and easy way to share files directly.
9. Define VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by

combining thousands of transistors into a single chip. VLSI began in the 1970s when complex
semiconductor and communication technologies were being developed.
10. Differentiate Throughput and Response Time
THROUGHPUT

RESPONSE TIME

Throughput measures quantity of queries completed

during a time interval
Throughput measures is the number of queries
executed in an hour
Throughput is a measure of the amount of work
processed

Response Time measures the average duration of

queries
Response Time is the elapsed time per query
Response Time is a measure of process
completion

11. Write the CPU performance equation.

T=N*S/R
T=processor time
N=no of instructions
S=no of steps
R=clock rate
12. If computer A runs a program in 10 seconds, and computer B runs the same program in 15
seconds, how much faster is A over B.
PerformanceA/PerformanceB=n
Performance ratio: 15/10 = 1.5
A is 1.5 times faster than B
13. What are the basic components of performance?
14. Write the formula for CPU execution time for a program
15. Write the formula for CPU clock cycles required for a program.
16. How will you measure the dynamic power dissipation?
17. Define - Stored Program Concepts
Stored program concept is one in which first the program and data are stored in the main memory and then
the processor fetches instructions and executes them, one after another.
18. What are the fields in an MIPS instruction?
19. Write an example for immediate operand

An immediate operand is a constant value or the result of a constant expression.

[Eg] mov cx, 20
; Load constant to register
add var, 1Fh
; Add hex constant to variable
sub bx, 25 * 80 ; Subtract constant expression
20. Write operations to perform sum of four variables b,c,d,e and store the result in a.
21. List the advantages of multiprocessor over uniprocessor.
A uniprocessor system has a single computer processor, while multiprocessor systems have two or more. For
uniprocessors, memory is consistent. For multiprocessors multiprocessor performance, memory consistency
is relaxed.
22. What are the different types of operands? Give examples
23. List the different addressing modes

Addressing
modes
Register
Immediate
Displacement

Example
Instruction
Add R4,R3
Add R4, #3

Meaning

R4 <- R4 + R3
R4 <- R4 + 3
R4 <- R4 +
Add R4, 100(R1)
M[100+R1]

Register deffered Add R4,(R1)

R4 <- R4 + M[R1]

Indexed

Add R3, (R1 +

R2)

R3 <- R3 +
M[R1+R2]

Direct

Add R1, (1001)

R1 <- R1 +
M[1001]

When used
When a value is in a register
For constants
Accessing local variables
Accessing using a pointer or a computed
address
Useful in array addressing:
R1 - base of array
R2 - index amount
Useful in accessing static data

Memory deferredAdd R1, @(R3)

Autoincrement

Add R1, (R2)+

Autodecrement

Add R1,-(R2)

R1 <- R1 +
M[M[R3]]

If R3 is the address of a pointer p, then

mode yields *p
Useful for stepping through arrays in a
R1 <- R1 +M[R2] loop.
R2 <- R2 + d
R2 - start of array
d - size of an element
Same as autoincrement.
R2 <-R2-d
Both can also be used to implement a
R1 <- R1 + M[R2]
stack as push and pop

24. Define addressing mode.

The different ways in which the location of an operand is specified in an instruction are referred to as
addressing modes.

PART-B
1. i)Discuss in detail about Eight great ideas of computer Architecture.(8)
ii) Explain in detail about Technologies for Building Processors and Memory (8)
2. Explain the various components of computer System with neat diagram (16)
3. Discuss in detail the various measures of performance of a computer(16)
4. Define Addressing mode and explain the basic addressing modes with an example for
each.
5. Explain operations and operands of computer Hardware in detail (16)
6. i)Discuss the Logical operations and control operations of computer (12)
ii)Write short notes on Power wall(6)
7. Consider three different processors P1, P2, and P3 executing the same instruction
set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0
GHz clock rate and has a CPI of 2.2
.
a.
Which processor has the highest performance expressed in instructions per
second?
b.
If
the processors each execute a program in 10 seconds, find the
number of cycles and the number of instructions.
c.
We
are trying to reduce the execution time by 30% but this leads to an
increase of 20% in the CPI. What clock rate should we have to get this time reduction?
8. Assume a program requires the execution of 50 x 106 FP instructions,110 x 106 INT instructions, 80 x
106 L/S instructions, and 16 x 106 branchinstructions. The CPI for each type of instruction is 1, 1, 4 and 2
respectively.Assume that the processor has a 2 GHz clock rate.
a.
By how much must we improve the CPI of FP instructions ifwe want the program to run two
times faster?
b.
By how much must we improve the CPI of L/S instructionsif we want the program to run two
times faster?
c.
By how much is the execution time of the program improvedif the CPI of INT and FP
instructions is reduced by 40% and the CPI of L/S and
Branch is reduced by 30%?
9.
Explain
Branching operations with example
10.
Explain
the following addressing modes in detail with diagram
i)Immediate addressing ii)Register addressing, iii)Baseor displacement addressing, iv)PC-relative
addressing v)Pseudodirect addressing

UNIT-II ARITHMETIC OPERATIONS PART-A

1.
2.
3.
4.

Add 610 to 710 in binary and Subtract 610 from 710 in binary
Write the overflow conditions for addition and subtraction.
Draw the Multiplication hardware diagram
List the steps of multiplication algorithm

5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.

What is fast multiplication?

List the steps of division algorithm
What is scientific notation and normalization? Give an example
Give the representation of single precision floating point number
Define overflow and under flow with examples
Give the representation of double precision floating point number
What are the floating point instructions in MIPS?
What are the steps of floating point addition?
List the steps of floating point multiplication
Define - Guard and Round
Write the IEEE 754 floating point format.
What is meant by sub-word parallelism?
Subword Parallelism is a technique that enables the full use of word-oriented datapaths when dealing
with lower-precision data. It is a form of low-cost, small-scale SIMD parallelism.
Multiply 100010 * 100110.
Divide 1,001,010ten by 1000ten.

For the following C statement, what is the corresponding MIPS assembly code?
f = g + (h 5).

subi f, h, 5
addi f, f, g

# Temporary variable f contains h 5

20. For the following MIPS assembly instructions above, what is a corresponding
C statement?

add f, g, h
add f, i, f

f = g + h;
// (g + h) is being stored in the value of f
f = i + f;
// the value of f from the first statement is being added to i and stored in f
f = i + (g + h);
//same as the two before but is more readable

PART- B
1.
2.
3.
4.
5.
6.

Explain the Multiplication algorithm in detail with diagram and examples

Discuss in detail about division algorithm in detail with diagram and examples
Explain in detail about floating point addition with example
Explain in detail about floating point multiplication
Give the algorithm for multiplication of signed 2's complement numbers and illustrate with an example
Multiply the following pair of signed 2's complement numbers :
A = 010111, B = 101100.
7. Add the numbers 0.510 and -0.437510using binary Floating point Addition algorithm
8. Multiply 1.10 10X 1010and 9.200X10-5 using binary Floating point multiplication
9. Calculate the division of A and B
A : 3.264 X 103 B: 6.52 X 102 10 .Show the IEEE 754 binary representation of the number
-0.75 10in single and double precision

UNIT III PROCESSOR AND CONTROL UNIT

PART-A
1. What is meant by data path element?
The datapath elements are the functional blocks within a microprocessor that actually interact to perform
computational operations. These tasks include reading/writing to memory, arithmetic, logic
operations, and numerical shift operations.
2. What is the use of PC register?
The program counter, PC, is a special-purpose register that is used by the processor to hold the address of the
next instruction to be executed. It keeps track of the the next memory address of the instruction that is to be
executed once the execution of the current instruction is completed.
3. What is meant by register file?
A register file is an array of processor registers in a central processing unit (CPU). The register file is the
component that contains all the general purpose registers of the microprocessor. A few CPUs also place
special registers such as the PC and the status register in the register file.
4. What are the two state elements needed to store and access an instruction?
Instruction Memory
Program Counter
5. Draw the diagram of portion of datapath used for fetching instruction.
6. Define - Sign Extend

Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a
binary number while preserving the number'ssign (positive/negative) and value.
7. What is meant by branch target address?
8. Differentiate branch taken from branch not taken.
9. What is meant by delayed branch?
delayed branch is a conditional branch instruction found in some RISCarchitectures that include pipelining.
The effect is to execute one or more instructions following the conditional branch before the branch is taken.
This avoids stalling the pipe*line while the branch condition is evaluated
10.Write the instruction format for the jump instruction.
11. What are hazards? Write its types.
12.What is meant by forwarding?
Forwarding is the concept of making data available to the input of the ALU for subsequent instructions, even
though the generating instruction hasnt gotten to WB in order to write the memory or registers.
13.What is pipeline stall?
In computing, a bubble or pipeline stall is a delay in execution of an instruction in an
instruction pipeline in order to resolve a hazard. During the decoding stage, the control unit will
determine if the decoded instruction reads from a register that the instruction currently in the execution
stage writes to.
14.What is meant by branch prediction?
A technique used in some processors with instruction
prefetch to guesswhether a conditional branch will be taken or not and prefetch code fromthe appropriate loca
tion.
When a branch instruction is executed, its address and that of the nextinstruction executed (the chosen destina
tion of the branch) are stored inthe Branch Target Buffer.
15.What are exceptions and interrupts?
An interrupt is usually defined as an event that alters the sequence of instructions executed by a processor.
Interrupts are issued by interval timers and I/O devices. Exceptions are caused either by programming errors
or by anomalous conditions that must be handled by the kernel.
16.Define - Vectored Interrupts
In a computer, a vectored interrupt is an I/O interrupt that tells the part of the computer that handles
I/O interrupts at the hardware level that a request for attention from an I/O device has been received
and and also identifies the device that sent the request.
17.What is meant by pipelining?

Pipelining is a form of computer organization in which successive steps of an instruction sequence are
executed in turn by a sequence of modules able to operate concurrently, so that another instruction can be
begun before the previous one is finished.
18.What are the five steps in MIPS instruction execution? Or What are the 5 pipeline stages?
The MIPS pipeline has five stages:
IF: instruction fetch
ID: instruction decode and register read
ALU: ALU execution`/89 MEM: data memory read or write
WB: write result back into a register
19.What are the three instruction classes and their instruction formats?
I-Type (Immediate)
J-Type (Jump)
R-Type (Register)
20.Write the formula for calculating time between instructions in a pipelined processor.

PART B
1. Explain the basic MIPS implementation of instruction set
2. Explain the basic MIPS implementation with necessary multiplexers and control lines
3. What are control hazards? Explain the methods for dealing with the control hazards.
Discuss the influence of pipelining in detai
l
4.
5. Explain how the instruction pipeline works. What are the various situations where an instruction pipeline
can stall? What can be its resolution?
6. What is data hazard? How do you overcome it?What are its side effects?
7. Discuss the data and control path methods in pipelining
8. Explain dynamic branch prediction
9. How exceptions are handled in MIPS
10. Explain in detail about building a datapath
11. Explain in detail about control implementation scheme

UNIT IVPARALLELISAM
PART-A
1. What is meant by ILP?
Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be
performed simultaneously. The potential overlap among instructions is called instruction level parallelism.
There are two approaches to instruction level parallelism:
Hardware
Software
2. What is multiple issue? Write any two approaches.
the ability to execute more than one instruction at a time is called multiple issue. There are two general
approaches to multiple issue:
static multiple issue (where the scheduling is done at compile time)
dynamic multiple issue (where the scheduling is done at execution time), also known as superscalar.
3. What is meant by speculation?
4. Define - Static Multiple Issue
5. Define - Issue Slots and Issue Packet
6. Define VLIW
Very long instruction word or VLIW refers to a processor architecture designed to take advantage
of instruction level parallelism (ILP). A VLIW processor allows programs that can explicitly specify

instructions to be executed at the same time

7. Define - Superscalar Processor
A superscalar CPU architecture implements a form of parallelism called instruction-level parallelism
within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at
a given clock rate.
8. What is meant by loop unrolling?
Loop unrolling is a compiler optimization applied to certain kinds of loops to reduce the frequency of
branches and loop maintenance instructions. It is easily applied to sequential array processing loops where
the number of iterations is known prior to execution of the loop.
9. What is meant by anti-dependence? How is it removed?
An anti-dependency, also known as write-after-read (WAR), occurs when an instruction requires a value that
is later updated.
In the following example, instruction 2 anti-depends on instruction 3 the ordering of these instructions
cannot be changed, nor can they be executed in parallel (possibly changing the instruction ordering), as this
would affect the final value of A.
1. B = 3
2. A = B + 1
3. B = 7
An anti-dependency is an example of a name dependency. That is, renaming of variables could remove the
dependency, as in the next example:
1. B = 3
N. B2 = B
2. A = B2 + 1
3. B = 7

10. Differentiate in-order execution from out-of-order execution.

In-order instruction execution
instructions are fetched, executed & completed in compilergenerated order
one stalls, they all stall
instructions are statically scheduled
Out-of-order instruction execution
instructions are fetched in compiler-generated order
instruction completion may be in-order (today) or out-of-order (older
computers)
in between they may be executed in some other order
independent instructions behind a stalled instruction can pass it
instructions are dynamically scheduled
11. What is meant by hardware multithreading?
12. What are the two main approaches to hardware multithreading?
13. What is SMT?
14. Compare SMT from hardware multithreading.
15. What are the three multithreading options?
16. Define - SMP
17. Differentiate UMA from NUMA.
18. What is a multicore microprocessor?
19. What is a parallel processing program?
20. Define a cluster

PART- B
1.
Explain Instruction level parallelism
2.
Explain the difficulties faced by parallel processing programs
3.
Explain shared memory multiprocessor
4.
Explain in detail Flynn's classification of parallel hardware
5.
Explain cluster and other Message passing Multiprocessor
6.
Explain in detail hardware Multithreading
7.
Explain SISD and MIMD
8.
Explain SIMD and SPMD
9.
Explain Multicore processors
Explain the different types of multithreadin

g
10.

UNIT V MEMORY AND I/O SYSTEM

PART-A
1. What are the temporal and spatial localities of references?

Temporal locality: states that recently accessed items are likely to be accessed in the near
future. Spatial locality: says that items whose addresses are near one another tend to be
referenced close together in time.
2.
3.
4.
5.
6.
7.
8.

Write the structure of memory hierarchy

What are the various memory technologies?
Differentiate SRAM from DRAM.
What is flash memory?
Define - Rotational Latency
What is direct-mapped cache?
Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte address
1200 map?
The block is given by (block address) modulo (Number of cache blocks)
Where the address of the block is Byte address/Bytes per clock
Notice that his block addresss is the block containing all addresses between (Byte
address/Bytes per clock)*Bytes per clock and ( Byteaddresss/ Bytes per block) *Bytes per
block+ (Bytes per block - 1)
Thus, with 16 bytes per clock, byte address 1200 is block address (1200/16)=75 which
maps to cache block number (75 modulo 64)=11

Bits in a Cache
9. How many total bits are required for a direct-mapped cache with 16 KB of data and 4-word blocks,
assuming a 32-bit address?
We know that 64 KB is 64K words, which is 2 to the power 14 words, and, with a block size of one
word, 2 to the power 14 blocks. Each block hs 32 bits of data plus a tag, which is 32-14-2 bits, plus a
valid bit. Thus, the total cache size is (2 to the power 14)*49= 784 bits or 98KB for a 64-KB cache. For
this cache, the total number of bits in the cache is over 1.5 times as many as needed just for the storage of
the data.
10. What are the writing strategies in cache memory?

Write strategies
o Write-through

+ memory consistent
- more memory traffic
o Write-back

+ less memory intensive

- extra administration
- slow context switch
11. What are the steps to be taken in an instruction cache miss?
12.
13. What are the various block placement schemes in cache memory?

14.
15.
16.
17.
18.
19.
20.

Define - MTTF and AFR

Define - Availability
What are the three ways to improve MTTF?
Define - TLB
What is meant by virtual memory?
Differentiate physical address from logical address.
What is meant by address mapping?

21. What is latency?

Latency is the number of cycles after initiation of an operation before the result is available

PART- B
1. Explain in detail about memory technologies
2. Explain in detail about memory Hierarchy with neat diagram
3. Describe the basic operations of cache in detail with diagram
4. Discuss the various mapping schemes used in cache design
A byte addressable computer has a small data cache capable of holding eight 32-bit words. Each cache
block contains 132-bit word. When a given program is executed, the processor reads data from the
following sequence of hex addresses - 200, 204, 208, 20C, 2F4, 2F0, 200, 204,218, 21C, 24C, 2F4. The
pattern is repeated four times. Assuming that the cache is initially empty, show the contents of the cache
at the end of each pass, and compute the hit rate for a direct mapped cache.
5. Discuss the methods used to measure and improve the performance of the cache.
6. Explain the virtual memory address translation and TLB withnecessary diagram.
7. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer
between memory and peripherals.
8. Explain in detail about interrupts with diagram
9. Describe in detail about programmedInput/output with neat diagram
10. Explain in detail about I/O processor.
11.