MIXED

DESIGN

MIXDES 2010, 17th International Conference "Mixed Design of Integrated Circuits and Systems", June 24-26, 2010, Wroc
aw, Poland

Compact Physics-based Model for Ultrashort FinFETs

Ashkhen Yesayan1,2, Nicolas Chevillon1, Fabien Prgaldiny1 and Christophe Lallement1
1)

InESS / University of Strasbourg

Parc dinnovation,
BP 10413, 67412 Illkirch Cedex, France
2)
Yerevan State University
1 Alek Manookian St.,
375025 Yerevan, Armenia
Contact author: f.pregaldiny@unistra.fr

AbstractA fully explicit physics-based model for ultrashort

undoped (or lightly doped) FinFETs is proposed. In particular, a
new physical approach to account for short-channel effects is
presented as an extension of the long channel model. The
modeling of small geometry effects relies on the accurate
description of the potential profile along the channel and in
particular on the position of the minimum potential. This is
achieved without using any empirical parameters. The impact of
carrier mobility degradation is also studied and taken into
account. This design-oriented model is valid and continuous in all
operating regimes. Comparisons between the model and 3-D
Silvaco simulations are performed and show the usefulness of this
compact model for high-performance circuit design.
Index TermsFinFET, compact model, short-channel effects,
carrier mobility, circuit simulation.
Figure 1. 3-D FinFET structure modeled in this work.

I. INTRODUCTION
As it is known, multi-gate MOSFETs are good alternatives
of conventional MOSFETs for sub 100 nm CMOS
technology [1]. The key factors that limit how far a multi-gate
MOSFET can be scaled come from short-channel effects
(SCEs) such as threshold voltage roll-off and drain-induced
barrier lowering (DIBL). The choice of undoped channel is
preferable because of the dopant fluctuation and associated
improvement in mobility. Several compact FinFET or double
gate (DG) MOSFET models have been published [2-7].
However, there is still a lack of accurate and fully analytic
compact modeling of extremely short DG or FinFET devices.
An explicit compact model is proposed in [7,8] but the good
accuracy is achieved by using a set of extracted empirical
parameters.
Here is proposed an explicit, fully analytical approach to
model the short channel effects for undoped DG and FinFET.
The model is based on the exact solution of potential profile
along the channel [9].
The paper is organized as follows. Section II presents the
analytical model. The core of the long-channel model is briefly
described and then the modeling of short channel MOSFET in
weak and strong inversion is detailed. Section III presents the
comparisons with Atlas simulations and discussions.
This work was carried out within the framework of Research Projects EU
COMON IAPP (FP7-IAPP-no 218255)

II. ANALYTICAL MODEL

The 3-D FinFET structure studied in this paper is shown in
Fig. 1. The silicon film is lightly doped and the silicon height
(HSi) is higher than 50 nm so we can neglect the corner effects.
The top oxide thickness is about 50 nm so that we can consider
the horizontal section of FinFET as a DG MOSFET. In these
conditions, we can derive the FinFET compact model from the
one derived for DG MOSFET [2-5]. The polydepletion effect is
neglected by using a metal gate.
A. Long-channel drain current model
In our investigations, all the electric quantities such as
voltage, current and charge are normalized as detailed in [2].
For the sake of clarity, we remind the fundamental relations
of the long-channel DG MOSFET charge-based model. The
important relationship between the charge density and the bias
voltages, given in [2], is:
v p  vch

4qg  ln qg  ln 1  D qg  with D

Cox
CSi

(1)

where vp = vg - vto is the pinch-off voltage (here we propose

that the gate work function difference is negligible), vch is the
electron quasi-Fermi potential, qg is the gate charge density,
Cox is the gate oxide capacitance per unit surface of each gate,

*QTv`B;?i kyRy #v .2T`iK2Mi Q7 JB+`Q2H2+i`QMB+b  *QKTmi2` a+B2M+2- h2+?MB+H lMBp2`bBiv Q7 GQ/x

d8

CSi is the silicon layer capacitance per unit surface and vto is the
normalized long-channel threshold voltage [2].

i qm2  2qm 

qmD

D
ln 1  q
D 2 m qmS
2

(2)

where i is the normalized current and qm is the normalized

mobile charge density (qm = 2qg). This model is valid for both
DG MOSFET and FinFET with long channel.
B. Short-channel drain current model in weak inversion
The importance of the source to channel barrier is well
known and routinely considered when treating drain-induced
barrier lowering or weak inversion operation. It is a good
approximation to consider that free carriers diffuse from this
energy barrier and swept into the drain forming the
subthreshold drain current. The barrier also exists above
threshold, but the channel charge screens the gate voltage, so
the gate voltage has less influence on the surface potential. In
the case of short channels the potential minimum occurs in the
middle of the channel [11] and is known as virtual
cathode [12]. The potential profile along the channel is not flat
even if there is no drain to source applied voltage and gradual
channel approximation (GCA) can no longer be applied. To
escape this situation, and having in the mind the importance of
potential minimum in formation of subthreshold current, we
propose a model where the potential at virtual cathode is
extended throughout the whole channel (see Fig. 2). Our short
channel model is based on this assumption. To extend the long
channel model for short channel devices, we propose a
structure with a constant surface potential along the channel
equal to the one we have at virtual cathode of short channel
(\smin). This situation is illustrated in Fig. 2, where the surface
potential for a channel length of 1 Pm is taken as a reference.
For a short channel, e.g., L = 25 nm, the surface potential is not
flat and has the minimum approximately in the center of
channel. In Fig. 2, \'min is the shift of the minimum surface
potential for this structure from reference point (surface
potential of long channel). In our model we add this shift to
surface potential of long channel (\s0) in order to obtain flat
surface potential along the channel of short device (dotted line
in Fig. 2).

\ s min \ s 0  \ ' min

where \'min is a function depending on applied voltages.

de

Surface
potential

We need to obtain the mobile charge density according to

the bias voltages. To solve (1) without any iteration, we use an
algorithm to compute the charge density as an explicit function
of the voltages [10]. The physics of (1) is preserved, therefore
the validity of the algorithm is technology-independent. This
numerical inversion allows using our model for circuit
simulation. Then, noting that the mobile charge density is twice
the gate charge density and assuming that the drift-diffusion
transport model is valid, the normalized drain current for a
long-channel FinFET can be expressed as:

WSi

=
3
nm

\
smin

\
min

L=50
nm

L=1
Pm

\
S0
Position
close
to
the
center
of
the
channel

Figure 2. Surface potential in the middle of the channel at different channel

lengths. Modeled surface potential is shown with dotted line for L = 25 nm.

In weak inversion, for undoped long channel DG

MOSFET, the surface potential can be assumed equal to vg
[9,13], so to keep the form of the long channel model and to
extend it for short channel case, we simply replace vg by vgN in
the derivation of the long channel model [2]:
vgN \ s 0

(4)

4q g

where
vgN

vg  \ ' min

(5)

To calculate \'min, we use the accurate solution of potential

profile along the channel derived in [9]. Based on the general
scale length analysis [9] presents strong physical basis, since
no assumption is initially made on the potential pro
le into the
channel. We use the simple solution of potential profile given
for the structures where O/L > 1.5, here L is the gate length and
O is general scaling length. From comparison of drain current
curves with Atlas simulations we have seen that it is a good
approximation to consider the position of the minimum of
surface potential in the middle of the channel. This
approximation is already used in [3,11]. Eq. (5) is valid in
subthreshold regime, but it can be extended also in strong
inversion as \'min tends to zero at high gate voltages. The term
vgN is the solution of potential minimum only in weak inversion
and mathematically it tends to vg in high inversion, which we
need for our model. This is illustrated in Fig. 3, where two
devices are considered with the same WSi and different channel
lengths. It can be seen that the impact of \'min is reduced with
increasing channel length.
Due to roll-off effect, the pinch-off voltage has to be
changed too. The slope factor n is introduced in the pinch-off
voltage as in [6]:
v p*

where n is given by:

(3)

Modeled
surface

potential

L=25
nm

 vg  vto 

(6)

wvg

1
(7)
w\ c min
L
L
1  2sinh
sinh

2O
O
where \cmin is the minimum potential along the channel in the
center of device.
To smooth the slope degradation in high inversion regime we
substitute vp* in (2) only in the second and third terms which
are signi
cant in weak inversion. Thus substituting (5) and (7)
in (1) and (2), we extend the long channel model to short
n

For CLM, we used a pseudo two dimensional analysis as

proposed in [14] and subsequently modified by others [15,16].
Assuming that there is no charge in the pinch-off area, the
simplified form of CLM is:

'L

where Ec

J ln

vd  vdeff

J Ec

V0
and J
U T P0

vd  vdeff

J Ec

H Si WSi
3Cox 2

 1

(9)

Here HSi is the dielectric permittivity of silicon and P0 is the

constant mobility fixed at 1000 cm2/Vs. The lateral electric
field is assumed to be negligible in the channel region (LL)
and V0 can be treated as the thermal velocity of electrons. For
degenerate electron gas in 100 silicon layers, thermal velocity
of electrons reaches 1.2107 cm/s [17], therefore we set V0 to
this value in our calculations.

channel devices down to O/L | 1.5.

Figure 3. The ratio of vgN to applied gate voltage for two different structures.

C. Short-channel drain current model in strong inversion

1) Channel length modulation with constant mobility
To focus properly on short-channel effects and to validate
the model we at first keep the mobility () as a constant both in
analytical model and Atlas simulations.
To accurately model the operation of the device in
saturation, the two-dimensional nature of space charge near the
drain must be considered. In the case where mobility is kept
constant, the channel length modulation (CLM) is applied to
define the actual size of the channel where GCA is applicable.
In the presence of mobility degradation, the scattering limited
velocity effects are equivalent to increasing the channel length
of the device [14]. As we have no velocity saturation effects (
is considered as a constant), the drain saturation voltage (vdsat)
is the conventional pinch-off voltage. To extend the validity of
the model in weak inversion, the pinch-off voltage is replaced
by Qs/2Cox [15], where Qs is the charge density at the source.
Then to get the theoretical value for vdsat in weak inversion
which is the twice of thermal voltage (UT) [15], Qs was
replaced by Qseff. After normalization we have:

vdsat

2qseff

1
2 qs 

1  qs

(8)

where qs = Qs/4CoxUT [2]. A smooth transition from ohmic

region to saturation region is obtained by using a smoothing
function from [16].

2) CLM with the impact of mobility degradation

Scattering limited velocity saturation is an important effect
that has to be taken into account in short channel transistors.
Due to velocity saturation effect, the drain current saturates
before the drain voltage reaches the pinch-off point. With
velocity saturation taken into account, (8) has to be changed
with one of the most used expressions for vdsat [3, 15]:

vdsat

2qseff
1

1
UT Ptrans qseff

(10)

T LVsat

where
qseff

qs 

1
UT Ptrans
1
LVsat

(11)

Vsat is the value of velocity saturation, Ptrans is the effective

transverse mobility and T is a fitting parameter that we add
here to get a better agreement with simulations. For the
complete derivation of CLM, we follow [3].
D. Mobility model
The mobility at high inversion layers is already well
modeled in different compact models [3,4,16], but for weak
inversion this problem is still open. The mobility degradation is
significant for channel lengths below 100 nm. The low field
mobility dependence on channel length has been
experimentally studied in [18,19].
It is observed that when silicon film is thinned down to a
few nanometers, electron mobility in low and moderate
inversion layers becomes WSi dependent [20-23]. The mobility

dd

degradation at low-inversion layers is especially strong for the

smallest WSi values (3-5 nm). It was pointed out that the
scattering with surface optical phonons plays important role in
low-field transport for ultra-thin SOI transistors [21].
To see how strong the device characteristics are influenced
by mobility degradation, we compare threshold voltage roll-off
extracted from Atlas simulations with constant mobility and
with CVT model. As it can be seen in Fig. 4 the difference
between the roll-off curves from two simulations is significant
below 100 nm.

where P0 is low field mobility, e0 and e1 are fitting parameters.

The transverse electric field now consists in two terms. EQ acts
in moderate and high inversion layers and can be introduced
as EQ = qg4UTCox/HSi. Es is the electric field normal to the
surface in the middle of the channel (at the position of
minimum potential) without the impact of mobile charge. Es is
calculated from potential profile in [9]. This term of transverse
electric field is significant in weak inversion and tends to zero
for long channel devices. The mobility dependence on
longitudinal electric field is considered as follows:

Ptrans
1
2

(13)

P
v U
1  trans deff T
Vsat  L  'L 

III. RESULTS AND DISSCUSION

The presented model is compared with 3-D Atlas
simulations. To validate the model we at first keep the mobility
as a constant both in analytical model and Atlas simulations.

Figure 4. Threshold voltage roll-off extracted from 3-D Atlas simulations as

a function of channel length for WSi = 3 nm for both CVT and constant
mobility models.

In this work, we propose a simple model for the

dependence of the transverse mobility on both channel length
and channel width. To model the mobility we start from
Lombardi mobility model, which is also used in Atlas
numerical simulations [24]. This model includes optical
intervalley and acoustic phonons, surface roughness and
velocity saturation. Optical and acoustic phonons decrease the
mobility for a medium transverse electrical field, whereas the
surface roughness acts at high field. The transverse electric
field in short channel devices even at low-gate voltages
exceeds 106 V/cm and it is reasonable to conclude that it will
have significant influence on mobility degradation at low
inversion layers and should be taken into account in mobility
expression.
In Atlas simulations, the local electric field is considered. It
is impossible to do in compact modeling because the current
could not be explicitly derived. We have seen that a good
approximation is to calculate the surface electric field in the
center of device. Thus for transverse effective mobility we can
write:

P0

Ptrans
1

d3

Es EQ

e0
e1

(12)

The drain current is in excellent agreement with numerical

simulations (NS) in a wide range of silicon thicknesses. Fig. 5
shows the drain current versus gate voltage for L = 50 nm and
different WSi. For short channel effects the important factor is
the ratio r = L/O, e.g., for WSi = 20 nm and L = 50 nm r | 1.7
and there is a good agreement with NS, while for L = 70 nm
(r | 2.5) the short channel effects are not so strong and the
agreement with NS is ideal (see Fig. 6). Note that for the same
length L = 70 nm, when the silicon thickness is thinned down,
e.g. WSi = 3 nm, then r | 7 and the effect of DIBL disappears.
Fig. 7 shows the drain current versus gate voltage at
different gate lengths for WSi = 10 nm. The subthreshold slope
is accurately described for different channel lengths as shown
by the good agreement in this region. Let us note that to have a
better agreement with NS, a small shift of 0.013 V was added
to surface potential in drain current calculations presented in
Figs. 5-7.
The impact of mobility degradation and velocity saturation
are shown in Figs 8-9. Fig. 8 presents the drain current versus
drain voltage at different gate voltages for the structure with
WSi = 3 nm and L = 25 nm. The fitting parameter T in (10) is a
technological independent parameter (T = 3) and is constant in
our calculations. The scattering limited velocity is set to
Vsat = 1.2107 cm/s and P0 = 1080 cm2/Vs was extracted from
simulations at L = 100 nm. Comparisons with NS show a good
accuracy of output characteristics.

Figure 5. Representation in logarithmic scale of the drain current versus the

gate voltage for L = 50 nm and different WSi. Explicit model: lines; 3-D
simulations: markers.

Figure 6. Representation in linear and logarithmic scales of the drain current

versus the gate voltage for WSi = 20 nm and L = 70 nm. Explicit model: lines;
3-D simulations: markers.

In Fig. 9, the roll-off is calculated and compared with Atlas

simulations. The accuracy of Ptrans in weak and moderate
inversion is illustrated by the excellent agreement of roll-off
curves extracted from the model and the Atlas simulation with
CVT model. The roll-off is de
ned as the shift of the gate
voltage required to obtain the same current level (in weak
inversion) for both short and long-channel devices. It appears
that the roll-off curves calculated from the drain current model
with constant mobility and with mobility degradation effect
taken into account have a large difference below L = 100 nm.
The roll-off curve with a constant mobility shows the good
behavior of the potential minimum model. The roll-off curve
extracted with adapted mobility model gives evidence for the
accuracy of our mobility model in weak inversion. As we can
see, in both cases the analytical model gives a very good
agreement with NS.

Figure 7. Representation in linear and logarithmic scales of the drain current

versus the gate voltage for WSi = 10 nm and different channel lengths. Explicit
model: lines; 3-D simulations: markers.

Figure 8. Representation of the drain current versus the drain voltage for
different gate voltages for WSi = 3 nm and L = 25 nm. Mobility degradation is
taken into account. Explicit model: lines; 3-D simulations: markers.

Figure 9. Threshold voltage roll-off extracted from the analytical model and
3-D Atlas simulations as a function of channel length for WSi = 3 nm with both
CVT and constant mobility models.

dN

Table I shows the difference between the presented model

and our previous model [7]. The drastic reduction in the
number of model parameters makes the new model very well
suited for circuit simulation and circuit design. Let us also
emphasize that we have defined an extraction procedure of
model parameters with the characterization software IC-CAP.

[5]

[6]

[7]
TABLE I. COMPARISON OF THE PARAMETER NUMBER BETWEEN THE
PREVIOUS AND THE PRESENT MODEL

[8]
Modeled effect
Roll-off

Modeling
Previous model [7]

Present model

9 parameters

DIBL

9 parameters

Subthreshold slope

no parameter

CLM

1 parameter

Mobility

1 parameter (P0)

1 parameter

3 parameters

IV. CONCLUSION

[9]

[10]

[11]

[12]

A new analytical approach was proposed to include short

channel effects in our explicit compact model for long channel
FinFETs. This model is physics-based and predictive, hence
applicable to the compact modeling of FinFETs. The proposed
solutions have been validated by 3-D numerical simulations in
all operating regions without any problems of convergence.
The model accounts well for a large range of silicon layer
thicknesses (from WSi = 3 nm up to 20 nm) and channel lengths
(L = 25 nm up to 1 Pm). The mobility degradation is taken into
account in model, and we have shown that the mobility
degradation is an important factor for accurate calculation of
roll-off and DIBL. All quantities in the model are expressed in
terms of normalized variables. This allows us to significantly
simplify both model formulation and associated parameter
extraction, and makes the model very useful for the circuit
designer. In a future work, this compact model will be
completed by a new physical modeling of quantum effects (a
semi-empirical quantum model was introduced in [7]).

[19]

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