OR

4. a) Discuss on Fault Detection and Redundancy in Combinational

Circuits
b) What is Deductive Fault Simulation? Discuss

6
6

UNIT-III
5. a) Explain D-Algorithm with pseudo code
b) Explain TG for Fault Models

6
6

OR

6. a) What is Back tracking? Give an example

b) Discuss about Functional Fault Models for microprocessors

6
6

UNIT-IV
7. a) Explain Ad Hoc Design for Testability Techniques
b) Write a short notes on Syndrome testing

6
6

OR
8. a) Describe the method to enhance observability and controllability
by means of scan register
6
b) What is Transition-count compression? Elaborate
6
UNIT-V
9. a) Explain Pseudo exhaustive Testing, TPG Technique
b) Write a short note on BEST and RTS

6
6

OR
10. a) Discuss on A concurrent BIST Architecture
b) Write a brief note on BILBO architecture

6
6

[12/II S/211]

[A-11]

[EPRVD 204A]

M.Tech. DEGREE EXAMINATION

VLSI DESIGN
II SEMESTER
DIGITAL SYSTEMS TESTING & TESTABILITY
(Effective from the admitted batch 200910)
Time: 3 Hours
Max.Marks: 60
---------------------------------------------------------------------------------------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- -------------

UNIT-I
1. a) Explain Functional Modeling at the Register Level
b) Explain Event-driven simulation with an example

6
6

OR

2. a) Construct a binary decision diagram for exclusive OR function

b) What are the different delay models? Discuss

6
6

UNIT-II
3. a) For the following circuit
i) Find the set of all tests that detect the fault c s-a-1
ii) Find the set of all tests that detect the fault a s-a-0
iii) Find the set of all test that detect the multiple fault
{c s a -1, a s a -0}

b) Explain Parallel Fault Simulation with an example

OR

4. a) Discuss on Fault Detection and Redundancy in Combinational

Circuits
b) What is Deductive Fault Simulation? Discuss

6
6

UNIT-III
5. a) Explain D-Algorithm with pseudo code
b) Explain TG for Fault Models

6
6

OR

6. a) What is Back tracking? Give an example

b) Discuss about Functional Fault Models for microprocessors

6
6

UNIT-IV
7. a) Explain Ad Hoc Design for Testability Techniques
b) Write a short notes on Syndrome testing

6
6

OR
8. a) Describe the method to enhance observability and controllability
by means of scan register
6
b) What is Transition-count compression? Elaborate
6
UNIT-V
9. a) Explain Pseudo exhaustive Testing, TPG Technique
b) Write a short note on BEST and RTS

6
6

OR
10. a) Discuss on A concurrent BIST Architecture
b) Write a brief note on BILBO architecture

6
6

[12/II S/211]

[A-11]

[EPRVD 204A]

M.Tech. DEGREE EXAMINATION

VLSI DESIGN
II SEMESTER
DIGITAL SYSTEMS TESTING & TESTABILITY
(Effective from the admitted batch 200910)
Time: 3 Hours
Max.Marks: 60
--------------------------------------------------------------------------------- ------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- -------------

UNIT-I
1. a) Explain Functional Modeling at the Register Level
b) Explain Event-driven simulation with an example

6
6

OR

2. a) Construct a binary decision diagram for exclusive OR function

b) What are the different delay models? Discuss

6
6

UNIT-II
3. a) For the following circuit
i) Find the set of all tests that detect the fault c s-a-1
ii) Find the set of all tests that detect the fault a s-a-0
iii) Find the set of all test that detect the multiple fault
{c s a -1, a s a -0}

b) Explain Parallel Fault Simulation with an example