Question bank VLSI LAB

1.
a) Write the verilog code for the D Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common source amplifier and perform DC analysis,
transient analysis and AC analysis. Draw its layout and perform DRC, ERC and
LVS.

2.
a) Write the verilog code for the T Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common drain amplifier and perform DC analysis, transient
analysis and AC analysis. Draw its layout and perform DRC,ERC and LVS.

3.
a) Write the verilog code for the MS Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of inverter and perform DC analysis, transient analysis and
AC analysis.
4.
a) Write the verilog code for the JK Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common drain amplifier and perform DC analysis, transient
analysis and AC analysis.

5.
a) Write the verilog code for RS flip flop and perform functional verification with its
test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common drain amplifier and perform DC analysis, transient
analysis and AC analysis.

6.
a) Write the verilog code for Parallel adder and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of inverter and perform DC analysis, transient analysis and
AC analysis. Draw its layout and perform DRC, ERC and LVS.
7.
a) Write the verilog code for Binary synchronous and perform functional verification
with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of counter R-2R DAC and perform DC analysis and Transient
analysis.
8.
a) Write the verilog code for BCD counter synchronous and perform functional
verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of differential amplifier and perform DC analysis, transient
analysis and AC analysis.

9.
a) Write the verilog code for BCD counter synchronous and perform functional
verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common drain amplifier and perform DC analysis transient
analysis and AC analysis.
10.
a) Write the verilog code for Binary Asynchronous counter and perform functional
verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common drain amplifier and perform DC analysis,
transient analysis and AC analysis.
11.
a) Write the verilog code for D Filp Flop and perform functional verification with its
test code. Synthesise the code and generate the netlist.
b) Draw the schematic for differential amplifier and perform DC analysis, transient
analysis and AC analysis.
12.
a) Write the verilog code for T Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for Common source and perform DC analysis, transient
analysis and AC analysis.
13.
a) Write the verilog code for MS Flip Flop Counter and perform functional
Verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for R-2R and perform DC analysis, transient
Analysis and AC analysis.
14.
a) Write the verilog code for JK Flip Flop and perform functional
verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for inverter and perform DC analysis, transient
Analysis and AC analysis.
15.
a) Write the verilog code for the RS Flip Flop and perform functional verification with
its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for R -2R and perform DC analysis transient analysis and
AC analysis.

16.
a) Write the verilog code for the Parallel adder and perform functional verification
with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for Common Drain and perform DC analysis, transient
analysis and AC analysis.

17.
a) Write the verilog code for Binary Synchronous and perform functional verification
with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for common Drain and perform DC analysis, transient
analysis and AC analysis. Draw its layout and perform DRC, ERC and LVS.

18.
a) Write the verilog code for BCD Synchronous and perform functional verification
with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common source and perform DC analysis and Transient
analysis and Draw the layout and verify DRC, ERC and LVS.
19.
a) Write the verilog code for BCD Asynchronous and perform functional verification
with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic of Common Drain and perform DC analysis and Transient
analysis and Draw the layout and verify DRC, LVS.
20.
a) Write the verilog code for the Binary Asynchronous and perform functional
verification with its test code. Synthesise the code and generate the netlist.
b) Draw the schematic for Common source and perform DC analysis transient
analysis and AC analysis Draw its layout and perform DRC, ERC and LVS.