Académique Documents
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An Introduction
to
VDD
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
p+ diffusion
polysilicon
metal1
pMOS transistor
IC Design Cycle
Mask house
System Requirements
Fabrication house
Design house
Layout
Insulator (Sio2)
Semiconductor (diffusion)
Conducting material
(metal, polysilicon)
Design-Fabrication Interface
Design Tools
Design Rules
Design Tools: Enables designers to deal with
designs at a level that does not involve
details of fabrication process/parameters
Design Rules: Make it possible for the Circuit
to work properly (electrically) after
fabrication using an area, as small as
possible
2013 Centre for Development of Advanced Computing
Design Tools
MAGIC/ Micro Magic
Developed at the University of California, Berkeley
Virtuoso
Cadence Tools
MAGIC
An interactive Layout tool for creating and
modifying VLSI circuits
Popular in the Universities
Built-in knowledge of layout rules
Knows about connectivity and transistors
PMOS Enhancement
D
G
NMOS Enhancement
2013 Centre for Development of Advanced Computing
Color
Representation
Well (p,n)
Yellow
Well
n diffusion
Green
p diffusion
Brown
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Power Wires
Contacts
Black
Signal connection
Via
Insulator
Function
Layout example
P-transistor
L=2
W=4
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Manhattan Style
Diagonal Style
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1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
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What is ?
=> = 1
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Different Potential
0
or
6
Well
10
ndiff
2
Polysilicon
pdiff
Metal1
3
3
Contact
or Via
Hole
2
2
Metal2
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16
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No more a conductor
Drain Diffusion
Source
0
Source Diffusion
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Mask house
Layout description is
expressed into
standard interchange
formats:
1. Caltech Intermediate
Form (CIF)
2. Electronic Data
Interchange Format
(EDIF)
Formats are useful for
3. Calma GDS providing masks
2013 Centre for Development of Advanced Computing
MASK
Design house
Preprocess
software
Mask house
Fabrication house
Opaque area
Transparent area
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Defects
Etch
Repair
IC
Feature Size
Gate oxide thickness
Fabrication Process
pmos
CMOS
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Fabrication house
VLSI FABRICATION REQUIRES
AN EXPENSIVE CAPITAL
INVESTMENT
Wafer Fabrication
(Diffusion, oxidation,
photomasking, ion implant,
thin film deposition)
Final Tests
Packaging
(encapsulation)
Visual
inspection
Chip
Seperation
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Temp: ~ 1500 0 C
Ingot formation: Pure molten silicon
Czochralski Method
Mirror Polishing
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- Exposure wavelength ( ) the smaller the better.. = >>13.4nm (EUVL since 2007)
Lens size (Numerical Aperture) the larger the better
scaling has not kept up with the rate of feature size scaling
Lens size can grow upto limit Size and cost of Lenses; maximum lens size: NA = 1
Making k1 smaller has been the area of primary effort
The burden of doing this falls primarily on the mask maker!
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Must be resolved
on the Mask
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Image on the
Wafer
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Oxide
N+
nwell
pwell (Historical)
Twin tub
Silicon on insulator
Triple-well process
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N+
P
100
P+
P+
n well
p substrate
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Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
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Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
SiO2
p substrate
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Formation of n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2; only enter exposed Si
SiO2
n well
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
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Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Polysilicon Patterning
Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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Self-Aligned Process
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and
n-well contact
n well
p substrate
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N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing
n+ Diffusion
n well
p substrate
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N-diffusion
contd..
n+
n+
n+
n well
p substrate
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N-diffusion
contd..
n+
n+
n+
n well
p substrate
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P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n well
p substrate
n+
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Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
n+
n+
p+
p+
n well
p substrate
n+
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Metalization
Sputter aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
n+
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Oxide
P+
pwell Process
Start with n-type substrate (wafer)
Create p-well for n-type transistor
P+
N
100
N+
N+
P well
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P well
P+
P+
N+
N+
100
pwell
Produces balanced performance of p
and n transistors
nwell
1. Reduces latch-up
2. Low cost
- Gain
Epi => Growing single crystal film on Si surface
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-Absence of wells
Closer packing of p & n transistors
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Latchup
Formation of Parasitic Transistor/SCR
VD D
npnp
SCR
p
V DD
p
n-well
R nw ell
p-source
R n well
R psu bs
n-source
p-substrate
Firing of SCR results in heavy current, damaging the IC (VDD & GND short)
R psub s
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Guard Rings
V DD
p+
n+
p+
p+
n-well
n+
R psu bs
p-substrate
n+
R n well
Since 1994
Initially every three years
Now significant yearly updates
DRAM, Flash
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Introduction to Magic
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Layers
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Layers
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Example
:move up 10
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:upsidedown
Sideways
:sideways
Clockwise
:clockwise [degrees]
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Quit
:quit
To quit magic
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Show /Hide
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Chip Layout
Cell View
Expanded View
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Max Layers
Metals (5) and Vias/contacts between interconnect layers
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Max Features
Continuous DRC feedback during layout with hierarchical and incremental DRC
Interactive connectivity tracing
Interactive wiring tool with flylines to show connections not yet completed
Layout generator for gates (using MAX-LS)
Generators for large regular structures such as SRAMS, ROMs, PLA's, and
DRAM's (with the optional MegaCell Compiler)
Interfaces to other tools, including schematic capture (for example SUE), and
batch DRC and LVS (for example Dracula or Calibre).
Smart palette for easy control and feedback on layers
Full customization and extension via Tcl/Tk scripting language and API
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Inverter Layout :
P-transistor
F=A
A Out
0
L=2
W=4
VCC
Out
In
Metal-Diffusion
Contact
GND
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A.B = A + B
Layout ?
(W/L)p
(W/L)p
(W/L)n
(W/L)n
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A.B = A + B
(W/L)p
(W/L)p
(W/L)n
(W/L)n
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Conclusion
Continuing Research in Device, fabrication
& tool Technology fulfilling the future needs
of Industry
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