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LIST OF EXPERIMENTS:
DESIGN AND TESTING OF
1. Inverting, Non inverting and Differential amplifiers.
2. Integrator and Differentiator.
3. Instrumentation amplifier
4. Active low-pass, High-pass and band-pass filters.
5. Astable & Monostable multivibrators and Schmitt Trigger using op-amp.
6. Phase shift and Wien bridge oscillators using op-amp.
7. Astable and monostable multivibrators using NE555 Timer.
8. PLL characteristics and its use as Frequency Multiplier.
9. DC power supply using LM317 and LM723.
10. Study of SMPS.
SIMULATION USING SPICE
1. Simulation of Experiments 3, 4, 5, 6 and 7.
2. D/A and A/D converters (Successive approximation)
3. Analog multiplier
4. CMOS Inverter, NAND and NOR
TOTAL: 45 PERIODS
LIST OF EXPERIMENTS
SI.NO.
EXPERIMENT NAME
b)
a)
DESIGN AND TESTING OF ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER
b)
SIMULATION OF ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER
a)
b)
a)
DESIGN AND TESTING OF PHASE SHIFT OSCILLATOR AND WEIN BRIDGE OSCILLATOR
USING OP-AMP
b)
PAGE
NO.
10
11
12
13
STUDY OF SMPS
SIGN
IC 741:
General Description:
The IC 741 is a high performance monolithic operational amplifier constructed using the
planer epitaxial process. High common mode voltage range and absence of latch-up tendencies
make the IC 741 ideal for use as voltage follower. The high gain and wide range of operating
voltage provide superior performance in integrator, summing amplifier and general feedback
applications.
Block Diagram of Op-Amp:
Pin Configuration:
Features:
1. No frequency compensation required.
2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up
Specifications:
1. Voltage gain A = typically 2,00,000
2. I/P resistance RL = , practically 2M
3. O/P resistance R =0, practically 75
4. Bandwidth = Hz. It can be operated at any frequency
5. Common mode rejection ratio =
(Ability of op amp to reject noise voltage)
6. Slew rate + V/sec
(Rate of change of O/P voltage)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs 10K) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : 15mV
13. Input voltage range : 13V
14. Supply voltage rejection ratio : 150 V/V
15. Output voltage swing: + 13V and 13V for RL > 2K
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 s, Overshoot= 5%
Applications:
1. AC and DC amplifiers
2. Active filters
3. Oscillators
4. Comparators
5. Regulators
IC 555:
Description:
The operation of SE/NE 555 timer directly depends on its internal function. The three equal
resistors R1, R2, R3 serve as internal voltage divider for the source voltage. Thus one-third of the
source voltage VCC appears across each resistor.
Comparator is basically an Op amp which changes state when one of its inputs exceeds the
reference voltage. The reference voltage for the lower comparator is +1/3 VCC. If a trigger pulse
applied at the negative input of this comparator drops below +1/3 V CC, it causes a change in state.
The upper comparator is referenced at voltage +2/3 V CC. The output of each comparator is fed to the
input terminals of a flip flop.
The flip-flop used in the SE/NE 555 timer IC is a bistable multivibrator. This flip flop
changes states according to the voltage value of its input. Thus if the voltage at the threshold
terminal rises above +2/3 VCC, it causes upper comparator to cause flip-flop to change its states. On
the other hand, if the trigger voltage falls below +1/3 V CC, it causes lower comparator to change its
states. Thus the output of the flip flop is controlled by the voltages of the two comparators. A
change in state occurs when the threshold voltage rises above +2/3 V CC or when the trigger voltage
drops below +1/3 Vcc.
The output of the flip-flop is used to drive the discharge transistor and the output stage. A
high or positive flip-flop output turns on both the discharge transistor and the output stage. The
discharge transistor becomes conductive and behaves as a low resistance short circuit to ground. The
output stage behaves similarly. When the flip-flop output assumes the low or zero states reverse
action takes place i.e., the discharge transistor behaves as an open circuit or positive VCC state. Thus
EC 6412 LINEAR INTEGRATED CIRCUIT LAB
MANUAL
the operational state of the discharge transistor and the output stage depends on the voltage applied to
the threshold and the trigger input terminals.
Block Diagram of IC 555:
Pin Configuration:
Sink
(depending upon load) if the load is connected from Pin (3) to ground, and sinks zero current if the
load is connected between +VCC and Pin (3).
Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the potential of Pin
(4) is drives below 0.4V, the output is immediately forced to low state. The reset terminal enables
the timer over-ride command signals at Pin (2) of the IC.
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at which the
time comparators change state. A resistor connected from Pin (5) to ground can do the job.
Normally 0.01F capacitor is connected from Pin (5) to ground. This capacitor bypasses supply
noise and does not allow it affect the threshold voltages.
Pin (6) is the threshold terminal. In both astable as well as monostable modes, a capacitor is
connected from Pin (6) to ground. Pin (6) monitors the voltage across the capacitor when it charges
from the supply and forces the already high O/p to Low when the capacitor reaches +2/3 VCC.
Pin (7) is the discharge terminal. It presents an almost open circuit when the output is high and
allows the capacitor charge from the supply through an external resistor and presents an almost short
circuit when the output is low.
Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.
EC 6412 LINEAR INTEGRATED CIRCUIT LAB
MANUAL
Features of 555 IC
1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or
between pin 3 & VCC (supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +Vcc to avoid
false triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Specifications:
1. Operating temperature
SE 555-NE 555--
-55oC to 125oC
0o to 70oC
2. Supply voltage
+5V to +18V
3. Timing
Sec to Hours
4. Sink current
200mA
5. Temperature stability
Applications:
1. Monostable and Astable Multivibrators
2. dc-ac converters
3. Digital logic probes
4. Waveform generators
5. Analog frequency meters
6. Tachometers
EC 6412 LINEAR INTEGRATED CIRCUIT LAB
MANUAL
IC 565:
Description:
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561, 562,
564, 565, & 567 differ mainly in operating frequency range, power supply requirements and
frequency and bandwidth adjustment ranges. The device is available as 14 Pin DIP package and as
10-pin metal can package. Phase comparator or phase detector compare the frequency of input
signal fs with frequency of VCO output f o and it generates a signal which is function of difference
between the phase of input signal and phase of feedback signal which is basically a d.c voltage
mixed with high frequency noise. LPF remove high frequency noise voltage. Output is error
voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and mode is free
running mode. Application of control voltage shifts the output frequency of VCO from f o to f. On
application of error voltage, difference between fs & f tends to decrease and VCO is said to be
locked. While in locked condition, the PLL tracks the changes of frequency of input signal.
Pin Configuration:
10
Specifications:
1. Operating frequency range
6 to 12V
4. Input impedance
10 K typically
1mA typically
1.5%/V maximum
10mA typically
11
FL = 8 fout/V Hz
V = (+V) (-V)
Applications:
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector
IC 566:
Description:
The NE/SE 566 Function Generator is a voltage controlled oscillator of exceptional linearity
with buffered square wave and triangle wave outputs. The frequency of oscillation is determined by
an external resistor and capacitor and the voltage applied to the control terminal. The oscillator can
be programmed over a ten to one frequency range by proper selection of an external resistance and
modulated over a ten to one range by the control voltage with exceptional linearity.
12
Pin diagram:
Specifications:
Maximum operating Voltage ---
26V
Input voltage
---
Storage Temperature
---
Operating temperature
3V (P-P)
-65oC to + 150oC
---
Power dissipation
---
300mv
Applications:
13
1. Tone generators.
2. Frequency shift keying
3. FM Modulators
4. clock generators
5. signal generators
6. Function generator
IC723
Pin Configuration
Specifications of 723:
Power dissipation
1W
Input Voltage
9.5 to 40V
Output Voltage
2 to 37V
Output Current
Load regulation
0.6% Vo
Line regulation
0.5% Vo
14
15
ExNo:
DATE:
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER
AIM:
To design, construct and test inverting, Non-inverting and Differential amplifier using OPAMP.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
Apparatus
Resistor
Op-amp
Dual RPS
AFO
CRO/Voltmeter
Bread board
Connecting wires
Range
Quantity
IC741
15v
(0-15)v
-
A v =
Parameters
Assumed: R1
..
INVERTING AMPLIFIER:
RF
A v=
R1
NON-INVERTING AMPLIFIER:
R
A v =1+ F
R1
( )
DIFFERENTIAL AMPLIFIER:
R
A v= 2
R1
16
NON-INVERTING AMPLIFIER
INVERTING AMPLIFIER
DIFFERENTIAL AMPLIFIER
17
INVERTING AMPLIFIER:
S.NO
Vin(V)
Vo(V)
Gain= Vo / Vin
1
2
3
4
5
6
7
NON-INVERTING AMPLIFIER:
S.NO
Vin(V)
Vo(V)
Gain= Vo / Vin
18
1
2
3
4
5
6
7
DIFFERENTIAL AMPLIFIER:
S.NO
V1(V)
V2(V)
V0(V)
Gain = V0/(V1-V2)
1
2
3
4
5
6
7
19
RESULT:
AMPLIFIER TYPE
THEORITICAL GAIN
PRACTICAL GAIN
INVERTING AMPLIFIER
NON INVERTING AMPLIFIER
DIFFERENTIAL AMPLIFIER
ExNo:
DATE:
INTEGRATOR AND DIFFERENTIATOR
AIM:
To design, Construct and test the integrator and differentiator using OP AMP.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
Apparatus
Resistor
Capacitor
Op-amp
Dual RPS
AFO
CRO
Bread board
Connecting wires
DESIGN:
Parameters To be Given:
Range
.
Quantity
IC741
15v
-
fa =
R3=R1||R2
20
f b=
1
2 R1 C 2
DIFFERENTIATOR:
dv (t)
V o (t)
dt
f a=
1
2 R2 C 1
f b=
1
2 R1 C 1
R3=R1||R2
R2C2 = R1C1
CIRCUIT DIAGRAM
DIFFERENTIATOR
21
INTEGRATOR
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply the input signal using AFO.
3. Note the corresponding output waveforms.
4. Plot the graph.
TABULATION:
DIFFERENTIATOR
S.NO
INPUT
OUTPUT
22
Vin(V)
WAVEFORM
TIME (ms)
WAVEFORM
TIME (ms)
WAVEFORM
V0(V)
TIME (ms)
1
2
INTEGRATOR:
INPUT
S.NO
WAVEFORM
Vin(V)
OUTPUT
V0(V)
TIME (ms)
1
2
MODEL GRAPH:
INTEGRATOR
DIFFERENTIATOR
23
RESULT:
24
ExNo:
DATE:
INSTUMENTATION AMPLIFIER
AIM:
a) To design, construct and test the Instrumentation Amplifier using OP-AMP.
b) To simulate Instrumentation Amplifier using OP-AMP.
APPARATUS REQUIRED:
S.No
Apparatus
1.
Resistor
2.
Op-amp
Dual RPS
3.
Bread board
4.
Connecting wires
5.
Multimeter
6.
PC
7.
PSPICE Software
PROCEDURE FOR DESIGN:
Parameters to be given: Gain A=..
Range
Quantity
.IC741
15v
INSTRUMENTATION AMPLIFIER:
A . =3
R2
R1
CIRCUIT DIAGRAM
INSTRUMENTATION AMPLIFIER:
TABULATION:
S.NO
vdc1 (V)
vdc2 (V)
vout (V)
Gain=vout/(vdc1-vdc2)
1
2
3
4
5
6
SAMPLE CALCULATION FOR GAIN:
RESULT:
AMPLIFIER
INSTRUMENTATION AMPLIFIER
ExNo:
DATE:
THEORITICAL GAIN
PRACTICAL GAIN
Apparatus
Resistor
Capacitor
Op-amp
Dual RPS
AFO
CRO
Bread board
Connecting wires
PC
PSPICE Software
Range
Quantity
IC741
15v
-
H=
Parameters to be given: For LPF & HPF, F =F ...
L
For WBPF,
C=
..
F
Parameters to be assumed:
A v =3 ; =1.414 for second orderButterworth Filter ,
C=.
LOW PASS FILTER
1
F L=
2 RC
A v =1+
RF
R
( )
( )
Av =.
( )
f H=
1
2 R 1 C1
CIRCUIT DIAGRAM
LOW PASS FILTER
TABULATION:
S.NO
Freq( Hz)
Vo(V)
Gain=
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
Vo V
Vin V
Vin=
Gain in (DB)
=20log (Gain)
Freq( Hz)
Vo(V)
Gain=
V
Vo V
Vin V
Gain in (DB)
=20log (Gain)
S.N
O
Freq( Hz)
Vo(V)
Gain=
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
Vo V
Vin V
Gain in (DB)
=20log (Gain)
MODEL GRAPH:
LOW PASS FILTER
RESULT:
FILTER TYPE
LPF
HPF
WBPF
BANDWIDTH
ExNo:
DATE:
ASTABLE,MONOSTABLE MULTIVIBRATOR AND SCHIMITT TRIGGER USING OP-AMP
AIM:
a)
b)
To design, construct and test Astable, Monostable multivibrator and Schmitt trigger using OP AMP
To simulate Astable, Monostable multivibrator and Schmitt trigger using OP AMP
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Apparatus
Resistor
Capacitor
Op-amp
Dual RPS
AFO
CRO
Bread board
Connecting wires
PC
PSPICE Software
Range
.
Quantity
IC741
15v
-
T =2 R f C1 ln
R2
1+
( 1
) = R + R
1
MONOSTABLE MULTIVIBRATOR
T =0.69 RF C 1 =
R2
R1 + R2
R1= ,
= .
SCHIMITT TRIGGER
UTP=
R2
V V =V cc 1
R1 + R2 sat sat
LTP=
R2
R R
V sat R= 1 2
R 1+R 2
R 1+ R 2
ASTABLE MULTIVIBRATOR:
MONOSTABLE MULTIVIBRATOR:
SCHIMITT TRIGGER
TABULATION:
S.NO
ASTABLE MULTIVIBRATOR
V0(V)
TIME (ms)
Ton=
OUTPUT
1
2
S.NO
MONOSTABLE MULTIVIBRATOR
Toff=
Tcharging=
Tdischarging=
Voltage (V)
TIME (ms)
Ton=
TRIGGER INPUT
Toff=
Ton=
OUTPUT
Toff=
Tcharging=
S.NO
1
2
SCHIMITT TRIGGER
Voltage(V)
TIME (ms)
INPUT
OUTPUT
MODEL GRAPH:
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR
Amplitude
UTP
LTP
Ton=
Toff=
SCHIMITT TRIGGER
RESULT:
MULTIVIBRATOR TYPE
THEORITICAL TIME
PERIOD
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR
ExNo:
DATE:
RC PHASE SHIFT OSCILLATOR AND WEIN BRIDGE OSCILLATOR USING OP-AMP
AIM:
a) To design, construct and test the RC phase shift and Wein bridge oscillator using OP-AMP.
b) To simulate RC phase shift and Wein bridge oscillator using OP-AMP.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
Apparatus
Resistor
Capacitor
Op-amp
Dual RPS
CRO
Bread board
Connecting wires
PC
PSPICE Software
Range
.
Quantity
IC741
15v
-
1
R 2
A=
R 3=R 1 R 2
R1
2 RC 6
1
R2
A=1+
2 RC
R1
CIRCUIT DIAGRAM
RC PHASE SHIFT OSCILLATOR
TABULATION:
S.NO
OSCILLATOR TYPE
V0(V)
TIME (ms)
MODEL WAVEFORM:
RESULT:
OSCILLATOR TYPE
THEORITICAL FREQUENCY
PRACTICAL FREQUENCY
RC PHASE SHIFT
WEIN BRIDGE
ExNo:
DATE:
ASTABLE, MONOSTABLE MULTIVIBRATOR USING NE555 TIMER
AIM:
a) To design, construct and test the Astable and Monostable multivibrator using IC 555.
b) To simulate Astable and Monostable multivibrator using IC 555.
APPARATUS REQUIRED:
S.N
Apparatus
o
1.
Resistor
2.
Capacitor
3.
IC
4.
RPS
5.
AFO
6.
CRO
7.
Bread board
8.
Connecting wires
9.
PC
10. PSPICE Software
PROCEDURE FOR DESIGN:
Range
Quantity
.
IC555
(0-30)v
-
MONOSTABLE MULTIVIBRATOR
T =1.1 RC
MONOSTABLE MULTIVIBRATOR
R1= , f=
ASTABLE MULTIVIBRATOR:
PROCEDURE:
1. Make the connections as per the circuit diagram.
2. View the output waveforms through CRO.
3. Measure voltage across the capacitor and output terminal.
4. Plot the graph.
5. Compare the theoretical time period and practical time period
TABULATION:
S.NO
ASTABLE MULTIVIBRATOR
V0(V)
TIME (ms)
Ton=
OUTPUT
Toff=
Tcharging=
S.NO
MONOSTABLE MULTIVIBRATOR
Voltage (V)
TIME (ms)
Ton=
1
INPUT
OUTPUT
Toff=
Ton=
Toff=
Tcharging=
MODEL GRAPH:
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR
RESULT:
MULTIVIBRATOR TYPE
THEORITICAL TIME
PERIOD
PRACTICAL TIME
PERIOD
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR
ExNo:
DATE:
PLL CHARACTERISTICS AND ITS USE AS FREQUENCY MULTIPLIER
AIM:
To construct a PLL circuit and determine its characteristics and its use as frequency multiplier
APPARATUS REQUIRED:
S.No
Apparatus
Range
Quantity
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Resistor
Potentiometer
Capacitor
4-BitBinaryCounter
PLL IC
Transistor
Dual RPS
AFO
Bread board
Connecting wires
2,10,4.7 k
20k
1,10nF,1pF
IC7490
IC565
BC107
15v
-
1
1
1,1,1
1
1
1
-
PROCEDURE:
1. Make the Connections as per the circuit diagram.
2. Measure the free running frequency of VCO at pin 4, with the input signal Vin set equal to zero.
Compare it with the calculated value = 0.25/RtCt.
3. Now apply the input signal of 1V square wave at a 1 kHz to pin 2. Connect one
channel of
5. Now gradually decrease the input frequency till the PLL is again locked. This is the frequency f 3, the
upper end of the capture range. Keep on decreasing the input frequency until the loop is unlocked.
This frequency f4 gives the lower end of the lock in range.
6. The lock range fL = (f2-f4). Compare it with the calculated value of 7.8f 0/12. Also the capture range is
fC = (f3-f1).Compare it with the calculated values of
Capture range.
Fc= [fl/ (2) (3.6) (103)*C] 1/2
PROCEDURE:
TABULATION:
S.N
O
INPUT
Time(ms)
`
MODEL GRAPH
Frequency(Hz)
OUTPUT
Time (ms)
Frequency(Hz)
RESULT:
ExNo:
DATE:
DC POWER SUPPLY USING LM317 AND LM723
AIM:
To construct and test dc power supply using LM317 AND LM723.
APPARATUS REQUIRED:
S.No
1.
2.
2.
4.
5.
6.
7.
8.
Apparatus
Resistor
DRB
Capacitor
IC
Dual RPS
Multimeter
Bread board
Connecting wires
Range
IC723,IC317
LM723
Quantity
Vo=Vref
LM723
LM317
PROCEDURE:
LM723
1. Make the connections are made as per the circuit diagram.
2. Vary the Input dc Voltage using unregulated power supply and measure the corresponding output
voltage using multimeter
3. Plot line regulation characteristics for Vin vs. Vout.
LM317
1. Make the connections are made as per the circuit diagram.
2. Vary the Input dc Voltage using unregulated power supply and Measure the corresponding output
voltage using multimeter.
3. Plot line regulation characteristics for Vin vs. Vout.
4. Load resistance RL is varied and corresponding output voltage is measured using multimeter
5. Plot load regulation characteristics for RL vs. Vout.
TABULATION:
LM723
S.NO
LINE REGULATION
V in(volts)
Vo(volts)
LM317
LINE REGULATION
V in(volts)
Vo(volts)
LOAD REGULATION
RL ( ohms)
Vo(volts)
MODEL GRAPH:
LM723
LM317
RESULT:
REGULATOR TYPE
LM317
LM723
ExNo:
DATE:
SIMULATION OF DAC
AIM:
To simulate R-2R Ladder network Digital to Analog converter..
APPARATUS REQUIRED:
S.No
1.
2.
Apparatus
PC
PSPICE Software
CMOS DAC:
PRACTICAL
OUTPUTVOLTAGE
RESULT:
ExNo:
DATE:
SIMULATION OF ANALOG MULTIPLIER
AIM:
To simulate analog multiplier circuit.
APPARATUS REQUIRED:
S.No
1.
2.
Apparatus
PC
PSPICE Software
ANALOG MULTIPLIER:
RESULT:
ExNo:
DATE:
SIMULATION OF CMOS Inverter
AIM:
To simulate CMOS Inverter.
APPARATUS REQUIRED:
S.No
1.
2.
Apparatus
PC
PSPICE Software
CMOS Inverter:
RESULT:
ExNo:
DATE:
SIMULATION OF CMOS NAND
AIM:
To simulate CMOS NAND.
APPARATUS REQUIRED:
S.No
1.
2.
Apparatus
PC
PSPICE Software
CMOS NAND:
RESULT:
ExNo:
DATE:
SIMULATION OF CMOS NOR
AIM:
To simulate CMOS NOR.
APPARATUS REQUIRED:
S.No
1.
2.
Apparatus
PC
PSPICE Software
CMOS NOR:
RESULT:
ExNo:
Date:
STUDY OF SMPS
AIM :
To study the operation of switch mode power supply.
The series pass transistor Q acts as a switch i.e. it operates in saturation when conducting and in cutoff when it is not conducting
The resistors R1 and R2 form a resistive feedback network. The feedback voltage is given by
Vfb=
R2V 0
R 1+ R 2
This feedback voltage is applied at the non-inverting (+) terminal of the error amplifier. A reference
voltage which represents the desired value of output voltage is applied at the inverting (-) terminal of the
error amplifier.
The difference between feedback voltage and the reference voltage is called as error. The output voltage of
the error amplifier is a dc control voltage proportional to the error.
The dc control voltage is compared with the triangle waveform generated by the triangular wave generation.
The comparator output is a square waveform which is used to turn on and off transistor Q
The rectangular waveform at the emitter of Q is filtered by the LC filter to produce a pure ripple free
dc voltage at the rectangular output. Due to high frequency of operation, the size of LC components is small.
If the output Vo reduces below the regulated value, that the feedback voltage decreases. The output
voltage of error amplifier will decrease. This will increase the on time of the pulses at the output of the
comparator.
Thus ON time ton increases to increase duty cycle and hence output voltage will increase, thus
regulation will be practically achieved.
TYPES OF SWITCHING REGULATOR:
The switching regulators are available in three basic configuration:
OPERATION:
Q1 is a power transistor which is turned ON and OFF by the rectangular pulses applied at its base
DFW is a freewheeling diode, while L and C2 form a low pass filter. Vin is the unregulated dc power supply.
The average output voltage is varied by changing either the duty cycle or frequency. In most application the
variation of duty cycle is preferred to variation in frequency.
The expression for average output voltage in terms of duty cycle is given by
Vo= D Vin
The duty cycle D can be varied between 0 and 1. Therefore average output voltage V o is less than or equal
to Vin. This circuit is called as the switching buck regulator or a step down switching regulator.
STEP UP (or) BOOST SWITCHING REGULATOR:
The basic Boost switching regulator is shown
OPERATION:
The operation can be divided into two modes:
i)
Mode I (Q on)
ii)
It is possible to obtain an output voltage higher than supply voltage so the circuit is called Boost switching
regulator.
The output voltage can be varied by varying the duty cycle of the output waveform. The output voltage is
approximately given by
Vo
Vin
(1D)
Where D is the duty cycle. This equation shows that the output voltage is higher than the input voltage for
all the values of D.
BUCK BOOST REGULATOR:
The buck boost switching regulator is a non-isolated type converter which is also known as inverting
regulator.
The buck-boost regulator is a form of flyback type converter whose operation is very similar to a boost
regulator.
OPERATION:
The operation can be divided into three modes
i)
When Q1 is turned on, the supply voltage V gets connected across the inductance L. the inductance
current starts increasing linearly. Diode D1 is reverse biased during this mode. The inductance will store
energy during this mode of operation.
ii)
As soon as the transistor Q1 is turned off, the current through L is interrupted abruptly.
A negative voltage is induced into L which will forward bias diode D1
The load current starts flowing through D1, L is shown in figure below
Note that this current is negative. The capacitor charges with its lower plate positive.
This mode comes to an end when the current through diode reduces to zero.
iii)
When all the devices are in the off state, the capacitor C2 will discharge through the load in this mode of
operation. This circuit is called as inverting regulator as the output voltage is negative.
This regulator is used in those applications where output voltage greater than the input voltage with a
negative polarity is required.
The waveform shown in figure are for the discontinuous conduction. The conduction can be made
continuous by increasing the duty cycle above 50%.
But with a duty cycle value above 50% the stability and regulation problems will have to be faced. The
buck boost regulator has all the drawbacks of the boost regulator.
Advantages:
Low power dissipation in the series pass transistor as it operates as a switch and not in the active region.
High efficiency (up to 95%) due to reduced powet dissipation in the transistor.
Small size: this is due to the smaller size of L and C at higher operating frequencies and need of smaller heat
sink for the series pass transistor.
Higher power handling capacity.
Disadvantage:
Increased switching loss in the series pass transistor due to high frequency switching.
Radio frequency interference (RFI) to the neighbouring electronics circuits.
There is no isolation between input and output.
The load requires separate protection circuitry.
The transient response is slow as compared to the linear power supplies.
Ripple content in the output is higher than that for a linear power supply.
Load regulation is poor as compared to the linear regulators.
RESULT:
PIN DIAGRAM
OP-AMP
A741C
TIMER
NE555
BINARY COUNTER
IC 7490
GENERAL PURPOSE
VOLTAGE REGULATOR
LM723
ADJUSTABLE VOLTAGE
REGULATOR
LM317
Viva-voice Questions
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