A.

Fahim

Clock Generators for SOC Processors

Circuits and Architectures

Explores problems in the design of fully-integrated frequency

synthesizers suitable for system-on-a-chip (SOC) processors
Comprehensive coverage includes summary chapters on circuit
theory as well as feedback control theory
Discussion includes PLL analysis using continuous-time as well
as discrete-time models, linear and nonlinear effects of PLL
performance, and detailed analysis of locking behavior
Includes numerous real world applications as well as useful rules-ofthumb for design at the system, architectural and circuit levels

2005

Printed book
Hardcover
valid until April30,2015
129,99 | 113.00 | $169.00
*139,09(D) | 142,99(A) | CHF167.00

eBook
Available from your library or
springer.com/shop

MyCopy
Printed eBook for just
| $ 24.99
springer.com/mycopy

Current literature is filled with textbooks and research papers describing frequency
synthesizers from a front-end wireless transceiver perspective. The emphasis has
historically been on evaluating the frequency synthesizers performance in the frequency
domain, i.e. in terms of phase noise and spurious signals. As microprocessor frequency
surges, the need to understand digital requirements for low-jitter and the design of lowjitter frequency synthesizers and clock generators becomes increasingly important.
Clock Generators for SOC Processors is dedicated to the time-domain (i.e. jitter) design and
analysis of frequency sythesizers and clock generators for microprocessor applications.
In the past, such explanations have been scattered, and have not, to this date, been
gathered into one comprehensive textbook.

Clock Generators for SOC Processorsalso focuses on the CMOS IC implementation of such
synthesizers. An entire chapter is dedicated to low-voltage mixed-signal integrated
circuit design in deep submicron CMOS technologies. Subsequent chapters discuss
the design and analysis of the most common frequency synthesizer, the phase-locked
loop (PLL), as well as state-of-the-art innovative architectures suitable for system-ona-chip (SOC) processors. Design for Testability (DFT) is also discussed in the context of
frequency synthesizers in SOC processors. The book concludes by discussing some of
the most common issues that arise in clock interfacing, clock distribution, and accurate
delay generation through delay-locked loops (DLLs) as they apply to SOC processors. Such
issues mainly arise from having to communicate data and clock signals across multiple
clock and power domains.Clock Generators for SOC Processorsprovides numerous real
world applications, as well as practical rules-of-thumb for modern designers to use at the
system, architectural,and circuit level.

Order online at springer.com or for the Americas call (toll free) 1-800-SPRINGER or email us at:
customerservice@springer.com. For outside the Americas call +49 (0) 6221-345-4301 or email us at:
customerservice@springer.com.
The first price and the and $ price are net prices, subject to local VAT. Prices indicated with * include VAT for books; the (D) includes 7% for
Germany, the (A) includes 10% for Austria. Prices indicated with ** include VAT for electronic products; 19% for Germany, 20% for Austria. All prices
exclusive of carriage charges. Prices and other details are subject to change without notice. All errors and omissions excepted.