.

St. MARTINS ENGINEERING COLLEGE

(Accredited by NBA, Affiliated to JNTUH & Approved by AICTE, ISO 9001:2000 Institute)

Dhulapally, Secunderabad ,A.P, INDIA-500 014.

DEPARTMENT OF
ELECTRONICS &
COMMUNICATION ENGINEERING
IC APPLICATIONS AND HDL
SIMULATION
LAB MANUAL
Academic year 2015-16
Prepared By

Approved By

M. Vijaya Lakshmi
Assoc. Professor.

K. Yadaiah
Assoc.Prof.&HOD

Principal
Dr. C. VENKATARAMANA REDDY

LIST OF THE EXPERIMENTS

NAME OF THE EXPERIMENT

S.No

Pg.No

PART-I
INTRODUCTION
1

Adder, Subtractor, Comparator using IC 741 Op-Amp.

Integrator and Differentiator using IC741 Op-Amp.

Active Low Pass & High Pass Butterworth (First Order).

IC 741 Waveform Generators-Sine, Square wave and Triangular waves

IC 555 Timer Monostable and Astable Multivibrator Circuits

Schmitt trigger circuits using IC741

IC 565-PLL Applications

Voltage Regulator using IC 723, three terminal Voltage Regulators7825,7809,7912.

PART-II

HDL code to realize all the logic gates

10

Design of 2-to-4 decoder

11

Design of 8-to-3 encoder (without and with priority)

12

Design of 8-to-1 multiplexer

13

Design of 4 bit binary to gray converter

14

Design of 4bit comparator.

15

Design of Full adder using 3 modeling styles

16

Design of flip flops: SR, D, JK, T

Design of 4-bit binary, BCD counters.(Synchronous/Asynchronous reset)

17
18

Finite State Machine Design

Experiment No.1
ADDER, SUBTRACTOR, COMPARATOR USING IC 741 OP-AMP

AI
M:

To study the applications of IC 741 as adder, subtractor, comparator.

APPARAT
US:
1.IC 741
2.Resistors (1K)4
3.Function generator
4.Regulated power supply
5.IC bread board trainer
6.CRO
7.Patch cards and CRO probes
CI
R
C
UI
T
DI
A
G
R
A
M
Ad
de
r:

Subtractor:

Comparator:

THEORY:
ADDER:
Op-Amp may be used to design a circuit whose output is the sum of several input signals
such as circuit is called a summing amplifier or summer. We can obtain either inverting or noninverting summer.
Thecircuitdiagramsshowsatwoinputinvertingsummingamplifier.Ithastwo input voltages
V1andV2, two input resistors R1, R2and a feedback resistor Rf.
Assuming that op-amp is in ideal conditions and input bias current is as summed to be
zero, there is no voltage drop across the resistor comp and hence the noninverting input terminal
is at ground potential.
By taking nodal equations.
V1/R1+V2/R2+V0/Rf=0
V0=-[(Rf/R1) V1+(Rf/R2) V2]
And hereR1=R2=Rf=1K
V0=-(V1+V2)
Thus output is inverted and sum of input.

SUBTRACTOR:
A basic differential amplifier can be used as a subtractor. I the two input signals V1and
V2and two input resistances R1andR2 and a feedback resistor Rf.The input signals scaled to the
desired values by selecting appropriate values for the external resistors.
From the figure, the output voltage of the differential amplifier with a gain of1 is
V0=-R/Rf(V2-V1)
V0=V1-V2.
Also R1=R2=Rf=1K.
Thus, the output voltage V0 is equal to the voltage V1 applied to then on inverting
terminal minus voltage V2applied to inverting terminal.
Hence the circuit is sub tractor.
COMPARATOR:
A comparator is a circuit which compares a signal voltage applied atoneinputofanopampwithaknownreferencevoltageattheotherinput.Itisbasicallyanopen loop op-amp with output
Vsat as in the ideal transfer characteristics.
ItisclearthatthechangeintheoutputstatetakesplacewithanincrementininputVi
of
only2mv.Thisistheuncertaintyregionwhereoutputcannotbedirectly defined There are basically 2
types of comparators.
1. Non inverting comparator and.
2. Inverting comparator.
The applications of comparator are zero crossing detector ,window detector, time marker
generator and phase meter.
OBSERVATIONS:
ADDER:
V1(volts)

V2(volts)

Theoretical
V0=-(V1+V2)

Practical
V0 =-(V1+V2)

SUBTRACTOR:
V1(volts)

V2(volts)

Theoretical
V0=(V1-V2)

Practical
V0 =(V1-V2)

COMPARATOR:
Voltage input

Vref

Observed
amplitude

MODEL GRAPH:

PROCEDURE:
ADDER:
1.connections are made as per the circuit diagram.
2.Apply input voltage1) V1=5v,V2=2v
2) V1=5v,V2=5v
3) V1=5v,V2=7v.
3.Using Millimeter measure the dc output voltage atthe output terminal.
4.For different values ofV1and V2measure the output voltage.

square

wave

SUBTRACTOR:
1.Connectionsaremade as per the circuit diagram.
2.Apply input voltage1) V1=5v,V2=2v
2) V1=5v,V2=5v
3) V1=5v,V2=7v.
3.Using multi meter measure the dc output voltage at the output terminal.
4.For different values of V1and V2measure the output voltage.
COMPARATOR:
1.Connections are made as per the circuit diagram.
2.Select the sine wave of10V peak to peak ,1K Hz frequency.
3.Apply the reference voltage 2V and trace the input and output wave forms.
4. Superimpose input and output waveforms and measure sine wave amplitude with
reference to Vref.
5.Repeatsteps3and 4with referencevoltagesas2V,4V,-2V,-4Vandobserve the
waveforms.
6.Replace sine wave input with 5V dc voltage and Vref=0V.
7.Observe dc voltage at output using CRO.
8.Slowly increase Vrefvoltage and observe the change in saturation voltage.
PRECAUTIONS:
1.Make null adjustment before applying the input signal.
2.Maintain proper Vcc levels.
RESULT:

Experiment No.2
OP-AMP 741 AS DIFFRENTIATOR AND INTEGRATOR
AIM:
To design and test an op-amp differentiator and integrator
EQUIPMENTS AND COMPONENTS:
APPARATUS:
1. DC power supply 2. CRO
3. Bread Board
4. FunctionGenerator-

1 No.
1 No.
1 No.
1 No.

COMPONENTS:
1. 15 k Resistor 2 No.
2. 820 Resistor 1 No.
3. 1.5 k Resistor 1 No.
4 0.01 F Capacitor 2 No
5 0.5 nF Capacitor 1 No
5
IC741 - 1
No.
THEORY
The operational amplifier can used in many applications. Itcanbeusedas differentiator
and integrator. Indifferentiator the circuit performs the mathematical operation of
differentiation that is the output waveform is the derivative of the input
waveformforgooddifferentiation, onemustensurethathetimeperiodoftheinput signal is
larger than or equal to RfC1.the practical differentiatoreliminates the problemof
instabilityandhighfrequencynoise.
CIRCUITDIAGRAM:

PROCEDURE:
1connectthedifferentiatorcircuitasshowninfig1.adjustthesignalgeneratorto producea5
voltpeaksinewaveat100 Hz.
2observeinputViandVosimultaneouslyontheoscilloscopemeasureandrecordthe
peakvalueofVo andthephaseangleofVowithrespecttoVi.
3.Repeatstep2whileincreasingthe frequencyofthe inputsignal.Find the maximum
frequencyatwhichcircuit offersdifferentiation.Compareitwiththecalculatedvalue of fa
Observe&sketchtheinputandoutputfor squarewave.
4.Connecttheintegratorcircuit
showninFig2.Setthefunctiongeneratortoproduce
asquarewaveof1Vpeak-to-peakamplitudeat500Hz.Viewsimultaneouslyoutput
VoandVi.
5.Slowlyadjusttheinputfrequencyuntiltheoutputisgoodtriangularwaveform.
Measuretheamplitudeandfrequencyof theinputandoutputwaveforms.
6.Verifythefollowingrelationship
betweenR1Cfandinputfrequencyforgood
integrationf>fa&T<R1C1
WhereR1Cfisthetimeconstant
7.Nowsetthefunctiongeneratortoasinewaveof1Vpeak-to-peakandfrequency
500Hz.
Adjustthefrequencyoftheinputuntiltheoutputisanegativegoingcosine
wave.Measurethefrequencyandamplitudeof theinputandoutputwaveforms.
OBSERVATIONS:
1. Thetimeperiodandamplitudeof theoutputwaveformof differentiatorcircuit
2. Thetimeperiodandamplitudeof theintegratorwaveform
CALCULATIONS:
Design adifferentiatortodifferentiateaninputsignalthatvariesinfrequencyfrom10
Hz to 1 kHz.
1
f
2RfC1
fa=1 kHz, thehighestfrequencyof theinputsignal
LetC1=0.01 F,
ThenRf=15.9 k
ThereforechooseRf=15.0 k
1
f
2R1C1
Choose:fb=20x fa=20 KHz
HenceR1=795
ThereforechooseR1=820
SinceR1C1=RfCf(compensatedattenuator)
Cf=0.54 nF
ThereforechooseCf=0.5nF
Integrator:Designanintegratorthatintegratesasignalwhose frequenciesare
between1 KHz and10 KHz

1
2R1Cf

thefrequencyatwhichthegainis0 dB.
1
fa
2RfCf
fa: Gainlimitingfrequency,
Thecircuitactsas integratorfor frequenciesbetweenfaandfb
Generallyfa<fb[ Ref.Frequencyresponse of theintegrator]
Thereforechoosefa=1KHz
Fb=10 KHz
Let
Cf=0.01 F
ThereforeR1=1.59k
Choose R1=1.5 K
Rf=15 K
GRAPH:
Differentiator

Integrator

1V

-{).318V

(a
)

v
I

tV-------------------------t

1------._,

V;

+1v
+0.5
V

1V
(C
)

RESULT:

Differentiator
1
f
2R1Cf
T>Rf C1=
Integrator
1
fa
2RfCf
T=

Experiment No.3

ACTIVE FILTER APPLICATIONS-LPF, HPF [ FIRSTORDER ]

AI
M:

To study Op-Amp as firsorder LPF and firstorder HPF and to obtain

frequency
response.
APPARATUS:
1. IC 741.
2. Resistors (10K--2, 560, 330
3. Capacitors(0.1)
4. Bread board trainer
5. CRO
6. Function generator
7. connecting wires
8. Patch cards.
CI
RC
UI
T
DI
AG
RA
M:
(a)
LP
F

(a)HPF

THEORY:
LOWPASS FILTER:
ThefirstorderlowpassbutterworthfilterusesanRcnetworkforfiltering.The
opampisusedinthenoninvertingconfiguration,henceitdoesnotloaddowntheRC network. Resistor R1
and R2 determine the gain ofthefilter.
V0/Vin=Af/(1+jf/fh)
Af=1 +Rf/R1=pass band gain offilter .
F=frequency ofthe input signal.
Fh= 1/2RC =High cutt off frequency of filter .
V0/Vin =Gain ofthe filter as afunctionoffrequency
ThegainmagnitudeandphaseangleequationsoftheLPFthecanbeobtained
V0/Vin into its equivalent polar form as follows
2
|V0/Vin|=Af/(1+(f/fl) )
= - tan-1(f/fh)
Whereisthephaseangleindegrees.TheoperationoftheLPFcanbeverified
from the gain magnitude equation.

by

converting

1. Atvery low frequencies i.e f<fh,

|V0/Vin|=Af.
2. Atf=fh,|V0/Vin|=Af/2.
3. Atf>fh,|V0/Vin|<Af.
HIGH PASS FILTER:
High pass filters are often formed simply
by interchanging frequency.
DeterminingresistorsandcapacitorsinLPFsthatis,afirstorderHPFisformedfroma
firstorderLPFbyinterchangingcomponentsRandCfigure.Showsafirstorder
butterworthHpFwithalowercutoff frequencyofFl.Thisisthefrequencyatwhich magnitude ofthe
gain is 0.707times its pass band value. Obviously all frequencies,with the highest frequency
determinate by the closed loop band width ofop-amp.
For the firstorderHPF ,the output voltage is
V0 =[1+ Rf/R1] j2RCVin/(1- j2fRC)
V0/Vin=Af[j(f/fl)/(1=j(f/fl)]
WhereAf+ Rf/R1a pass band gain ofthe filter.
F=frequency ofinput signal.
Fl=1/2RC = lower cutt off frequency
Hence, the magnitude ofthe voltage gain is
2
|V0/Vin|=Af(f/fl)/1+(f/f1) .
Since,HPFsareformedfromLPFssimplybyinterchangingRsandCs.The
frequency scaling procedures oftheLPFsare also applicable toHPFs.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply sine wave ofamplitude 4Vp-ptothe non inverting input terminal.
3. Values the input signal frequency.
4. Note down the corresponding output voltage.
5. Calculate gain in db.
6. Tabulate the values.
7. Plot a graph between frequency and gain.
8. Identify stop band and pass band from the graph.

design

and

OBSERVATIONS:
Low Pass Filter
Frequency(Hz)

V0(V)

Gain
in
20log(V0/Vi)

db=

V0(V)

Gain
in
20log(V0/Vi)

db=

High Pass Filter

Frequency(Hz)

MODEL GRAPH:
High Pass Filter

Low Pass Filter

PRECAUTIONS:
1.Make null adjustment before applying the input signal.
2.Maintain proper Vcclevels.
RESULT:

Experiment No.4

FUNCTION GENERATOR USING OP AMPS

AI
M: Togeneratetriangularandsquarewaveformsandtodeterminethetimeperiod
ofthe waveforms.
APPARATUS:
1. OpAmp IC
741 2
Nos
2.Bread board IC trainer
3.Capacitor 0.1F
4.Zener diodes (6.2V)2 Nos
5.Resistors10K, 150K1.5K, 1M, 8.2KCRO
6.Patch cards
7.Connecting wires
CIRCUIT DIAGRAM:

THEORY:
Thefunctiongeneratorconsistsof acomparatorU1andanintegratorA2.The comparator U2
compares
the
voltage
atpointPcontinuously
with
the
inverting
input
i.e.,
atzerovolts.WhenvoltageatPgoesslightlybeloworabovezerovolts,theoutputof U1 is atthe negative
or positive saturation level, respectively.
ToillustratethecircuitoperationletussettheoutputofU1atpositivesaturation
+Vsat(approximately+Vcc).
This+VsatisaninputtotheintegratorU2.Theoutputof
U2,thereforewillbea
negative
goingramp.Thus,one
end
ofthevoltagedivider
R2-R3
isthepositivesaturationvoltage+VastofU1andtheotheristhenegativegoingramp
ofU2.
WhenthenegativegoingrampattainsacertainvalueVramp,pointpisslightlybelowzerovalts;
hencetheoutputofU1willswitchfrompositivesaturationtonegative saturationVsat(approximately
Vcc). ThismeansthattheoutputofU2willnowstop goingnegativelyandwillbegintogopositively.The
outputofU2willcontinue
to
increaseuntilitreaches+Vramp.AtthistimethepointPisslightlyabovezerovolts.
Thesequencethenrepeats.Thefrequenciesofthesquareareafunctionofthed.csupplyvoltage.Desireda
mplitudecanbeobtained by usingapproximatezenersatthe output ofU1.
THEORETICAL VALUES:
Time period, T=4R5C (R3+R4)/(R1+R2) =0.492 msec.
Positive peak ramp =VzR5/(R1+R2) =0.05 volts.
PRACTICAL VALUES:
Timeperiodsoftriangular wave=
Time periods ofsquare wave=
Positive peak ramp=
Voltage ofsquare wave=
PROCEDURE:
1. The circuit is connected as shown in the figure.
2. TheoutputofthecomparatorU1isconnectedtotheCROthroughchennal1,to generate a square
wave.
3. TheoutputofthecomparatorU2isconnectedtotheCROthroughchennal2,to generate a
triangular wave.
4. Thetimeperiodsofthesquarewaveandtriangularwavesarenotedandtheyare found tobe equal.

MODEL GRAPH:

PRECAUTIONS:
1.Make null adjustment before applying the input signal.
2.Maintain proper Vcclevels.
RESULT:

Experiment No.5

IC 555 Timer Monostable and Astable Multivibrator Circuits

AI
M:
timer
.

Toconstructandstudytheoperationofamonostablemultivibratorusing555I
C

APPARATUS:
1. 555 IC timer
2. Capacitors (0.1F,0.01F)
3. Resistors 10K
4. Bread board IC trainer
5. CRO
6. Connecting wires and Patchcards
THEORY:
Monostablemultivibratorisalsoknownastriangularwavegenerator.Ithaso
nestableandonequasistablestate.Thecircuitisusefulforgenerating
single
outputpulseoftimedurationin response toatriggeringsignal. The width of the
output
pulse
dependsonlyonexternalcomponentsconnectedtotheopamp.Thediodegives
a
negativetriggeringpulse.Whentheoutputis+Vsat,
adiodeclampsthecapacitor
voltage
to0.7V.
then,
anegativegoingtriggeringimpulsemagnitudeVipassing through RC and the
negative triggering pulse is applied tothe positive terminal.
Letusassumethatthecircuitisinstablestate.TheoutputV0iisat+Vsat.The
diodeD1conductsandVcthevoltageacrossthecapacitorCgetsclampedto0.7V.th
evoltageatthepositiveinputterminalthroughR1R2potentiometerdivideris+Vsat
. Now,ifanegativetriggerofmagnitudeViisappliedtothepositiveterminalsothat
the effectivesignalislessthan0.7V.theoutputoftheOp-Ampwillswitchfrom+Vsat
to
Vsat.
Thediodewillnowgetreversebiasedandthecapacitorstartschargingexponentiallyt
oVsat.WhenthecapacitorchargeVcbecomesslightlymorenegative thanVsat,
theoutputoftheopampswitchesbackto+Vsat.ThecapacitorCnowstartschargingto+Vsatthrough
R until Vcis 0.7V.

t
/
R
C
V0=Vf +(Vi-Vf)
.
=R2/(R1+R2)
IfVsat>>Vpand R1=R2and =0.5,
Then, T=0.69RC.

CIRCUIT DIAGRAM:

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Negative triggering is applied atthe terminal 2.
3. The output voltage is measured by connecting the channel-1 at pin3.
4. Theoutputvoltageacrosscapacitorismeasuredbyconnectingthechannel-2at the point P.
5. TheoreticallythetimeperiodiscalculatedbyT=1.1R1C1
whereR1 =10K
C1=0.1F.
6. Practically thecharginganddischargingtimersaremeasuredandtheoretical
valueoftime period is measured with practical value

MODELGRAPH:

PRECAUTIONS:
1.Make the null adjustment before applying the inputsignal.
2.Maintain proper vcc levels.

RESULT:

IC 555 TIMER-ASTABLECIRCUIT
AI
M: Toconstruct and study the operation ofAstablemultivibrator using
555 timer
APPARATUS:
1.IC 555 Timer
2.Resistors (10 K,4.7 K)
3.Diode (IN 4007)
4.Capacitors (0.1F,0.01F)
5.CRO
6.Patch cards
7.CRO Probes
8.Connecting wires
CIRCUIT DIAGRAM:

THEORY:
A simple OPAMP astable multivibrator is also called square wave generator and free
running oscillator .The principle for the generation of square wave output is to force an OP_AMP
to operate in the saturation region =R2/(R1+R2) of the output is feedback to input. The output
isalsofeedbacktothenegativeinputterminalafterintegratingbymeansofaRCLPFwheneverthenegative
inputjustexceedsVref,switching takes placeresultinginasquarewaveoutput.Inastablemultivibrator
both states are quasi stable states.
When the output is +Vsat, the capacitor is now starts charging towards +Vsat through
resistance R the voltage is held at +Vsat. This condition continuous until the charge on C just
exceedVsat.Then
the
capacitor
begins
to
dischargetowards
Vsat.Thenthecapacitorchargesmoreand
more
negatively
untilitsvoltagejust
Vsat.Thefrequencyisdeterminedbythetimeittakesthecapacitortocharge from Vsat and +Vsat
-t/RC
Vc(t)=Vf+(Vi-Vf)e
-t/RC
Vc(t)=Vsat-Vsat(1+)e
We getT1=RC ln((1+)/(1-))
T=2T1=2 RC ln ((1+)/(1-)),Vo(p-p)=2Vsat
PROCEDURE:
1.Connections are made as per the circuit diagram.
2.Pins 4 and 8 are shorted and connected topower supply Vcc(+5V)
3.Between pins 8 and 7 resistor R1 of10K is connected and between
7 and 6 resistor
R2 of4.7K is connected. Pins 2 and 6 short circuited.
4.Inbetween pins 1 and 5 a Capacitor of0.01F is connected.
5.Theout put is connected across the pin 3 and GND.
6. In between pins 6 and GND a Capacitor of 0.1F is connected.
7.Theoreticallywith out diode charging time Tcis given by
Tc=0.69(R1+R2) C1,
Discharging time Tdis given by Td=0.69R2C1
The frequency fis given by
f=1.45/(R1+2R2)C1
%of Duty cycle is (Tc/(Tc+Td))*100
8.PracticallyTdandTcare measured and wave forms are noted and theoretical
Values are verified with practical values
9.Connect diode between pins 7 and 2.
10. Theoretically with diode connected
charging time is given by Tc=0.69R1C1
Discharging time is given by Td=0.69R2C1
11. Practically TdandTcare noted and verified with theoretical values

OBSERVATIONS:
With diode
Theoretical

Practical

Theoretical

without diode
Practical

MODEL GRAPH:

PRECAUTIONS:
1.Make null adjustment before applying the input signal.
2.Maintain proper Vcclevels.
RESULT:

Experiment No.6

SCHMIT TRIGGER USING IC 741

Aim:
To construct the Schmitt trigger using Ic 741
Apparatus:
1. 741 IC
2. Function Generator
3. Bread board
4. Resistors
5. Power supply
6. Connection wire
Circuit Diagram

Experiment No.7
IC 565-PLL Applications
AIM:
1. Tostudytheoperationof NE565 PLL
2. Touse NE565 as amultiplier
EQUIPMENTSANDCOMPONENTS:
APPARATUS
1. DC power supply 2. CRO
3. BreadBoard
4. FunctionGenerator-

1 No.
1 No.
1 No.
1 No.

COMPONENTS:
1. 6.8 k Resistor 1 No.
2. 0.1 F Capacitor 1 No
5. 0.001 F Capacitor 2 Nos
6. IC565 - 1 No.
THEORY:
The565isavailableasa14-pinDIPpackage.Itisproducedbysignaticcorporation.
Theoutputfrequencyof theVCO canbe rewrittenas
0.25
fo
Hz
R TC T
Where RT and CTare the external resistor and capacitor connected to pin8 and pin9. A
value between 2k and 20k is recommended for RT .The VCO free running frequency
is adjusted with RTand CT to be at the centre for the input frequency range.

CIRCUITDIAGRAM:

PROCEDURE:
i. Connectthecircuitusingthecomponentvaluesas shown inthefigure
ii .MeasurethefreerunningfrequencyofVCO at pin4 withtheinputsignalVinset=
zero.Compareitwiththecalculatedvalue=0.25/RTCT
iii. Now apply the input signal of 1Vpp squarewaveata1kHz topin2
iv. Connect1 channelof thescopetopin2 anddisplaythissignalon thescope

v .GraduallyincreasetheinputfrequencytillthePLLislockedtotheinputfrequency. This
frequency f1 gives the lower ends of the capture range. Go on increase the input
frequency, till PLL tracks the input signal, say to a frequency f2.This frequency f2
gives the upper end of the lock range. If the input frequency is increased further the
loop will get unlocked.
vi. Now graduallydecreasetheinputfrequencytillthePLLisagainlocked.Thisis the
frequency f3, the upper end of the capture range .Keep on decreasing the input
frequency until the loop is unlocked. This frequency f4 gives the lower end of the
lock range
7.8fo
vii. The lock range fL=(f2 f4)
12
compareitwiththecalculatedvalueof
Also thecapturerangeis
fc=(f3 f1).
Compareitwiththecalculatedvalueof capturerange.
fc

fL

1/2

(2 )(3.6)
3
(10 )xC)
viii. To use PLL as a multiplie5r,makeconnectionsas show in fig. The
circuit uses a 4-bitbinarycounter7490 usedasadivide-by-5circuit.
ix.Settheinputsignalat1Vpp squarewaveat500Hz
x..Vary the VCO
frequencybyadjustingthe20KpotentiometertillthePLLis locked.
Measure the output frequency
xi. Repeatstep9 and10 for input frequency of 1kHzand1.5kHz.
OBSERVATIONS:
fo =
fL=
fC=
CALCULATIONS:
fL=(f2
f4) =
fc=(f3
f1) =

7.8fo
12
f
L

(2 )(3.6)
3
(10 )xC)

1/2

GRA
PH:

RESULT:
fo=
fL=
fC=

Experiment No.8

Voltage Regulator using IC 723, three terminal Voltage Regulators7825,7809,7912

VOLTAGE REGULATORUSING IC 723
AI
M:

Toplot the regulation characteristics ofthegiven IC LM 723.

APPARATUS:
1. Bread board
2. IC LM 723
3. Resistors(7.8K ,3.9K )
4. RPS
5. DRB
6. Capacitors 100F
7. Patch cards
8. Connecting wires

CIRCUIT DIAGRAM:

THEORY:
Avoltageregulatorisacircuitthatsuppliesconstantvoltageregardlessof changes inload
currents. Except
for
the
switching
regulators, all other types
of
regulatorsarecalledlinearregulators.ICLM723isgeneralpurposeregulator.The
inputvoltageofthis723ICis40Vmaximum.Outputvoltageadjustablefrom2Vto30
V. 150mAoutput current external pass transistor. Out putcurrents in excess of
10Amperepossiblebyaddingexternaltransistors.Itcan
beusedaseitheralinearora
switchingregulator.ThevariationofDCoutputvoltageasafunctionofDCloadcurrent
is
called
regulation.
% Regulation =[(Vnl-Vfl)/Vfl]*100
PROCEDURE:
(1).LINE REGULATION
1.Connections are made as per the circuit diagram
2.Power supply is connected to12 and 7 terminals
3.Volt meter is connected to10 and 7 terminals
4.Byincreasing the input voltage corresponding volt meter reading is noted.
(2).LOAD REGULATION
1.Connect the load tothe terminals 10 and GND.
2.Keep the input voltage constant atwhich line regulation is obtained
3.The maximum load value is calculated from IC ratings.
4.Now,wedecreasetheloadresistanceandnotedownthecorresponding
valu
e

Ofthe output in volt meter.

5.Plot the graph forload verses load regulation.

OBSERVATIONS:
(1).LINEREGULATION:
Vnl=
Line voltage (V)

Outputvoltage(V)

(2).LOAD REGULATION:
Regulated
output(V)

Load
current(mA)

Load
resistance(K)

Load
regulation

% REGULATION=[(Vnl-Vfl)/Vfl]*100
MODEL GRAPH:

PRECAUTIONS:
1.Whiletakingthereadingsofregulatedoutputvoltageloadregulation ,keep the input voltage
constant at15V.
2.Donotincrease the input voltage morethan 30 Vwhile taking thereadingforno load
condition?
RESULT:

Three Terminal Voltage Regulators (7805, 7809 And 7912)

AIM:
To verify the operation of three terminal fixed voltage regulators 7805, 7809, 7912
and also to find out their line and load regulation.
APPARATUS:
S.No.
Name of the
Range
Quantity
component
1.
7805
-1
2.
7809
-1
3.
7912
-1
4.
Capacitors
0.33f
1
0.1f
1
5.
Multimeter
(01
30)v
6.
Power
1
Supply
CIRCUIT DIAGRAM:

THEORY:
Three terminal voltage regulators have three terminals which are
unregulated input (Vin), regulated output (Vo) and common or a ground
terminal. These regulators do not require any feedback connections.
Positive voltage regulators:
78xx is the series of three terminal positive voltage regulators in which xx
indicate the output voltage rating of the IC.
7805:
This is a three terminal regulator which gives a regulated output of +5V
fixed. The maximum unregulated input voltage which can be applied to
7805 is 35V.
7809:
This is also three terminal fixed regulator which gives regulated voltage
of +9V.
Negative voltage regulators:

79xx is the series of negative voltage regulators which gives a fixed

negative voltage as output according to the value of xx.
7912:
This is a negative three terminal voltage regulator which gives a output of
-12V.
Line Regulation:
It is defined as the change in the output voltage for a given change in the
input voltage. It is expressed as a percentage of output voltage or in
millivolts.
%RL = Vo/Vin x 100
Load Regulation:
It is the change in output voltage over a given range of load currents that
is from full load to no load. It is usually expressed in millivolts or as a
percentage of output voltage.
%R Load = [(Vnl-Vfl)/Vnl] x100
PROCEDURE:
1.
Connect the circuit as shown in the figure.
2.
Apply unregulated voltage from 7.5V to 35V and observe the
output voltage.
3.
Calculate the line and load regulation for the regulator.
4.
Plot the graphs from the observations.
5.
Repeat the same for the remaining regulators.

Result

PART -II

Experiment No.9
HDL code to realize all the logic gates

AIM: Write a VHDL code for all the logic gates.

Apparatus required:
Electronics Design Automation Tools used:
i)
ii)

Xilinx Spartan 3E FPGA +CPLD Board

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
from Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

#1-TITLE: AND gate

LOGIC GATE SYMBOL:

7408N
TRUTH TABLE:

#2-TITLE: OR gate

LOGIC GATE SYMBOL:

7432
TRUTH TABLE:
x

#3-TITLE: NOT gate

LOGIC GATE SYMBOL:

7404
TRUTH TABLE:
x

.
#4-TITLE: NAND gate
LOGIC GATE SYMBOL:

7400

TRUTH TABLE:

#5- TITLE: NOR gate

LOGIC GATE SYMBOL:

7402

TRUTH TABLE:

#6-TITLE: EX-OR gate

LOGIC GATE SYMBOL:

7486

TRUTH TABLE:

#7-TITLE: EX-NOR gate

LOGIC GATE SYMBOL:

74135
TRUTH TABLE:

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity loggates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (7 downto 0));
end loggates;
architecture Behavioral of loggates is
begin
z(0) <= a and b;
z(1) <= a or b;
z(2) <= a xor b;
z(3) <= a xnor b;
z(4) <= a nor b;
z(5) <= a nand b;
z(6) <= not a;
z(7) <= not b;
end Behavioral;

WAVEFORMS:

VIVA QUESTIONS:
1. Implement the following function using VHDL coding. (Try to minimize if you
can).
F(A,B,C,D)=(A+B+C) . (A+B+D). (B+C+D) . (A+B+C+D)
2.
3.
4.
5.

What will be the no. of rows in the truth table of N variables?

What are the advantages of VHDL?
Design Ex-OR gate using behavioral model?
Implement the following function using VHDL code
f=AB+CD.
6. What are the differences between half adder and full adder?
7. What are the advantages of minimizing the logical expressions?
8. What does a combinational circuit mean?
9. Implement the half adder using VHDL code?
10. Implement the full adder using two half adders and write VHDL program in
structural model?

Experiment No.10
Design of 2-to-4 decoder
AIM: Write a VHDL code for IC74138 -3X8 Decoder.
Apparatus required:

Electronics Design Automation Tools used:

i)

Xilinx Spartan 3E FPGA +CPLD Board

ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
from Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

BLOCK DIAGRAM:

TRUTH TABLE:
S.No

Enable inputs
g1
g2a_l g2b_l

Encoded inputs
A
B
C

Decoded
output
X

11111111

2
3
4
5
6
7
8
9
10
11

1
1
1
1
1
1
1
1
1
1

1
X
0
0
0
0
0
0
0
0

X
1
0
0
0
0
0
0
0
0

X
X
0
0
0
0
1
1
1
1

X
X
0
0
1
1
0
0
1
1

X
X
0
1
0
1
0
1
0
1

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ebytenc is
Port ( w : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (2 downto 0));
end ebytenc;
architecture Behavioral of ebytenc is
begin
process(w)
begin
case (w) is
when "00000001" => y <= "000";
when "00000010" => y <= "001";
when "00000100" => y <= "010";
when "00001000" => y <= "011";
when "00010000" => y <= "100";
when "00100000" => y <= "101";
when "01000000" => y <= "110";
when "10000000" => y <= "111";
when others => y <= "111";
end case;
end process;
end Behavioral;
WAVEFORMS:

11111111
11111111
01111111
10111111
11011111
11101111
11110111
11111011
11111101
11111110

VIVA QUESTIONS
:
1. Write the behavioral code for the IC 74x138.
2. Write the VHDL code for the IC 74x138 using CASE statement.
3. Write the VHDL code for the IC 74x138 using WITH statement.
4. Write the VHDL code for the IC 74x138 using WHEN--ELSE statement.
5. Write the structural program for IC 74x138.
6. What does priority encoder mean?
7. How many decoders are needed to construct 4X16 decoder?
8. What is the difference between decoder and encoder?
9. Write the syntax for exit statement?
10. Explain briefly about next statement?
11. How to specify the delay in VHDL program?
12. Write the syntax for component declaration.

Experiment No.11
Design of 8-to-3 encoder (without and with priority)
AIM: Write a VHDL code for IC74138 -3X8 encoder
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
from Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

TRUTH TABLE:

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

b : out STD_LOGIC_VECTOR (02 downto 0));
end encoder;
architecture Behavioral of encoder is
begin
process(a)
begin
case(a) is
when "00000001" => b <="000";
when "00000010" => b <="001";
when "00000100" => b <="010";
when "00001000" => b <="011";
when "00010000" => b <="100";
when "00100000" => b <="101";
when "01000000" => b <="110";
when "10000000" => b <="111";
when others => b <= "ZZZ";
end case;
end process;
end Behavioral;

WAVEFORMS:

Experiment No.12
Design of 8-to-1 multiplexer
AIM: Write a VHDL code for IC741518x1 multiplexer.
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
from Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

TITLE: IC741518x1 multiplexer.

BLOCK DIAGRAM:

PIN DIAGRAM 74151(8X1 MULTIPLEXER):

TRUTH TABLE:
S.No

en_l
B

Data select lines

C
0
0

Output
Y
I(0)

A
0

I(1)

I(2)

I(3)

I(4)

I(5)

I(6)

I(7)

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.all; use
ieee.std_logic_unsigned.all;
entity \8_1mux\ is port(
a : in STD_LOGIC_VECTOR(7 downto 0); s : in
STD_LOGIC_VECTOR(2 downto 0); y : out
STD_LOGIC
); end \8_1mux\;
--}} End of automatically maintained section
architecture \8_1mux\ of \8_1mux\ is begin
process(s,a) begin
case s is
when "000"=> y<= a(0); when
"001"=> y<= a(1); when "010"=>
y<= a(2); when "011"=> y<= a(3);
when "100"=> y<= a(4); when
"101"=> y<= a(5); when "110"=>
y<= a(6); when "111"=> y<= a(7);
when others =>null; end case;

end process;
end \8_1mux\;

VIVA QUESTIONS
:
1. Write the behavioral code for the IC 74x151.
2. Write the VHDL code for the IC 74x151 using IF statement.
3. Write the VHDL code for the IC 74x151 using WITH statement.
4. Write the VHDL code for the IC 74x151 using WHEN--ELSE statement.
5. Write the structural program for IC 74x151.
6. What is meant by multiplexer?
7. What does demultiplexer mean?
8. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
9. Compare decoder with demultiplexer?
10. Design a full adder using 8X1 multiplexer?
11. What are the two kinds of subprograms?

Demultiplexer
Demultiplexer: Demultiplexerisacombinationalcircuitthatacceptssingleinput
and distributes it to several outputs (Selectively distributes it to 1 of N output
channels)&Exactlyreverseofthemultiplexer.
EN

ENABLE

SEL(2)

INV3

SEL(1)

INV2

SEL(0)
INV1

EN
DataInput

O/P

1:8

0
1
2
3

Demux4

5
6
7

SEL0
SEL1
SEL2

D0
D1
D2
D3
D4

2 U1
3
4
5

2
3 U3
4
5

D6
D7

0
1
1
1
1
1
1
1
1

CONTROLINPUTS
SEL(3) SEL(3) SEL(3)
X
X
X
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

AND5
2 U5
3
4
5
6
AND5

2 U7
3
4
5
6

AND5

LogicDiagram

0
D0=Y
D1=Y
D2=Y
D3=Y
D4=Y
D5=Y
D6=Y
D7=Y

AND5

2 U8
3
4
5
6

OUTPUTS

2 U4
3
4
5
6

2 U6
3
4
5
6
AND5

DataOutputs

Truth Table

6 AND5

ControlInput

EN

AND5

2 U2
3
4
5
6
AND5

D5

BlockDiagramof1:8Demux

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity otedem is
Port ( x : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end otedem;
architecture Behavioral of otedem is
begin
process(s,x)
begin
case (s) is
when "000" => y(0) <= x;
when "001" => y(1) <= x;
when "010" => y(2) <= x;
when "011" => y(3) <= x;
when "100" => y(4) <= x;
when "101" => y(5) <= x;
when "110" => y(6) <= x;
when "111" => y(7) <= x;
when others => y <= "ZZZZZZZZ";
end case;
end process;
end Behavioral;

WAVEFORMS:

VIVA QUESTIONS:
1. Write the dataflow model for the IC 74x85.
2. Write the VHDL code for the IC 74x85 using CASE statement.
3. Write the VHDL code for the IC 74x85 using WITH statement.
4. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement.
5. Write the structural program for IC 74x85.
6. How many 4-bit comparators are needed to construct 12-bit comparator?
7. What does a digital comparator mean?
8. Design a 2-bit comparator using gates?
9. Explain the phases of a simulation?
10. Explain briefly about wait statement?

Experiment No.13
4-bit Binary to Gray converter
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii)
iii)

Model Simulation tool or Xilinx ISE Simulator tool

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
from Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

BinaryItisanumbersystem,whichhasonlytwostates0(high)and1(low)
GrayInGraycodeEverynewcodediffersfromthepreviousintermsofsinglebit
onlyonebitchangesbetweensuccessivenumbers.
Decimal
0
1
2
3
4
5
6
7
8
9
10
11

Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011

Gray
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110

13
14
15

1101
1110
1111

1011
1001
1000

12

1100

1010

B3
B2

G3
2

U3

G2

G1

G0

XOR2

B1

U2

3
XOR2

B0

U1

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating

XOR2

---- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;
entity btgcc is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end btgcc;
architecture Behavioral of btgcc is
begin
process(b)
begin
case(b) is
when "0000" => g <= "0000";
when "0001" => g <= "0001";
when "0010" => g <= "0011";
when "0011" => g <= "0010";
when "0100" => g <= "0110";
when "0101" => g <= "0111";
when "0110" => g <= "0101";
when "0111" => g <= "0100";
when "1000" => g <= "1100";
when "1001" => g <= "1101";
when "1010" => g <= "1111";
when "1011" => g <= "1110";
when "1100" => g <= "1010";
when "1101" => g <= "1011";
when "1110" => g <= "1001";
when "1111" => g <= "1000";
when others => g <= "ZZZZ";
end case;
end process;
end Behavioral;

WAVEFORMS:

Experiment No.14
IC 74x85 4-BIT COMPARATOR

AIM: Write a VHDL code for IC 74x85 4-bit comparator .

Apparatus required:
Electronics Design Automation Tools used:
i)

Xilinx Spartan 3E FPGA +CPLD Board

ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

BLOCK DIAGRAM:

PIN DIAGRAM 7485 (4 BIT COMPARATOR):

TRUTH TABLE:
S.No.

1
2
5

Cascade
inputs

Present input
condition
A>B A=B A<B

AGTBIN=1 X
1
AEQBIN=1 0
0
ALTBIN=1 X

X
0
1
0
X

X
0
0
1
X

AGTBOUT AEQBOUT ALTBOUT

1
1
0
0
0

0
0
1
0
0

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity \4bitcomparator\ is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
agtb : out STD_LOGIC; --gt=graeater than
altb : out STD_LOGIC; --lt =less than
aeb : out STD_LOGIC --e=equality
);
end \4bitcomparator\;
--}} End of automatically maintained section
architecture \4bitcomparator\ of \4bitcomparator\
is begin
process(a,b) begin
if a > b then agtb<='1';
altb<='0';
aeb<='0';
elsif(a < b) then
agtb<='0';
altb<='1';
aeb<='0';
else
agtb<='0';
altb<='0';
aeb<='1';
end if;

0
0
0
1
1

end process; end \

4bitcomparator\;

WAVEFORMS:
10

20

30

40

50

60

70

80

90

100

ns

a(3)
a(2)
a(1)
a(0)
b

b(3)
b(2)
b(1)
b(0) agtb altb aetb

VIVA QUESTIONS
1. Realize 4 bit comparator using data flow model.
2. Implement 4-bit comparator using case statement.
3. What would be the result if process statement with out sensitivity list is used?
4. Write a behavioral VHDL program for comparing 8 bit unsigned integers.
5. Write a Behavioral VHDL program for comparing 8 bit integers of various types.
6. Design a 16-bit comparator using 74x85 Ics.

8.IC7474A POSITIVE EDGE TRIGGERING D FLIP FLOP

AIM: Write a VHDL code for IC7474a positive edge triggering D flip flop.
Apparatus required:
Electronics Design Automation Tools used:
i)

Xilinx Spartan 3E FPGA +CPLD Board

ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

CIRCUIT DIAGRAM:

TRUTH TABLE:

VHDL CODE:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dflip is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
pr_l : in STD_LOGIC;
clr_l : in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end dflip;
architecture Behavioral of dflip is
signal pr,clr : STD_LOGIC;
begin
process(clr_l,clr,pr_l,pr,clk)
begin
pr <= not pr_l; clr <= not clr_l;
if (clr and pr) = '1' then q<='0';qn<='1';
elsif clr='1' then q<='0';qn<='1';
elsif pr='1' then q<='1';qn<='0';
elsif(clk'event and clk='1') then
q<=d;
qn<=not d;

end if;
end process;
end Behavioral;

WAVEFORMS:

Experiment No.16
Design Of Flip Flops: SR, D, JK, T
AIM: Write a VHDL code for IC7474a positive edge triggering J.K flip flop.
J.KFlipflop:
TheraceconditionsinSRFlipflopcanbeeliminatedbyconvertingitintoJ.K,
thedatainputsJandKareANDedwithQ\andQtoobtainS&Rinputs.
HereSR,T,orDdependingoninputs.
S=J.Q\
R=K.Q

VHDL CODE:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity jkflip is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
q : out STD_LOGIC;

qn : out STD_LOGIC);
end jkflip;
architecture Behavioral of jkflip is
signal ff : STD_LOGIC;
begin
process(clk,rst)
variable jk : STD_LOGIC_VECTOR(1 downto 0);
begin
if (rst='0') then
ff <= '0';
elsif(clk'event and clk='1') then
jk:=J&K;
case jk is
when "01" => ff <= '0';
when "10" => ff <= '1';
when "11" => ff <= not ff;
when others => ff <= ff;
end case;
end if;
end process;
q <= ff;
qn <= not ff;
end Behavioral;

WAVEFORMS:

TFlipflop
AIM: Write a VHDL code for IC7474a positive edge triggering T flip flop.
TFlipflop(ToggleFlipflop):OneverychangeinclockpulsetheoutputQ
changesitsstate(Toggle).AFlipflopwithonedatainputwhichchangesstatefor
everyclockpulse.(J=K=1inJQKFlipfloptheresultingoutputisTFlipflop).

VHDL CODE:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tflip is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end tflip;
architecture Behavioral of tflip is

signal ff : STD_LOGIC;
begin
process(clk,clr)
begin
if (clr='1') then
ff <= '0';
elsif(clk'event and clk='1') then

if (t='1') then ff<=not ff;

else ff <= ff;
end if;
end if;
end process;
q<=ff;
qb<=not ff;
end Behavioral;

WAVEFORMS:

VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x74.

2. Write the dataflow code for the IC 74x74.
3. What is the difference between sequential and combinational circuit?
4. What is a flip-flop?
5. Explain the functions of preset and clear inputs in flip-flop?
6. What is meant by a clocked flip-flop?
7. What is meant by excitation table?
8. What is the difference between flip-flop and latch?
9. What are the various methods used for triggering flip-flops?
10. Explain level triggered flip-flop?
11. Write the behavioral code for IC 74X74.
12. Write the syntax of IF statement?

9.4BIT COUNTER
AIM:To write the VHDL code for IC 74x93 4 -bit binary counter.
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

COUNTER:Counterisadigitalcircuitthatcancountsthenumberofpulses.Forbuildingthe
counters,Flipflopareused.
RippleCounter/Asynch

9.

TRUTH TABLE:
Q(3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

VHDL CODE:library IEEE;

OUTPUT
Q(2)
Q(1)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

Q(0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity upctrs is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end upctrs;
architecture Behavioral of upctrs is
begin
process(clk,rst)
begin
if (rst='1') then q<="0000";
elsif(clk'event and clk='1') then q<=q+1;
end if;
end process;
end Behavioral;

WAVEFORMS:

VIVA QUESTIONS:
1. Realize 4 bit counter using data flow model.
2. What is the purpose of IEEE unsigned library.
3. What is the difference of down to and up to.
4. Write a VHDL model for a 74HC192 synchronous 4 bit up/down counter.
5. Write a VHDL data flow model for 7493 IC.
6. Write a VHDL behavioral model for 7493 4 bit binary counter.
7. Write a VHDL structural model for 7493 IC.
8. Write a VHDL behavioral model for 74293 IC.
9. Write a VHDL structural model for 74293IC.
10. Write a VHDL data flow model for 74293IC.

Experiment No.15
Design of Full adder using 3 modeling styles
Apparatus required:
Electronics Design Automation Tools used:
i) Xilinx Spartan 3E FPGA +CPLD Board
ii)

Model Simulation tool or Xilinx ISE Simulator tool

iii)

Xilinx XST Synthesis tool or Leonardo Spectrum Synthesis Tool

iv)

Xilinx Project Navigator 13.2 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

v)

JTAG cable

vi)

Adaptor 5v/4A

Symbol:

Logic Diagram:

Truth Table:

VHDL CODE:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fullll is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : out STD_LOGIC;
c : out STD_LOGIC);
end fullll;
architecture Behavioral of fullll is
begin
s<= a(0) xor a(1) xor a(2);
c<= (a(0) and a(1)) or (a(1) and a(2)) or (a(2) and a(0));
end Behavioral;

WAVEFORMS:

VIVA QUESTIONS:

Starting the ISE Software :

For Windows users, start ISE from the Start menu by selecting:
Start

Programs

Xilinx ISE 7

Project Navigator
The ISE Project Navigator opens. The Project Navigator lets you manage the sources and
processes in your ISE project. All of the tasks in the Quick Start Tutorial are managed
from with in Project Navigator.
Stopping and Restarting a Session
At any point during this tutorial you can stop your session and continue at a later time.
To stop the session: Save all source files you have opened in other applications.
Exit the software (ISE and other applications).
The current status of the ISE project is maintained when exiting the
software.
To restart your session, start the ISE software again. ISE displays the contents
and state of your project with the last saved changes.
Accessing Help
At any time during the tutorial, you can access online help for additional information
about a variety of topics and procedures in the ISE software as well as related tools.
To open Help you may do either of the following:

1. Press to view Help for the specific tool or function that you have selected or
highlighted.-->F1
2. Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.
Creating a New Project in ISE
In this section, you will create a new ISE project. A project is a collection of all files
necessary to create and to download a design to a selected FPGA or CPLD device.
To create a new project for this tutorial:
1.Select
. The New Project Wizard appears.
File > New Project

2.First, enter a location (directory path) for the new project.

3.Type tutorial in the Project Name field. When you type tutorial in the Project Name field, a
tutorial subdirectory is created automatically in the directory path you selected.
4.Select from the Top-Level Module Type list, indicating that the top-level file in your HDL
project will be HDL, rather than Schematic or EDIF.
5.Click
Next
to move to the project properties page.
6.Fill in the properties in the table as shown below
Device Family:
CoolRunner XPLA3 CPLDs
Device:

xcr3128xl

Package:

TQ144

Speed Grade: -7
Top-Level Module Type:

HDL

Synthesis Tool:

XST (VHDL/Verilog)

Simulator:

ModelSim

Generated Simulation Language: or depending on the language you want VHDL

Verilog to use when running behavioral simulation.

When the table is complete, your project properties should look like the following:

7.Click Next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be created.
Creating an HDL Source
In this section, you will create a top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the
"Creating a VHDL Source" section below.

This simple AND Gate design has two inputs: A and B. This design has one output called C
1. Click New Source in the New Project Wizard to add one new source to your project.
2. Select VHDL Module as the source type in the New Source dialog box.
3. Type in the file name andgate.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Define the ports for your VHDL source.
In the Port Name column, type the port names on three separate rows: A, B and C.
In the Direction column, indicate whether each port is an input, output, or inout. For A and B,
select in from the list. For C, select out from the list.

7. Click Next in the Define VHDL Source dialog box.

8. Click Finish in the New Source Information dialog box to complete the new source file
template.
9. Click Next in the New Project Wizard.
10. Click Next again.
11. Click Finish in the New Project Information dialog box.
ISE creates and displays the new project in the Sources in Project window and adds the
andgate.vhd file to the project.

12. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL file
in the ISE Text Editor. The andgate.vhd file contains:
Header information.
Library declaration and use statements.
Entity declaration for the counter and an empty architecture
statement. 13. In the header section, fill in the following fields:

Design Name: andgate.vhd

Project Name: andgate

Target Device: xcr3128xl- TQ144

Description: This is the top level HDL file for an up/down counter.
Dependencies: None
Note: It is good design practice to fill in the header section in all source files.
14. Below the
end process

statement, enter the following line:

C <= A and B;
15. Save the file by selecting File > Save.
Checking the Syntax of the New Counter Module

When the source files are complete, the next step is to check the syntax of the design. Syntax
errors and typos can be found using this step.

1. Select the counter design source in the ISE Sources window to display the related processes in
the Processes for Source window.
2. Click the "+" next to the Synthesize-XST process to expand the hierarchy.
3. Double-click the Check Syntax process.
When an ISE process completes, you will see a status indicator next to the process name.

If the process completed successfully, a green check mark appears.

If there were errors and the process failed, a red X appears.

A yellow exclamation point means that the process completed successfully, but some
warnings occurred.

An orange question mark means the process is out of date and should be run again.

4. Look in the Cons ole tab of the Transcript window and read the output and status messages
produced by any process that you run.
Caution!
You must correct any errors found in your source files. If you continue without valid
syntax, you will not be able to simulate or synthesize your design.
Simulation
1. Double click Launch ModelSim Simulator in the Process View window.

2. Right Click

'a'

to open a context menu.

3. Select Force or Clock to add the signal.

4.

Define

the

Clock

or

Force

signal

to

load

appropriate

signal

5. Run the simulation by clicking the Run icon in the Main or Wave window toolbar.

6. Waveform can be observed in the wave window

7. Click the Run All icon on the Main or Wave window toolbar. The simulation continues
running until you execute a break command.

8. Click the Break icon. The simulation stops running.

9. To restart the simulation, click the Restart icon to reload the design elements and reset the
simulation time to zero. The Restart dialog that appearsgives you options on what to retain
during the restart. Click the Restart button in the Restart dialog.

Assigning Pin Location

1. Double-click the Assign Package Pins process found in the User Constraints process group.
ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File
(UCF). You will be prompted with the following message:

2. Click Yes to add the UCF file to your project. The counter.ucf file is added to your project
and is visible in the Sources in Project window. The Xilinx Constraints Editor opens
automatically.
3. Now the Xilinx Pinout and Area Constraints Editor (PACE) opens.
4. You can see your I/O Pins listed in the Design Object List window. Enter a pin location for
each pin in the Loc column as specified below:
A: p90
B: p91
C: p53

5. Click on the Package View tab at the bottom of the window to see the pins you just added.
Put

your

mouse

over

grid

number

to

verify

thepin

assignment.

5. Select File _ Save. You are prompted to select the bus delimiter type based on the synthesis
tool you are using. Select XST Default <> and click OK.
6. Close PACE.
Creating Configuration Data
The final phase in the software flow is to generate a program file and configure the device.
Generating a Program File
The Program File is a encoded file that is the equivalent of the design in a form that can be
downloaded into the CPLD device.
1. Double Click the Generate Programming File process located near the bottom of the
Processes for Source window. The Program File is created. It is written into a file called

andgate.jed: This is the actual configuration data.

Configuring the Device

iMPACT is used to configure your FPGA or CPLD device. This is the last step in the design
process. This section provides simple instructions for configuring a Spartan-3 xc3s200 device
connected to your PC.
Note: Your board must be connected to your PC before proceeding. If the device on your board
does not matchthe device assigned to the project, you will get errors. Please refer to the iMPACT
Help for more information. To access the help, select Help > Help Topics.
To configure the device:
1. Click the "+" sign to expand the Generate Programming File processes.
2. Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure
Devices dialog box is displayed.

3. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and click
Next.
4. Verify that Automatically connect to cable and identify Boundary-Scan chain is selected and
click

E-CAD LAB
Finish.
5. If you get a message saying that there was one device found, click OK to continue.
6. The iMPACT will now show the detected device, right click the device and select
New Configuration File.
7. The Assign New Configuration File dialog box appears. Assign a configuration file to
each device in the JTAG chain. Select the
andgate.jed
file and click Open.
8. Right-click on the counter device image, and select Program... to open the Program
Options dialog box.
9. Click OK to program the device. ISE programs the device and displays Programming
Succeeded if the operation was successful.
10. Close iMPACT without saving.

95
1