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A New Continuous PWM Strategy for Three-Phase

Direct Matrix Converter Using Indirect Equivalent Topology


S M Dabour, E M Rashad
Electrical Power and Machines Engineering Department,Tanta University, Egypt, emrashad@ieee.org

Keywords: Carrier-based PWM; matrix converter; indirect


modulation; voltage transfer ratio

fixed slope carrier signal instead of a variable slope carrier


signal.
The aim of this paper is to propose a new control scheme
using CPWM method including over-modulation mode to
increase the converter VTR. This solution is simple and more
efficient compared with the other techniques [5]-[7]. It is
based on indirect equivalent model of DMC, which assumes
the converter as a virtual rectifier followed by a VSI without a
dc-link. With this representation, the CPWM methods can be
applied for each stage independently. In the two stages,
sinusoidal PWM (SPWM) and modified SPWM (MSPWM)
by adding a zero-sequence signal (ZSS) are applied. The
resulted switching signals for each stage are combined using
indirect equivalent switching matrix to get the gating pulses
of the DMC. A detailed analysis of the proposed technique
has been presented. The modulation strategy is implemented
using Matlab/ Simulink. Then the algorithm is compiled to
real time system based on DS1104 card provided by
dSPACE. All steps of hardware design using discrete
semiconductor devices are given. Experimental results have
been obtained and compared with those obtained using the
analysis.

Abstract
This paper presents a new continuous carrier-based pulse
width modulation (CPWM) method to control three-phase
direct matrix converter (DMC). This technique is based on the
equivalent indirect scheme, which models the converter as
two independent stages to perform rectification and inversion
processes. With this representation, two CPWM methods of
the rectification process are proposed. In the inversion stage,
the well-known CPWM methods of the standard voltage
source inverter (VSI) have been applied. With these
techniques, a voltage transfer ratio (VTR) of 0.937 has been
achieved in the linear modulation mode. This value is higher
than the present attainable value of 0.866. The proposed
technique has been implemented using a laboratory setup.
Measured results showed the validity of the given analysis.

1 Introduction
Three-phase matrix converter (MC) is a direct three- to threephase converter. It was firstly introduced in 1976 [1]. Due to
the progress of the power electronics technology, MC
development is growing steadily. After almost three decades
of intensive research, the development of MC has been
involved in industrial applications. In 2008, Yaskawa
Company in Japan introduces the first product of three-phase
MC. However, the industrial use of this type of the power
converter is limited, because of two main reasons; reduced
VTR (< 1) and complicated control implementation. The
converter VTR can be increased by operating in the
overmodulation region [2-4]. Some of research work to solve
complexity of the converter control algorithm has been
published using direct and indirect MC topologies. A novel
carrier based PWM modulation method is proposed in [5] to
control DMC, which does not need any sector information for
calculating the duty-ratios, and the output voltage is
synthesized to 0.866 times the amplitude of the input voltage.
This scheme also allows the input power factor to be
controlled. In [6] the unsymmetrical triangular carrier signal
is compared to the modulating signals. The inverter stage is
controlled by a variable slope carrier signal. Thus, the
implementation of this technique is complicated. However,
[7] introduces carrier based PWM for indirect matrix
converter (IMC) by comparing the modulation signals with a

2 Three-Phase DMC Topology


The topology of a three-to three-phase DMC is comprised
from nine bi-directional switches (BDSs) as shown in Fig. 1.
These switches are connected so that any of the input phases
(A, B, and C) can be switched to any of the output phases; (a,
b, and c). The output voltages can be derived from the input
voltages using the switching matrix, S as follows;
va
SaA
vb = SbA
vc
ScA

SaB
SbB
ScB

SaC
SbC
ScC

vA
vB
vC

(1)

VA
VB

SaA

SbA

ScA

VC

SaB

SbB

ScB

SaC

SbC

ScC

Va
Vb
Fig. 1. Three-phase DMC topology

Vc

The same performance of the DMC can be achieved in


practice using an indirect equivalent configuration as shown
in Fig. 2. It consists of two stages, a bi-directional controlled
three-phase rectifier followed by a three-phase VSI. Using
such hypothetical configuration the switching matrix of the
DMC, S can be derived from product of switching matrix of
the rectifier stage, R and of the inverter stage, I as follows;
S=IR
SaA
SbA
ScA

On the other hand, to obtain a maximum possible dc-link


voltage from the supply, each switch in the upper group must
be turned on when the corresponding input phase voltage is of
the higher than the other phases at the instant considered. In
contrary, each switch in the lower group must be turned on if
the corresponding input phase voltage is of the lower than the
other phases at the instant considered.
The modulating signal for each switch (1 to 6, where j is
the modulating signal of switch Sj and j=1 to 6) can be
obtained by assuming that the input phase voltages of the MC
are balanced and has a frequency of i as given by;
vA = Vim sin(i t)
vB = Vim sin i t 2/3
= 4/3
(6)
In this scheme, the rectifier modulating signals are chosen as
in (7) to synthesize sinusoidal input current with controllable
power factor, where k is a suitable constant and is the input
displacement angle.

(2)

SaB
SbB
ScB

SaC
S7
SbC = S9
ScC
S11

S8
S10
S12

S1
S2

S3
S4

S5
S6

(3)

3 Proposed PWM Technique


The proposed PWM technique is based on the indirect
equivalent configuration of the DMCs. Therefore, it is
necessary to find a set of modulating signals for each stage.
Each set is compared with its own carrier wave to obtain the
PWM signals which are combined to get the gating signals of
the DMC switching matrix.

1
3
5

3.1 Rectifier-Side Control (RSC)

where
T

S1
S2

S3
S4

S5
. vA
S6

vB

vC

(4)

S2

S4

S6

Rectifier Stage

(9)

Rectifier Side Modes of Operation and Boundaries


There are three modes of operation of the rectifier stage
namely; linear, overmodulation (RSO) and six-pulse mode.
The choice of rectifier duty ratio D in (9) determines the dclink voltage and consequently the modes of operation.

S7 S9 S11

va
vb
vc

VDC

(7)

where, D is the rectifier duty ratio and equals 3kVp. The


waveforms of the new modulating signals at D=2 are shown
in Fig. 3.

Magnitude

vA
vB
vC

5,6 = 1/3 1 D sin i t 4/3 +

Vp
+
S5

sin(i t + )
sin(i t 2/3 + )
sin(i t 4/3 + )

3,4 = 1/3 1 D sin i t 2/3 +

where vp and vn are the voltages at the dc-link rails. It is


clearly seen from (4) that, the rectifier switches are divided
into two groups; namely upper {S1, S3, S5} and lower {S2, S4,
S6} groups. Three switches in a group connect all input
phases to one terminal of the dc-link. To avoid short-circuits
on input phases or open-circuit on the dc-link, only one
switch in a group must be turned on at a time. This means;
S1 + S3 + S5 = 1
S2 + S4 + S6 = 1
(5)

S1 S3

vp
= v
n

Application of Offset Duty Ratio


It has clearly seen that, the above choice of rectifier
modulating signals in (7) does not satisfy the condition in (5).
Therefore, an offset duty ratio must be added to satisfy this
condition. A constant 1/3 may be added to each modulating
signal to satisfy these constraints. The new signals are;
1,2 = 1/3(1 D sin i t + )

vpn = R . vin

vn

To deduce the optimum value of k, substitute the value of


each modulating signal from (7) into its corresponding switch
(4), and after some trigonometric manipulations, the optimum
value of k is given by;
k = 2/(3Vim cos)
(8)

The rectifier stage has to generate a virtual dc-link voltage


(Vdc) from the input three-phase supply. The ratio between Vdc
to the maximum value of the input phase voltage (Vim) is
defined as a rectifier-side VTR (MR). The virtual dc-link
voltage is built by chopping the input three-phase voltages.
This operation is performed by the rectifier switching matrix,
R so that;

vp

2
4
6

0.5

S8 S10 S12
Vn

0
0

0.005

0.01

0.015

0.02

Time (msec)

Inverter Stage

Fig. 3 Rectifier side modulating signals using SPWM at D=2.

Fig. 2 Indirect equivalent representation of DMC

The boundaries of these modes are based on the following


considerations:
- The three-phase supply is balanced with line voltages of
3Vim magnitude. The space vector diagram of three-phase
system is shown in Fig. 4.
- The waveform of the dc-link voltage envelope has a
fundamental frequency of six times input frequency and a
peak value of 3 times Vim as shown in Fig. 5.
- The vector length of the inner circle in the space vector
diagram corresponds to the maximum dc-link voltage
available in the linear modulation region. The vector
length of the outer circle is the peak input line voltage.
However, the maximum available dc voltage can be
determined from the waveform of Fig. 5 and given as
follows;

This results in a flat-topped waveform and reduces the


amount of overmodulation. By injecting ZSS with third
harmonic voltage with triangular waveforms (v3h), the new
modulating signals becomes as follows;
1,2 = 1/3(1 D sin i t + + v3h )
3,4 = 1/3 1 D sin i t 2/5 + + v3h
5,6 = 1/3 1 D sin i t 4/5 + + v3h

(11)

where,
v3h = 1/2(vmax + vmin )

(12)

It was found that for this technique, the limit of the linear
modulation region is extended to 1.62Vim. The simulation
result of the modulating signals using this scheme is shown in
Fig. 6.

2
6
Vdc _max =
v d i t = 1.654Vim
2/6 0 CB
vCB = 3Vim cos i t

Fig. 7 shows the rectifier side control characteristic for


SPWM, and PWM with ZSS. The range of linear part of the
input side control characteristic for SPWM ends at MR=3/2
(D=2). The PWM with ZSS provides extension of the linear
range up to MR =1.62. For MR>1.62, the rectifier is in overmodulation range. Fig. 8 gives the flowchart of the proposed
algorithm. These modulating signals S1-S6; are compared with
a common unipolar carrier signal whose frequency is much
higher than the frequency of the duty cycles (input side
frequency of supply frequency). The results of the
comparison are the switching signals of each switch of the
rectifier stage. The resulting switching signals of the rectifier
switches are shown in Fig. 9 for RSC using PWM with ZSS
at D=2. It is clearly show that, the operation of the rectifier
switches by this algorithm did not allow supply short circuits
and the resulting operation sequence are; S5S4, S1S4, S1S6,
S3S6, S3S2 and S5S2.

(10)

where, VCB is the instantaneous line voltage between input


phase C and B. Hence, the value of 1.654Vim is the
maximum virtual dc-link voltage that can be obtained
when the rectifier stage is in six-pulse mode and it
behaves as a three-phase diode bridge rectifier.
Application of Zero Sequence Signal Injection
The range of linear mode of the rectifier stage can be
increased using the principle of ZSS injection employed in
the three-phase VSI.

Vi
1 .5

VC

R2
R3

Magnitude

1
R1
VA

R4
3

V im

0
0

0.005

R6

0.01

0.015

0.02

Fig. 6 Rectifier side modulating signals using PWM with ZSS


at D=2.
X: 2
Y: 1.62

1.654

vCB

X: 2
Y: 1.5

PWM
THI-PWM
THIPWM
with
ZSS
SYPWM

1.732
1.654

M
Mc
c

Magnitude

Time (msec)

Fig.4 Space vector diagram of a three-phase voltages system

1.5

0.005

SPWM
SPWM

Six Step
Limit

Linear
Limit
0

0.5

VB
R5

0.01

0.015

Linear

Six
Pulse

Overmodulation

0.02

0
-2

Time (msec)

-1

2 2.5
DD

Fig. 5 The waveform of the dc-link voltage envelope

Fig. 7 Rectifier side control characteristic.

3.2 Inverter-side control (ISC)


S1

The CBPWM techniques in the standard voltage source


inverter are well known and reported in many researcher
works such as [12-13]. However, it has been implemented
here to modulate the inverter stage.

S2

0
1
0
1
S3

START
K=1

0
1
S4

Read
va,vb,vc

0
1
vc > vb

v3h=-0.5vc

S5

Yes

Yes

va >vb &vc

R=1

0
1

Yes

v3h=-0.5vb

R=2

v3h=-0.5va

R=3

v3h=-0.5vc

R=4

v3h=-0.5vb

R=5

S6

No

No

0
0

Yes

vb > va & vc

va > vc

va = Vom sin(o t)
vb = Vom sin o t 2/3
vc = Vom sin o t + 2/3

No

v3h=-0.5va

vx**=vx*+v3h

R=6

x {a,b,c}

Yes

dx < 0

Sinusoidal PWM

R=1

Sinusoidal PWM is the most popular and widely used CPWM


technique because of its simple implementation in both
analogue and digital realization. It can be executed, if vzss
equals zero. The modulating signal waveforms, ei are purely
sinusoidal. As a result, the maximum possible inverter side
VTR, MI is 0.5 if the inverter operates in linear mode.
However, the value of 0.636 is the maximum available VTR
in the overmodulation region (ISO).

R=6
Test R

d1=1/3(1+D.va**)

d5=1/3(1+D.vc**)

d4=1/3(1-D.vb**)

d4=1/3(1-D.vb**)

PWM Modulator
S2

S3

S4

S5

Symmetrical PWM
In order to increase the output voltage level in the linear mode
of the inverter stage, the ZSS can be applied. For SYPWM
the ZSS can be determined as follows [13];

S6

Fig. 8 Flowchart of the RSC using PWM with ZSS.

vzss =

The inverter side VTR (MI) is defined as the ratio between the
peak value of the output phase voltage (Vom) and the average
value of the virtual input dc voltage. A general representation
of the inverter modulating signals ei (i=a, b and c) for threephase carrier PWM modulators is as follows;
ei = vi + vzss

(14)

dx = 0

No

S1

T/2

These inverter modulating signals, ei are compared with a


common triangular carrier signal whose frequency is much
higher than that of the modulating signal. The result
represents the switching signals of each leg of the inverter
stage. Two schemes of CPWM technique are employed;
Sinusoidal PWM (SPWM) and Symmetrical PWM
(SYPWM).

x {a,b,c}

dx=1/3(1D.vx**)

k=k+1

3T/4

where vzss is the injected zero sequence signal, and vi* is called
sinusoidal reference signal and it is defined as a function of
the output frequency (o) as follows;

Yes

vb > va

Duty cycle
limiter

T/2

Fig. 9 RSC switching signals using PWM with ZSS.

No

No

T/4

1
2

vmin
+ vmax

where
= , ,

(15)
and

= , ,

Using this scheme, the maximum possible inverter side VTR,


MI is increased to 0.577 in linear mode.

(13)

4. Direct Matrix Converter Modulator

5.2 Experimental Results

4.1 DMC Gating Signals

To testify the converter behavior, the output phases (a-c) are


connected to the passive load (100 and 0.25 H). A small
input line voltage supply of 100 V at 50 Hz is applied. Fig.10
gives experimental waveforms of output line-voltages (upper
trace) and phase-voltages (bottom trace) at frequency of 10
Hz. Both stages are in linear mode (MR=2 and MI=0.95). Fig.
11 shows the experimental waveforms of the load currents
(upper trace) and its spectrum analysis (bottom trace). The
load currents are near sinusoidal due to load inductive nature.

Once the switching signals of the two stages have been


derived, the gating signals of the implemented 53 DMC can
be determined considering the switching matrix given in (3).
4.2 Maximum VTR of 53 Direct Matrix Converter
There are two VTRs to be controlled in this technique; MR
and MI. The overall VTR of the 33 DMC (M) equals the
product of the two VTRs (M=MRMI). The resulting overall
VTRs due to the proposed technique are given in Table I. It
has clearly seen that, the OM operating region is classified
into three different modes based on the choice of the rectifier
and inverter stages modulating signals. These modes are
Rectifier-Side OM (RSO), Inverter-Side OM (ISO) and Both
Sides OM (BSO). The maximum VTR equals 1.053 for BSO
operation mode. When the SPWM is applied in both sides the
maximum VTR of the converter is 0.75. Owing to the
application of ZSS in the inverter side only, the converter
VTR is 0.866. This VTR is as that of space vector modulation
techniques [4], [7], [10]. Due to the application of ZSS in
both sides, the VTR of the linear mode is increased to 0.937.
This result represents the maximum obtainable of this MC
topology using this technique in linear mode.

vab

vbc

va

5 Experimental Setup and Results


5.1 Experimental Setup
The switching matrix of the DMC is realized by 9-BDS, each
is composed of a diagonal power MOSFET (IRFP460A) and
a bridge of fast recovery diodes (BY229F). The employed
MOSFET has the following characteristics; voltage blocking
capability is 500V, current capacities is 20A, integral
freewheel-diode, no clamp circuit required, low switching
losses, and total turn on and turn off times 77 and 168 ns
respectively. The fast recovery diodes are with reverse
recovery time of less than 135 ns. The gate driver circuit is
based on a high-speed optocoupler device (6N137) with a
typical 50 and 12 ns rise and fall time respectively. Therefore,
it is very suitable for MC applications.

vb

Fig. 10. Experimental waveforms for output side linevoltages (top trace) and phase-voltages (bottom trace) for
peak input voltage of 100V and output frequency of 10Hz
where both stages are in linear-mode.
ia
ib

The control system is based on the DS1104 controller.


Furthermore, it has been implemented using Matlab/Simulink
and then compiled to real time system. Measurements are
obtained using a digital scope and a current probe (HAMEG
HM-407 and HZ-56). All experimental results have been
obtained using a switching frequency of 1-kHz and sampling
time of 200sec. The reference input current displacement
angle adjusted to zero, which achieves maximum VTR.
(MI)
(MR)
SPWM
With ZSS
RSO

1.5
1.62
1.654

SPWM
0.5
0.75
0.81
0.827

With ZSS
0.577
0.866
0.937
0.955

0.5A/Div

ISO
0.636
0.955
1.03
1.053
Fig. 11. Experimental waveforms for output line-currents
(top trace) and its spectrum (bottom trace) for linear-mode.

Table I. Matrix converter VTR of the proposed technique

Finaly, the developed MC is tested for over-modulation mode


when BSO operation. Figs. 12 and 13 show the output line
and phase voltages and the currents waveforms at output
frequency of 10 Hz. It can be found that, at BSO operation an
amount of the lowest order harmonics specially 5th and 7th
harmonics are introduced.

5 Conclusions
In this paper a new CPWM scheme of the three-phase DMC
is presented. This method based on the indirect equivalent
model of DMC. The maximum possible VTR of the DMC
using this technique is found to be 1.03 with inverter stage
over-modulation only, 0.955 with rectifier stage overmodulation only and is 1.053 with both rectifier and inverter
stages overmodulation, whilst, the total harmonic distortion of
the output current and the lowest order harmonics are
increased. Moreover, the voltage transfer ratio can be
increased to 0.937 with simultaneous input and output in
linear mode. In addition, the proposed scheme allows the
input power factor to be controlled. The theoretical analysis
of the proposed modulation scheme is confirmed by
experimental results.

vab

vbc
vbc

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[1]

va

vb

Fig. 12. Experimental waveforms for output line (top trace)


and phase-voltages (bottom trace) for BSO operation.
1A/Div

ia

ib

Fig. 13. Experimental waveforms for output line-currents


and its spectrum analysis for BSO operation