Altera Max-Plus tutuorial

a) Design creation and compilation

1. From the start menu, select Altera>MAX+Plus

2. In order to select your target device, you have to assign the required family. In
Max+Plus || Manager, select assign>device. Then select FLEX10KE from the
Device Family combo box. Be sure that the Devices are in the AUTO mode not a
specific chip (this enables the compiler to select the suitable device to your
design). Finally, click OK

3. from the Options tab in MAX+plus Manager, select color Palette and convert the
color of the Reserved Keywords to be red as shown, click OK

4. To create new VHDL file, click File>new. You should get the shown window.
The VHDL file is a simple text file. Other types will be used later.

5. Save the text file as a VHDL file with the same name of the Entity. It is a must in
Altera MAX+Plus. So, go to File>Save As. Select the required directory in the
Directories sub-tab. Then, write HalfAdder.vhd in the File name. you can just
write HalfAdder without the extension in case of selecting .vhd in the Automatic
Extension at the end of the window as shown, click OK

6. After saving the file, go to file tab, and select project>Set project to current file.
This will force Max+Plus to compile and simulate the current file. Note that
without this step, Max+Plus will compile the last opend file.

7. Write the VHDL implementation in the text file. For the first time, just write the
HalfAdder code as shown, then save the file by clicking Save not Save As.

8. In order to compile the design and check the syntax, from the MAX+Plus II at the
top left of the window, select compile

9. click start in the compile window and notice the messages after compilation.

10. In case of correct code, you should see the following window.

b) Design Simulation
1. First of all, you have to create a waveform file (.scf). This is done by
File>new. Then selecting the last choice and click OK

2. Save the file by only clicking Save or select Save As and write the entity
name followed by .scf in the file name.

3. The waveform editor will be opened. To insert the required signals in the
editor, select node>Enter nodes from SNF (the precompiled file that has
all details about the component ports)

4. The asterisk (*) in the Node/Group means all ports, so click the list botton
and all ports will be displayed in the Available Nodes & Groups box.
Mark them all and select them from the arrow at the middle of the
window.

5. Now the nodes are displayed in the waveform editor. To adjust the nodes
values, first select the first port by just single click by the mouse. Then,
click the Count button that is now activated.

6. You will notice the following window, just click OK.

7. Now, select the second input and click the count again. Here, you have to
multiply the time period by two in order to make this node slower than the
first one by 2.

8. Save the file and then click the simulator in the MAX+Plus II tab

9. The simulator will simulate the design and gives you the output (are they
correct?). Notice the glitches in the Sum output (why glitches?)

c) The Area, Delay, and Place and route for our design
1. To know the number of logic cells (LC), the number of memory bits taken
by the design, open the report file as shown.

2. To know the component delay or the frequency of the clock in case of

sequential circuits, open the Timing analyzer.

3. Click start in the Delay matrix and the delay between every input and
every output will be displayed in this matrix as shown.

4. To know where MAX+Plus places the logic cells, and each cell is
connected to what input or output, view the FloorPlan editor.

5. In the FloorPlan, you can click on any cell to know exactly its sources and
destinations. You can either select
to view the destinations.

to view the sources, or select