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sequential logic.
In combinational circuit outpus depends only on present inputs.
In sequential circuit, output depends upon both present and
previous inputs/outputs.
because of this sequential ckt hae memory to store the previous
inputs.
Hence sequential ckt always contains a memory element or a
feedback from output to input or boyh.
Clocked S - R Latch
Clocked S - R Latch
(continued)
T-flip flop
Flip-Flop Problem
The change in the flip-flop output is
to 0 with R remaining at 0
The master latch sets to 1
A 1 is transferred to the slave
Chapter 5
- Part 1
12
Flip-Flop Solution
Use edge-triggering instead of master-
slave
An edge-triggered flip-flop ignores the
pulse while it is at a constant level and
triggers only during a transition of the
clock signal
Edge-triggered flip-flops can be built
directly at the electronic circuit level, or
A master-slave D flip-flop which also
5
exhibits edge-triggered behavior can beChapter
- Part 1
13
used.
Edge-Triggered D FlipFlop
The edge-triggered
D flip-flop is the
same as the masterslave D flip-flop
C
C
Formed by
adding inverter
to clock input
C
C
Q changes to the value on D applied at the positive clock edge within timing constraints to be specified
SR
Master-Slave:
Dynamic
indicator
Postponed output
S
indicators
Edge-Triggered:
SR
Triggered SR
Triggered SR Triggered D
(b) Master-Slave Flip-Flops
Triggered D
Triggered D
Triggered D
(c) Edge-Triggered Flip-Flops
Chapter 5
- Part 1
16
Registers
4-bit Register
Shift Register
Shift Register
Ripple Counter
Synchronous Counter
All flip-flops have a common clock & are
synchronized
Flip-flop
in
lowest-order
position
is
complemented with every pulse.
Lowest flip-flop has J=K=1
Chain of AND gates generates the required
logic for the J & K inputs in each stage
The counter can be extended to any number
of stages, with each stage having an
additional flip-flop and an AND gate that gives
an output of 1 if all previous flip-flop outputs
are 1s