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Time Borrowing
In a system using flip-flops, data departs the first flop on the rising edge of
the clock and
must set up at the second flop before the next rising edge of the clock. If
the data arrives
late, the circuit produces the wrong result. If the data arrives early, it is
blocked until the
clock edge, and the remaining time goes unused. Therefore, we say the
clock imposes a
hardedgebecause it sharply delineates the cycles.
In contrast, when a system uses transparent latches, the data can depart
the first latchon the rising edge of the clock, but does not have to set up
until the falling edge of theclock on the receiving latch. If one half-cycle or
stage of a pipeline has too much logic, itcan borrow time into the next
half-cycle or stage, as illustrated in Figure 10.12(a)[Bernstein99]. Time
borrowingcan accumulate across multiple cycles. However, in systemswith
feedback, the long delays must be balanced by shorter delays so that the
overall loopcompletes in the time available. For example, Figure 10.12(b)
shows a single-cycle selfbypass loop in which time borrowing occurs
across half-cycles, but the entire path must fitin one cycle.
A typical example of a self-bypass loop is the execution stage of a
pipelinedprocessor in which an ALU must complete an operation and
bypass the result back for usein the ALU on a dependent instruction. Most
critical paths in digital systems occur inself-bypass loops because
otherwise latency does not matter.Figure 10.13 illustrates the maximum
amount of time that a two-phase latch-basedsystem can borrow (beyond
the Tc/2 tpdqnominally available to each half-cycle of logic).
Because data does not have to set up until the falling edge of the
receiving latchs clock,
one phase can borrow up to half a cycle of time from the next (less setup
time and nonoverlap):
Time borrowing has two benefits for the system designer. The most
obvious is intentional time borrowing, in which the designer can more
easily balance logic betweenhalf-cycles and pipeline stages. This leads to
potentially shorter design time because thebalancing can take place
during
circuit
design
rather
than
requiring
changes
to
themicroarchitecture to explicitly move functions from one stage to
another. The other benefit is opportunistic time borrowing. Even if the
designer carefully equalizes the delay in eachstage at design time, the
delays will differ from one stage to another in the fabricated chipbecause
of process and environmental variations and inaccuracies in the timing
model usedby the CAD system. In a system with hard edges, the longest
cycle sets the minimumclock period. In a system capable of time
borrowing, the slow cycles can opportunisticallyborrow time from faster
ones and average out some of the variation.
Some experienced design managers forbid the use of intentional time
borrowing untilthe chip approaches tapeout. Otherwise designers are
overly prone to assuming that theirpipeline stage can borrow time from
adjacent stages. When many designers make this same assumption, all of
the paths become excessively long. Worse yet, the problem may be
iddenuntil full-chip timing analysis begins, at which time it is too late to
redesign so many paths.Another solution is to do full-chip timing analysis
starting early in the design process.