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  • Latch-Up in CMOS

    Transféré par

    Shreya Verma
    122 vues4 pages
    1) Latch-up can occur in CMOS devices due to the presence of parasitic bipolar junction transistors (BJTs). A spike at the output of a CMOS inverter can turn on these parasitic BJTs and allow current to flow in a cycle that cannot self-terminate. 2) This occurs because the lightly doped n-well and p-substrate layers offer high resistance, allowing the voltages at these nodes to shift beyond normal transistor thresholds. 3) Increasing the doping concentration deep in the n-well and p-substrate regions can reduce their resistance and prevent the parasitic BJTs from turning on, thereby solving the latch-up issue.

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    Latch-Up in CMOS

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    1) Latch-up can occur in CMOS devices due to the presence of parasitic bipolar junction transistors (BJTs). A spike at the output of a CMOS inverter can turn on these parasitic BJTs and allow current to flow in a cycle that cannot self-terminate. 2) This occurs because the lightly doped n-well and p-substrate layers offer high resistance, allowing the voltages at these nodes to shift beyond normal transistor thresholds. 3) Increasing the doping concentration deep in the n-well and p-substrate regions can reduce their resistance and prevent the parasitic BJTs from turning on, thereby solving the latch-up issue.

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    122 vues4 pages

    Latch-Up in CMOS

    Transféré par

    Shreya Verma
    1) Latch-up can occur in CMOS devices due to the presence of parasitic bipolar junction transistors (BJTs). A spike at the output of a CMOS inverter can turn on these parasitic BJTs and allow current to flow in a cycle that cannot self-terminate. 2) This occurs because the lightly doped n-well and p-substrate layers offer high resistance, allowing the voltages at these nodes to shift beyond normal transistor thresholds. 3) Increasing the doping concentration deep in the n-well and p-substrate regions can reduce their resistance and prevent the parasitic BJTs from turning on, thereby solving the latch-up issue.

    Droits d'auteur :

    © All Rights Reserved
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 4

    3/12/2015

    LatchUpinCMOS|VLSISoCDesign

    18thOctober2014

    LatchUpinCMOS

    CMOSdeviceisoftenportrayedtobeanimpeccabledevice,especiallyinthe
    textbooks.TherearesomeinnateproblemsintheCMOSdeviceandoneofthem
    isthelatchup.We'regonnatalkaboutitindetail.
    ConsiderthecrosssectionofaCMOSinverter.PleasenotethatIhaveskipped
    drawingsomemetallayersandcontactsforthesakeofsimplicity.Myfocusison
    explainingtheproblemoflatchupandnotthelayoutdesignrules!

    [http://4.bp.blogspot.com/RiB4Vq_8SOE/VEGTw5vpIBI/AAAAAAAAD18/FTb
    _SMJHWE/s1600/Fig1.png]
    Figure1:CMOSwithparasiticBJTs

    Intheabovecrosssection,notethat123formaparasiticpnptypebipolar
    junctiontransistor,while432formaparasiticnpnbipolarjunctiontransistor.
    SinceparasitictransistorswouldbepresentineveryCMOSdevice!Asimplistic
    figuredepictingtheseparasitictransistorsisgivenbelow:

    http://vlsisoc.blogspot.com/2014/10/latchupincmos.html

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    [http://2.bp.blogspot.com/
    akfXAV33bM0/VEGT4mbUwaI/AAAAAAAAD2E/AjEiNTbLKD4/s1600/Fig2.png]
    Figure2:SimplisticFiguredepictingparasiticBJTs

    Here,thenpnandthepnptransistorsaredepictedwith2and3beingcommon
    betweenthetwotransistors.Alsonotethatthenwelllayerandthepsubstrate
    atelightlydopedlayers,andhenceoffergreaterresistanceascomparedtothe
    n+,p+drainandsourceregions.ThenwellresistanceofPMOSisdepictedby
    theresistorR2andtheresistanceofpsubstrateisdepictedbytheresistorR1.
    Let'ssay,we'vegotaspikeattheoutputoftheCMOSinverter.
    1. Thisisanegativespike(orabump),whichdecreasesthepotentialofVOUT
    belowgroundpotentialby0.7V.
    2. Asaresult,thenpntransistor432getsturnedON,andtheemitter(n+,4)
    startsemittingelectrons,whicheventuallygetcollectedatthecollector(n
    well,2)andgointoVDD.
    3. Thecurrenthenceflowsinthereversedirectionfromthen+bodytowards
    thenwellregion.
    4. Wewillhaveavoltagedropinthedirectionofcurrent,asaresultthe
    potentialatthenwellcanreach0,7VbelowVDD.Thisturnsthepnp
    transistorON,becausep+regionemitterisatVDD!
    5. Thecurrentiscollectedatthecollector(psubstrate,3)andflowsintothe
    groundthroughthep+bodyregion.
    6. Goingoppositetothedirectionofcurrent,thepotentialdifferenceincreases,
    andthevoltageatpsubstrate(justbelowthen+ofNMOS,mightreach0.7V,
    therebyinjectingmorecurrent!

    http://vlsisoc.blogspot.com/2014/10/latchupincmos.html

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    [http://4.bp.blogspot.com/
    uljDInmPbKI/VEGT_qfHbEI/AAAAAAAAD2M/XZJTLK3foVg/s1600/Fig3.png]
    Figure3:Sequenceofeventsleadingtolatchup

    Asevidentfromtheabovesteps,justonespikeattheoutputinitiatesachain
    reactionresultingincurrentflowthroughthedeviceincessantly,andhencethe
    devicegetswornoutinaveryshortspanoftime!Thisisthelatchup!
    Howtomitigatetheproblem?
    Well,aswejustnoticed,themaincauseoflatchupwastheresistanceofnwell
    andthepsubstratelayers.Hence,themostlogicalsolutionwouldbetoincrease
    theirdopingconcentrationbyionimplantation.Butthatwoulddeterioratethe
    transistoroperation!Remember,weneedtokeepthedopingofwellsand
    substratelowwhilethoseofsourceanddrainhighyoensureagoodtransistor
    operation.
    Whatdowedonow?
    Well,weshallstickwithionimplantation,butinsteadofdoingitnearthesilicon
    surfaceandhencenearthedrainandsource,implantadeepnwellwithhigh
    dopingconcentration,andsimilarly,implantadeeppwellinsidethepsubstrate
    toreducetheresistanceandhencekilltheparasticBJTaction!

    References:
    LatchupinCMOS,NPTELlecturesbyDr.NanditaDasgupta.

    Posted18thOctober2014byNamanGupta
    Labels:CMOS,LatchUp,LatchUpinCMOS,ParasiticBJTs
    1 Viewcomments

    HimanshuMangal October18,201410:50am
    NiceArticle
    Reply

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